From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 384343148DA for ; Tue, 28 Apr 2026 15:18:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777389487; cv=none; b=uRvVE58V+0ckNLtKga9fHFHjnXAesJEi3utyFNI6CkYR9Xfm2uuQ8l8qFEFuPjoNoZ5c48aaTGK8i6Qoj0JWKyfGTQWFb6S0SXD+NEe1FMhRO6jVSamZWtNa5ZsK+MLwp+8zJ7k4UR5VZMTglXyhzt45hN6zaVErFaeFMag0Sj0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777389487; c=relaxed/simple; bh=G5jYe2Ro6yI72cEA7e8A3BYucfWE+49wWIUVMxyffVQ=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=ptb14a2lxHz+4C1/gv74mNtehwYqO9SdWRDuD4lBH5NUQE25wtOQhgqaj6X4zSjvxsnbufBAc813P5O5wSCs+tqo7Kd+iu4lVAyMo10fZ2gitVNC4erxYaCsddH7KYtCpBV5NAdANyYUkvzMfVwv4h1O02/w0PNHbubBfn/IGGw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Pd5rgNeY; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Pd5rgNeY" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777389485; x=1808925485; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=G5jYe2Ro6yI72cEA7e8A3BYucfWE+49wWIUVMxyffVQ=; b=Pd5rgNeYTwuQHVQoycBLXQVO0iR4xR7C3JJfj5TkLSFeWq1vXlgmadQ3 ifMqwgfdwtxUDmJonhs9M2rjCZGeJ74jy6tM1m63oCJrEAFAQJHF+DnyP aj2rhUPg3hz1AsdgnWxEeKJhye+z2NodmdUhtknjEQNGjEfOxfJvVZHGi j7iu5ft3y9yjl86j5R3YJ7r3+1PCI5DWRB7jqrmXL9x9C96/Cn8fsBOso rE9GOim+nQfZ+jx+nbsJWF2c9OkaXETRKYzm1MZaRutDDEr9Bmg9rlLAL tLQ/QmJg0RmYtF5MuQgc2vorFYPBPXj30IxiAuJCa1Yoj4nGG02C7hOi5 g==; X-CSE-ConnectionGUID: VkKiOB5dTEmUGOHLpmkd3Q== X-CSE-MsgGUID: 62morNYWT7+b4uLj/60Wkw== X-IronPort-AV: E=McAfee;i="6800,10657,11770"; a="89761941" X-IronPort-AV: E=Sophos;i="6.23,204,1770624000"; d="scan'208";a="89761941" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2026 08:18:04 -0700 X-CSE-ConnectionGUID: ELNJMs58Q4eN7enpR34rLw== X-CSE-MsgGUID: 19SBxFJzRG6Q9sTks8Qczw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,204,1770624000"; d="scan'208";a="257302027" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.30]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2026 08:18:02 -0700 Date: Tue, 28 Apr 2026 17:18:00 +0200 From: Andi Shyti To: Jia Yao Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org, Shuicheng Lin , Matt Roper , Joonas Lahtinen , Rodrigo Vivi , Maciej Plewka , Andi Shyti Subject: Re: [PATCH v3] drm/i915/dg2: Add per-context control for Wa_22013059131 Message-ID: References: <20260417050956.1945481-1-jia.yao@intel.com> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260417050956.1945481-1-jia.yao@intel.com> Hi, On Fri, Apr 17, 2026 at 05:09:56AM +0000, Jia Yao wrote: > Wa_22013059131 sets FORCE_1_SUB_MESSAGE_PER_FRAGMENT in LSC_CHICKEN_BIT_0 > at engine init, but this is known to cause GPU hangs in certain workloads. > Add I915_CONTEXT_PARAM_WA_22013059131 so userspace that handles the > workaround itself (e.g. by limiting SLM size) can set it to 1 to let the > kernel know bit 15 programming is not needed for that context. > > LSC_CHICKEN_BIT_0 is not context-saved by hardware, so the kernel restores > the correct value on every context switch via the indirect context > batchbuffer to avoid leaking state between contexts. The old unconditional > application of Wa22013059131 in intel_workarounds.c is removed. > > v3: > - Kernel-internal context will not change workaround settings Do we have a link of the userspace using this API? Joonas, do we need also a documentation update here? Thanks, Andi > Bspec: 54833 > Fixes: 645cc0b9d972 ("drm/i915/dg2: Add initial gt/ctx/engine workarounds") > Cc: stable@vger.kernel.org > Cc: Shuicheng Lin > Cc: Matt Roper > Cc: Joonas Lahtinen > Cc: Rodrigo Vivi > Cc: Maciej Plewka > Cc: Andi Shyti > Signed-off-by: Jia Yao > Reviewed-by: Matt Roper