Re: [PATCH 2/2] PCI: Add quirk to disable PCIe port services on Sophgo SG2042

Icenowy Zheng
2026-05-02T13:58:30Z

在 2026-05-01五的 22:23 +0530，Manivannan Sadhasivam写道：
> On Wed, Apr 01, 2026 at 01:56:58AM +0800, Han Gao wrote:
> > SG2042's PCIe root ports [1f1c:2042] fail to deliver MSI interrupts
> > to
> > downstream devices when native port services are enabled. Devices
> > under
> > an affected root port receive zero interrupts despite successful
> > vector
> > allocation, causing driver timeouts (e.g. amdgpu fence fallback
> > timer
> > expired on all rings).
> >
>
> Have you investigated why the endpoint is not able to deliver MSIs to
> host when
> Port services are enabled? Is it because the portdrv driver consumes
> all MSIs or
> MSIs are masked in hw (if so why? due to hardware issue?) or
> something else?

The problem is that the MSI controller has only 16 MSIs usable (it's
wrongly described as 32 previously, a fix to this is pending[1]), and
the failing device have an onboard PCIe switch, which created many PCIe
ports (and corresponding pcieport devices).

With pcieport devices activated, 11 MSIs are requested by the pcieport
drivers -- 3 SoC PCIe ports and 8 switch downstream ports. Then only 5
MSIs are available, but there're still 10 downstream-facing PCIe ports
now (and 5 of them are hardwired to onboard peripherals).

Thanks,
Icenowy

[1]
https://lore.kernel.org/all/20260407160143.1182430-1-zhengxingda@iscas.ac.cn/

>
> Currently, the problem description is very vague.
>
> - Mani
>
> > Set PCI_DEV_FLAGS_NO_PORT_SERVICES on SG2042 root ports to prevent
> > the
> > port service driver from probing, restoring correct MSI delivery.
> >
> > Fixes: 1c72774df028 ("PCI: sg2042: Add Sophgo SG2042 PCIe driver")
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
> > ---
> >  drivers/pci/quirks.c    | 12 ++++++++++++
> >  include/linux/pci_ids.h |  2 ++
> >  2 files changed, 14 insertions(+)
> >
> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> > index 48946cca4be7..bbde482ff7cb 100644
> > --- a/drivers/pci/quirks.c
> > +++ b/drivers/pci/quirks.c
> > @@ -6380,3 +6380,15 @@ static void
> > pci_mask_replay_timer_timeout(struct pci_dev *pdev)
> >  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750,
> > pci_mask_replay_timer_timeout);
> >  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755,
> > pci_mask_replay_timer_timeout);
> >  #endif
> > +
> > +/*
> > + * SG2042's PCIe root ports do not correctly deliver MSI
> > interrupts to
> > + * downstream devices when native PCIe port services are enabled.
> > All
> > + * services including bwctrl must be disabled, equivalent to
> > pcie_ports=compat.
> > + */
> > +static void quirk_sg2042_no_port_services(struct pci_dev *dev)
> > +{
> > + pci_info(dev, "SG2042: disabling native PCIe port
> > services\n");
> > + dev->dev_flags |= PCI_DEV_FLAGS_NO_PORT_SERVICES;
> > +}
> > +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOPHGO, 0x2042,
> > quirk_sg2042_no_port_services);
> > diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
> > index 406abf629be2..9663be526dd0 100644
> > --- a/include/linux/pci_ids.h
> > +++ b/include/linux/pci_ids.h
> > @@ -2630,6 +2630,8 @@
> >
> >  #define PCI_VENDOR_ID_CXL 0x1e98
> >
> > +#define PCI_VENDOR_ID_SOPHGO 0x1f1c
> > +
> >  #define PCI_VENDOR_ID_TEHUTI 0x1fc9
> >  #define PCI_DEVICE_ID_TEHUTI_3009 0x3009
> >  #define PCI_DEVICE_ID_TEHUTI_3010 0x3010
> > --
> > 2.47.3
> >