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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8d9f47408besm2913396d6.28.2026.06.15.09.32.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2026 09:32:44 -0700 (PDT) Date: Mon, 15 Jun 2026 12:32:39 -0400 From: Brian Masney To: Pavel =?iso-8859-1?Q?L=F6bl?= Cc: Stephen Boyd , Michal Simek , linux-clk@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH] clk: clocking-wizard: fix integer overflow in rate calculation Message-ID: References: <20260605130340.3549582-1-pavel@loebl.cz> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260605130340.3549582-1-pavel@loebl.cz> User-Agent: Mutt/2.3.1 (2026-03-20) On Fri, Jun 05, 2026 at 03:03:40PM +0200, Pavel Löbl wrote: > When using driver on Zynq-7000 (32-bit) determine_rate calculation > overflows. For instance requesting 32MHz with 100MHz parent clock > results in 100000000*(4*1000+0) 32-bit multiplication. > > Replace the expression with mult_frac which is already used in > clk_wzrd_recalc_ratef. > > Cc: stable@vger.kernel.org > Fixes: 7681f64e6404 ("clk: clocking-wizard: calculate dividers fractional parts") > Signed-off-by: Pale Löbl Reviewed-by: Brian Masney