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[34.124.129.10]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c9b0992227sm50676885ad.37.2026.06.29.08.15.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2026 08:15:26 -0700 (PDT) Date: Mon, 29 Jun 2026 15:15:21 +0000 From: Pranjal Shrivastava To: Nicolin Chen Cc: will@kernel.org, robin.murphy@arm.com, jgg@nvidia.com, joro@8bytes.org, kees@kernel.org, baolu.lu@linux.intel.com, kevin.tian@intel.com, miko.lenczewski@arm.com, smostafa@google.com, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, stable@vger.kernel.org, jamien@nvidia.com Subject: Re: [PATCH rc v6 4/7] iommu/arm-smmu-v3: Skip EVTQ/PRIQ setup in kdump kernel Message-ID: References: <1280ac4fdb37f998fd6dcb2bf8f4437283279395.1779265413.git.nicolinc@nvidia.com> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1280ac4fdb37f998fd6dcb2bf8f4437283279395.1779265413.git.nicolinc@nvidia.com> On Wed, May 20, 2026 at 10:03:21AM -0700, Nicolin Chen wrote: > In kdump cases, the crashed kernel's CDs and page tables can be corrupted, > which could trigger event spamming. Also, we cannot serve page requests. > > Skip the EVTQ/PRIQ setup entirely rather than enabling then disabling them. > > Also add some inline comments explaining that. > > Fixes: b63b3439b856 ("iommu/arm-smmu-v3: Abort all transactions if SMMU is enabled in kdump kernel") > Cc: stable@vger.kernel.org # v6.12+ > Suggested-by: Kevin Tian > Reviewed-by: Kevin Tian > Reviewed-by: Jason Gunthorpe > Signed-off-by: Nicolin Chen > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 43 +++++++++++++-------- > 1 file changed, 27 insertions(+), 16 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index e00b28e36f9c4..3f22949391c82 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -5161,21 +5161,35 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) > cmd.opcode = CMDQ_OP_TLBI_NSNH_ALL; > arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); > > - /* Event queue */ > - writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE); > - writel_relaxed(smmu->evtq.q.llq.prod, smmu->page1 + ARM_SMMU_EVTQ_PROD); > - writel_relaxed(smmu->evtq.q.llq.cons, smmu->page1 + ARM_SMMU_EVTQ_CONS); > - > - enables |= CR0_EVTQEN; > - ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, > - ARM_SMMU_CR0ACK); > - if (ret) { > - dev_err(smmu->dev, "failed to enable event queue\n"); > - return ret; > + /* > + * Event queue > + * > + * Do not enable in a kdump case, as the crashed kernel's CDs and page > + * tables might be corrupted, triggering event spamming. > + */ > + if (!is_kdump_kernel()) { > + writeq_relaxed(smmu->evtq.q.q_base, > + smmu->base + ARM_SMMU_EVTQ_BASE); > + writel_relaxed(smmu->evtq.q.llq.prod, > + smmu->page1 + ARM_SMMU_EVTQ_PROD); > + writel_relaxed(smmu->evtq.q.llq.cons, > + smmu->page1 + ARM_SMMU_EVTQ_CONS); > + > + enables |= CR0_EVTQEN; > + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, > + ARM_SMMU_CR0ACK); Nit: I believe only the write_reg_sync(CR0) should be under this if condition do we see any weird behavior if we perform the reg writes in kdump_kernel? > + if (ret) { > + dev_err(smmu->dev, "failed to enable event queue\n"); > + return ret; > + } > } > > - /* PRI queue */ > - if (smmu->features & ARM_SMMU_FEAT_PRI) { > + /* > + * PRI queue > + * > + * Do not enable in a kdump case, as we cannot serve page requests. > + */ > + if (!is_kdump_kernel() && (smmu->features & ARM_SMMU_FEAT_PRI)) { > writeq_relaxed(smmu->priq.q.q_base, > smmu->base + ARM_SMMU_PRIQ_BASE); > writel_relaxed(smmu->priq.q.llq.prod, > @@ -5208,9 +5222,6 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) > return ret; > } > > - if (is_kdump_kernel()) > - enables &= ~(CR0_EVTQEN | CR0_PRIQEN); > - > /* Enable the SMMU interface */ > enables |= CR0_SMMUEN; > ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, > -- > 2.43.0 > Apart from that nit, Reviewed-by: Pranjal Shrivastava Thanks, Praan