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[34.140.183.197]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1fc1066cfsm58540435e9.1.2026.10.21.08.14.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2026 08:14:25 -0700 (PDT) Date: Wed, 21 Oct 2026 16:14:21 +0100 From: Vincent Donnefort To: Marc Zyngier Cc: oupton@kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, joey.gouly@arm.com, seiden@linux.ibm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, kernel-team@android.com, fuad.tabba@linux.dev, stable@vger.kernel.org Subject: Re: [PATCH v1] KVM: arm64: pkvm: Clear GICv3 LRs in the hypervisor Message-ID: References: <20261021110000.508827-1-vdonnefort@google.com> <86qzhjz1iz.wl-maz@kernel.org> <86pkx3yylb.wl-maz@kernel.org> X-Mailing-List: stable@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <86pkx3yylb.wl-maz@kernel.org> On Wed, Oct 21, 2026 at 02:25:52PM +0100, Marc Zyngier wrote: > On Wed, 21 Oct 2026 13:50:22 +0100, > Vincent Donnefort wrote: > > > > On Wed, Oct 21, 2026 at 01:22:28PM +0100, Marc Zyngier wrote: > > > On Wed, 21 Oct 2026 12:00:00 +0100, > > > Vincent Donnefort wrote: > > > > > > > > The LR registers are architecturally UNKNOWN when the CPU boots or > > > > resumes. However, in protected mode, only the used ones are reset. > > > > During boot the HVC __vgic_v3_init_lrs() is never called because > > > > vgic_present is only set in init_subsystems(), after cpu_hyp_init() was > > > > called. > > > > > > Why don't you fix this rather than making the init even more > > > different? > > > > Ack, I'll make a patch to fix that first. > > > > > > > > > Also, the PM notifier isn't registered for pKVM and the HVC > > > > becomes unavailable after the host is deprivileged. > > > > > > Sanitising the LRs on PSCI_ON is probably the right thing to do, but I > > > don't understand why resetting the LRs is out of reach from the host, > > > given that the host is fully in charge of the interrupt injection, and > > > therefore controls the LRs. > > > > I suppose I could reinstantiate the pm callbacks for pkvm to at least reset the > > LRs? > > I think there are two different things: > > - pKVM must not rely on the host resetting the LRs once it is > deprivileged (that's the PSCI_ON case) Definitely not a hot path, but if we keep this one ^, isn't a shame of making the host issue HVCs on CPU resume to reset the LRs if we know the hypervisor did it anyway? -- Vincent > > - pKVM must not prevent the host from resetting the LRs (that's the > "mind your own business" case). > > Both need addressing. If that means the LRs get reset twice because > pKVM inherits the PM callbacks, so be it. > > Thanks, > > M. > > -- > Without deviation from the norm, progress is not possible.