From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00BDFEB64DC for ; Fri, 21 Jul 2023 10:21:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231433AbjGUKVo (ORCPT ); Fri, 21 Jul 2023 06:21:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57576 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231652AbjGUKV2 (ORCPT ); Fri, 21 Jul 2023 06:21:28 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF6483C11 for ; Fri, 21 Jul 2023 03:20:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689934850; x=1721470850; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=OxibDKtAvapPQ7P85Ukb7Bo6W97b/VOI3fTJx3B8gxY=; b=FcPvvGuxd2q6BBZUcm+t5NR7fNuC0SytedhgbAVd+qYyAKFT08vw1S+C bWnxBfVzyP8ghVObBbwiUZevxCGw/JOhz11b86rGDsXvGd6F1oJ3WzZD4 l4eFANKR3U9YJob5Jp3iehu2ay40oawKusZVHl9DSMxhNwdVF+QHxfacM LVOAg+ZXn3K16juoMyY+Cs0FYuWgADsmmTXyrXLKffoRAaG6WqOYPPt18 mSFz4R9ueGErGDNngaEflUqs5dOElWm4KNwKOMgGEfLKGSHF0B5FAQcJ0 ne+BakZDLyDEzvrEuoxLlbMxWItZClBYMvL6W9VoXVRcUEuPBRspNtfbJ w==; X-IronPort-AV: E=McAfee;i="6600,9927,10777"; a="365881228" X-IronPort-AV: E=Sophos;i="6.01,220,1684825200"; d="scan'208";a="365881228" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2023 03:17:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10777"; a="794916476" X-IronPort-AV: E=Sophos;i="6.01,220,1684825200"; d="scan'208";a="794916476" Received: from ahajda-mobl.ger.corp.intel.com (HELO [10.213.21.56]) ([10.213.21.56]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2023 03:17:24 -0700 Message-ID: Date: Fri, 21 Jul 2023 12:17:22 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Firefox/102.0 Thunderbird/102.13.0 Subject: Re: [Intel-gfx] [PATCH v7 5/9] drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control Content-Language: en-US To: Andi Shyti , Jonathan Cavitt , Matt Roper , Chris Wilson , Mika Kuoppala , Nirmoy Das Cc: intel-gfx , linux-stable , dri-evel References: <20230720210737.761400-1-andi.shyti@linux.intel.com> <20230720210737.761400-6-andi.shyti@linux.intel.com> From: Andrzej Hajda Organization: Intel Technology Poland sp. z o.o. - ul. Slowackiego 173, 80-298 Gdansk - KRS 101882 - NIP 957-07-52-316 In-Reply-To: <20230720210737.761400-6-andi.shyti@linux.intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org On 20.07.2023 23:07, Andi Shyti wrote: > Enable the CCS_FLUSH bit 13 in the control pipe for render and > compute engines in platforms starting from Meteor Lake (BSPEC > 43904 and 47112). > > Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines") > Signed-off-by: Andi Shyti > Cc: Jonathan Cavitt > Cc: Nirmoy Das > Cc: # v5.8+ > --- > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 7 +++++++ > drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 + > 2 files changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > index 7566c89d9def3..9d050b9a19194 100644 > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > @@ -218,6 +218,13 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) > > bit_group_0 |= PIPE_CONTROL0_HDC_PIPELINE_FLUSH; > > + /* > + * When required, in MTL+ platforms we need to > + * set the CCS_FLUSH bit in the pipe control > + */ > + if (GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70)) > + bit_group_0 |= PIPE_CONTROL_CCS_FLUSH; > + Btw, not for this patch, but related: rcs and ccs have slightly different set of flushes according to bspec but this functions is the same for both. Is it sth we should address, or just safe simplification. Regards Andrzej > bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH; > bit_group_1 |= PIPE_CONTROL_FLUSH_L3; > bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; > diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > index 5d143e2a8db03..5df7cce23197c 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > @@ -299,6 +299,7 @@ > #define PIPE_CONTROL_QW_WRITE (1<<14) > #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14) > #define PIPE_CONTROL_DEPTH_STALL (1<<13) > +#define PIPE_CONTROL_CCS_FLUSH (1<<13) /* MTL+ */ > #define PIPE_CONTROL_WRITE_FLUSH (1<<12) > #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ > #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on ILK */