From: Harshit Mogalapalli <harshit.m.mogalapalli@oracle.com>
To: Sasha Levin <sashal@kernel.org>, stable@vger.kernel.org
Cc: Zhang Rui <rui.zhang@intel.com>,
Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>,
"Rafael J . Wysocki" <rafael.j.wysocki@intel.com>
Subject: Re: [PATCH 5.15.y] powercap: intel_rapl: Do not change CLAMPING bit if ENABLE bit cannot be changed
Date: Wed, 23 Jul 2025 12:11:38 +0530 [thread overview]
Message-ID: <bbb2c75c-2e14-47c2-987b-aefabf298d6b@oracle.com> (raw)
In-Reply-To: <20250721001504.767161-1-sashal@kernel.org>
Hi Sasha,
Question inline from a backport point of view:
On 21/07/25 05:45, Sasha Levin wrote:
> From: Zhang Rui <rui.zhang@intel.com>
>
> [ Upstream commit 964209202ebe1569c858337441e87ef0f9d71416 ]
>
> PL1 cannot be disabled on some platforms. The ENABLE bit is still set
> after software clears it. This behavior leads to a scenario where, upon
> user request to disable the Power Limit through the powercap sysfs, the
> ENABLE bit remains set while the CLAMPING bit is inadvertently cleared.
>
> According to the Intel Software Developer's Manual, the CLAMPING bit,
> "When set, allows the processor to go below the OS requested P states in
> order to maintain the power below specified Platform Power Limit value."
>
> Thus this means the system may operate at higher power levels than
> intended on such platforms.
>
> Enhance the code to check ENABLE bit after writing to it, and stop
> further processing if ENABLE bit cannot be changed.
>
> Reported-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
> Fixes: 2d281d8196e3 ("PowerCap: Introduce Intel RAPL power capping driver")
> Cc: All applicable <stable@vger.kernel.org>
> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
> Link: https://patch.msgid.link/20250619071340.384782-1-rui.zhang@intel.com
> [ rjw: Use str_enabled_disabled() instead of open-coded equivalent ]
> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
> [ replaced rapl_write_pl_data() and rapl_read_pl_data() with rapl_write_data_raw() and rapl_read_data_raw() ]
> Signed-off-by: Sasha Levin <sashal@kernel.org>
> ---
> drivers/powercap/intel_rapl_common.c | 23 ++++++++++++++++++++++-
> 1 file changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_rapl_common.c
> index 9dfc053878fda..40d149d9dce85 100644
> --- a/drivers/powercap/intel_rapl_common.c
> +++ b/drivers/powercap/intel_rapl_common.c
> @@ -212,12 +212,33 @@ static int find_nr_power_limit(struct rapl_domain *rd)
> static int set_domain_enable(struct powercap_zone *power_zone, bool mode)
> {
> struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
> + u64 val;
> + int ret;
>
> if (rd->state & DOMAIN_STATE_BIOS_LOCKED)
> return -EACCES;
>
> cpus_read_lock();
> - rapl_write_data_raw(rd, PL1_ENABLE, mode);
> + ret = rapl_write_data_raw(rd, PL1_ENABLE, mode);
> + if (ret) {
> + cpus_read_unlock();
> + return ret;
> + }
> +
> + /* Check if the ENABLE bit was actually changed */
> + ret = rapl_read_data_raw(rd, PL1_ENABLE, true, &val);
> + if (ret) {
> + cpus_read_unlock();
> + return ret;
> + }
Shouldn't this be rapl_read_data_raw(rd, PL1_ENABLE, false, &val); ?
Thanks
Harshit
> +
> + if (mode != val) {
> + pr_debug("%s cannot be %s\n", power_zone->name,
> + mode ? "enabled" : "disabled");
> + cpus_read_unlock();
> + return 0;
> + }
> +
> if (rapl_defaults->set_floor_freq)
> rapl_defaults->set_floor_freq(rd, mode);
> cpus_read_unlock();
next prev parent reply other threads:[~2025-07-23 6:41 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-08 15:14 FAILED: patch "[PATCH] powercap: intel_rapl: Do not change CLAMPING bit if ENABLE" failed to apply to 5.15-stable tree gregkh
2025-07-21 0:15 ` [PATCH 5.15.y] powercap: intel_rapl: Do not change CLAMPING bit if ENABLE bit cannot be changed Sasha Levin
2025-07-23 6:41 ` Harshit Mogalapalli [this message]
2025-07-23 13:48 ` srinivas pandruvada
2025-07-23 15:06 ` Sasha Levin
2025-07-23 17:09 ` srinivas pandruvada
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