* [PATCH 1/2] drm/i915/psr: Disable PSR on update_m_n and update_lrr [not found] <20260312083710.1593781-1-jouni.hogander@intel.com> @ 2026-03-12 8:37 ` Jouni Högander 2026-03-16 8:13 ` Kandpal, Suraj 2026-03-12 8:37 ` [PATCH 2/2] drm/i915/psr: Compute psr_entry_setup_frames into intel_crtc_state Jouni Högander 1 sibling, 1 reply; 5+ messages in thread From: Jouni Högander @ 2026-03-12 8:37 UTC (permalink / raw) To: intel-gfx, intel-xe; +Cc: Jouni Högander, stable PSR/PR parameters might be changing on update_m_n or update_lrr. Disable on update_m_n and update_lrr to ensure proper parameters are taken into use on next PSR enable in intel_psr_post_plane_update. Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15771 Fixes: 2bc98c6f97af ("drm/i915/alpm: Compute ALPM parameters into crtc_state->alpm_state") Cc: <stable@vger.kernel.org> # v6.19+ Signed-off-by: Jouni Högander <jouni.hogander@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 5041a5a138d1..7e0e4c3bf985 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -3112,6 +3112,8 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, * - Display WA #1136: skl, bxt */ if (intel_crtc_needs_modeset(new_crtc_state) || + new_crtc_state->update_m_n || + new_crtc_state->update_lrr || !new_crtc_state->has_psr || !new_crtc_state->active_planes || new_crtc_state->has_sel_update != psr->sel_update_enabled || -- 2.43.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* RE: [PATCH 1/2] drm/i915/psr: Disable PSR on update_m_n and update_lrr 2026-03-12 8:37 ` [PATCH 1/2] drm/i915/psr: Disable PSR on update_m_n and update_lrr Jouni Högander @ 2026-03-16 8:13 ` Kandpal, Suraj 0 siblings, 0 replies; 5+ messages in thread From: Kandpal, Suraj @ 2026-03-16 8:13 UTC (permalink / raw) To: Hogander, Jouni, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Hogander, Jouni, stable@vger.kernel.org > Subject: [PATCH 1/2] drm/i915/psr: Disable PSR on update_m_n and update_lrr > > PSR/PR parameters might be changing on update_m_n or update_lrr. Disable Nit: *might change based on update_m_n or update_lrr Otherwise LGTM, Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> > on update_m_n and update_lrr to ensure proper parameters are taken into use > on next PSR enable in intel_psr_post_plane_update. > > Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15771 > Fixes: 2bc98c6f97af ("drm/i915/alpm: Compute ALPM parameters into > crtc_state->alpm_state") > Cc: <stable@vger.kernel.org> # v6.19+ > Signed-off-by: Jouni Högander <jouni.hogander@intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index 5041a5a138d1..7e0e4c3bf985 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -3112,6 +3112,8 @@ void intel_psr_pre_plane_update(struct > intel_atomic_state *state, > * - Display WA #1136: skl, bxt > */ > if (intel_crtc_needs_modeset(new_crtc_state) || > + new_crtc_state->update_m_n || > + new_crtc_state->update_lrr || > !new_crtc_state->has_psr || > !new_crtc_state->active_planes || > new_crtc_state->has_sel_update != psr- > >sel_update_enabled || > -- > 2.43.0 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/2] drm/i915/psr: Compute psr_entry_setup_frames into intel_crtc_state [not found] <20260312083710.1593781-1-jouni.hogander@intel.com> 2026-03-12 8:37 ` [PATCH 1/2] drm/i915/psr: Disable PSR on update_m_n and update_lrr Jouni Högander @ 2026-03-12 8:37 ` Jouni Högander 2026-03-16 6:21 ` Kandpal, Suraj 1 sibling, 1 reply; 5+ messages in thread From: Jouni Högander @ 2026-03-12 8:37 UTC (permalink / raw) To: intel-gfx, intel-xe; +Cc: Jouni Högander, Mika Kahola, stable Psr_entry_setup_frames is currently computed directly into struct intel_dp:intel_psr:entry_setup_frames. This causes a problem if mode change gets rejected after PSR compute config: Psr_entry_setup_frames computed for this rejected state is in intel_dp:intel_psr:entry_setup_frame. Fix this by computing it into intel_crtc_state and copy the value into intel_dp:intel_psr:entry_setup_frames on PSR enable. Fixes: 2b981d57e480 ("drm/i915/display: Support PSR entry VSC packet to be transmitted one frame earlier") Cc: Mika Kahola <mika.kahola@intel.com> Cc: <stable@vger.kernel.org> # v6.8+ Signed-off-by: Jouni Högander <jouni.hogander@intel.com> --- drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index e189f8c39ccb..d3a9ace4c9d1 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1188,6 +1188,7 @@ struct intel_crtc_state { u32 dc3co_exitline; u16 su_y_granularity; u8 active_non_psr_pipes; + u8 entry_setup_frames; const char *no_psr_reason; /* diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 7e0e4c3bf985..c13116e6f17f 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1716,7 +1716,7 @@ static bool _psr_compute_config(struct intel_dp *intel_dp, entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, conn_state, adjusted_mode); if (entry_setup_frames >= 0) { - intel_dp->psr.entry_setup_frames = entry_setup_frames; + crtc_state->entry_setup_frames = entry_setup_frames; } else { crtc_state->no_psr_reason = "PSR setup timing not met"; drm_dbg_kms(display->drm, @@ -1814,7 +1814,7 @@ static bool intel_psr_needs_wa_18037818876(struct intel_dp *intel_dp, { struct intel_display *display = to_intel_display(intel_dp); - return (DISPLAY_VER(display) == 20 && intel_dp->psr.entry_setup_frames > 0 && + return (DISPLAY_VER(display) == 20 && crtc_state->entry_setup_frames > 0 && !crtc_state->has_sel_update); } @@ -2190,6 +2190,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, intel_dp->psr.pkg_c_latency_used = crtc_state->pkg_c_latency_used; intel_dp->psr.io_wake_lines = crtc_state->alpm_state.io_wake_lines; intel_dp->psr.fast_wake_lines = crtc_state->alpm_state.fast_wake_lines; + intel_dp->psr.entry_setup_frames = crtc_state->entry_setup_frames; if (!psr_interrupt_error_check(intel_dp)) return; -- 2.43.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* RE: [PATCH 2/2] drm/i915/psr: Compute psr_entry_setup_frames into intel_crtc_state 2026-03-12 8:37 ` [PATCH 2/2] drm/i915/psr: Compute psr_entry_setup_frames into intel_crtc_state Jouni Högander @ 2026-03-16 6:21 ` Kandpal, Suraj 2026-03-16 11:28 ` Hogander, Jouni 0 siblings, 1 reply; 5+ messages in thread From: Kandpal, Suraj @ 2026-03-16 6:21 UTC (permalink / raw) To: Hogander, Jouni, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Hogander, Jouni, Kahola, Mika, stable@vger.kernel.org > Subject: [PATCH 2/2] drm/i915/psr: Compute psr_entry_setup_frames into > intel_crtc_state > > Psr_entry_setup_frames is currently computed directly into struct Should this be PSR entry_setup_frames. Since Psr_entry_setup_frames does not exist. With that fixed LGTM, Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> > intel_dp:intel_psr:entry_setup_frames. This causes a problem if mode change > gets rejected after PSR compute config: Psr_entry_setup_frames computed for > this rejected state is in intel_dp:intel_psr:entry_setup_frame. Fix this by > computing it into intel_crtc_state and copy the value into > intel_dp:intel_psr:entry_setup_frames on PSR enable. > > Fixes: 2b981d57e480 ("drm/i915/display: Support PSR entry VSC packet to be > transmitted one frame earlier") > Cc: Mika Kahola <mika.kahola@intel.com> > Cc: <stable@vger.kernel.org> # v6.8+ > Signed-off-by: Jouni Högander <jouni.hogander@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display_types.h | 1 + > drivers/gpu/drm/i915/display/intel_psr.c | 5 +++-- > 2 files changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > b/drivers/gpu/drm/i915/display/intel_display_types.h > index e189f8c39ccb..d3a9ace4c9d1 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1188,6 +1188,7 @@ struct intel_crtc_state { > u32 dc3co_exitline; > u16 su_y_granularity; > u8 active_non_psr_pipes; > + u8 entry_setup_frames; > const char *no_psr_reason; > > /* > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index 7e0e4c3bf985..c13116e6f17f 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -1716,7 +1716,7 @@ static bool _psr_compute_config(struct intel_dp > *intel_dp, > entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, > conn_state, adjusted_mode); > > if (entry_setup_frames >= 0) { > - intel_dp->psr.entry_setup_frames = entry_setup_frames; > + crtc_state->entry_setup_frames = entry_setup_frames; > } else { > crtc_state->no_psr_reason = "PSR setup timing not met"; > drm_dbg_kms(display->drm, > @@ -1814,7 +1814,7 @@ static bool intel_psr_needs_wa_18037818876(struct > intel_dp *intel_dp, { > struct intel_display *display = to_intel_display(intel_dp); > > - return (DISPLAY_VER(display) == 20 && intel_dp- > >psr.entry_setup_frames > 0 && > + return (DISPLAY_VER(display) == 20 && crtc_state- > >entry_setup_frames > > +0 && > !crtc_state->has_sel_update); > } > > @@ -2190,6 +2190,7 @@ static void intel_psr_enable_locked(struct intel_dp > *intel_dp, > intel_dp->psr.pkg_c_latency_used = crtc_state->pkg_c_latency_used; > intel_dp->psr.io_wake_lines = crtc_state->alpm_state.io_wake_lines; > intel_dp->psr.fast_wake_lines = crtc_state->alpm_state.fast_wake_lines; > + intel_dp->psr.entry_setup_frames = crtc_state->entry_setup_frames; > > if (!psr_interrupt_error_check(intel_dp)) > return; > -- > 2.43.0 ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] drm/i915/psr: Compute psr_entry_setup_frames into intel_crtc_state 2026-03-16 6:21 ` Kandpal, Suraj @ 2026-03-16 11:28 ` Hogander, Jouni 0 siblings, 0 replies; 5+ messages in thread From: Hogander, Jouni @ 2026-03-16 11:28 UTC (permalink / raw) To: Kandpal, Suraj, intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: stable@vger.kernel.org, Kahola, Mika On Mon, 2026-03-16 at 06:21 +0000, Kandpal, Suraj wrote: > > Subject: [PATCH 2/2] drm/i915/psr: Compute psr_entry_setup_frames > > into > > intel_crtc_state > > > > Psr_entry_setup_frames is currently computed directly into struct > > Should this be PSR entry_setup_frames. Since Psr_entry_setup_frames > does not exist. > With that fixed LGTM, > Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Thank you Suraj for the review. These are now pushed to drm-intel-next. BR, Jouni Högander > > > intel_dp:intel_psr:entry_setup_frames. This causes a problem if > > mode change > > gets rejected after PSR compute config: Psr_entry_setup_frames > > computed for > > this rejected state is in intel_dp:intel_psr:entry_setup_frame. Fix > > this by > > computing it into intel_crtc_state and copy the value into > > intel_dp:intel_psr:entry_setup_frames on PSR enable. > > > > Fixes: 2b981d57e480 ("drm/i915/display: Support PSR entry VSC > > packet to be > > transmitted one frame earlier") > > Cc: Mika Kahola <mika.kahola@intel.com> > > Cc: <stable@vger.kernel.org> # v6.8+ > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_display_types.h | 1 + > > drivers/gpu/drm/i915/display/intel_psr.c | 5 +++-- > > 2 files changed, 4 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > > b/drivers/gpu/drm/i915/display/intel_display_types.h > > index e189f8c39ccb..d3a9ace4c9d1 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > @@ -1188,6 +1188,7 @@ struct intel_crtc_state { > > u32 dc3co_exitline; > > u16 su_y_granularity; > > u8 active_non_psr_pipes; > > + u8 entry_setup_frames; > > const char *no_psr_reason; > > > > /* > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > b/drivers/gpu/drm/i915/display/intel_psr.c > > index 7e0e4c3bf985..c13116e6f17f 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -1716,7 +1716,7 @@ static bool _psr_compute_config(struct > > intel_dp > > *intel_dp, > > entry_setup_frames = > > intel_psr_entry_setup_frames(intel_dp, > > conn_state, adjusted_mode); > > > > if (entry_setup_frames >= 0) { > > - intel_dp->psr.entry_setup_frames = > > entry_setup_frames; > > + crtc_state->entry_setup_frames = > > entry_setup_frames; > > } else { > > crtc_state->no_psr_reason = "PSR setup timing not > > met"; > > drm_dbg_kms(display->drm, > > @@ -1814,7 +1814,7 @@ static bool > > intel_psr_needs_wa_18037818876(struct > > intel_dp *intel_dp, { > > struct intel_display *display = > > to_intel_display(intel_dp); > > > > - return (DISPLAY_VER(display) == 20 && intel_dp- > > > psr.entry_setup_frames > 0 && > > + return (DISPLAY_VER(display) == 20 && crtc_state- > > > entry_setup_frames > > > +0 && > > !crtc_state->has_sel_update); > > } > > > > @@ -2190,6 +2190,7 @@ static void intel_psr_enable_locked(struct > > intel_dp > > *intel_dp, > > intel_dp->psr.pkg_c_latency_used = crtc_state- > > >pkg_c_latency_used; > > intel_dp->psr.io_wake_lines = crtc_state- > > >alpm_state.io_wake_lines; > > intel_dp->psr.fast_wake_lines = crtc_state- > > >alpm_state.fast_wake_lines; > > + intel_dp->psr.entry_setup_frames = crtc_state- > > >entry_setup_frames; > > > > if (!psr_interrupt_error_check(intel_dp)) > > return; > > -- > > 2.43.0 > ^ permalink raw reply [flat|nested] 5+ messages in thread
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[not found] <20260312083710.1593781-1-jouni.hogander@intel.com>
2026-03-12 8:37 ` [PATCH 1/2] drm/i915/psr: Disable PSR on update_m_n and update_lrr Jouni Högander
2026-03-16 8:13 ` Kandpal, Suraj
2026-03-12 8:37 ` [PATCH 2/2] drm/i915/psr: Compute psr_entry_setup_frames into intel_crtc_state Jouni Högander
2026-03-16 6:21 ` Kandpal, Suraj
2026-03-16 11:28 ` Hogander, Jouni
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