From: "Chang S. Bae" <chang.seok.bae@intel.com>
To: Andrei Vagin <avagin@google.com>
Cc: Thomas Gleixner <tglx@kernel.org>, Ingo Molnar <mingo@redhat.com>,
Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
<linux-kernel@vger.kernel.org>, <criu@lists.linux.dev>,
<x86@kernel.org>, <stable@vger.kernel.org>
Subject: Re: [PATCH] Revert "x86/fpu: Refine and simplify the magic number check during signal return"
Date: Fri, 1 May 2026 14:04:40 -0700 [thread overview]
Message-ID: <c4fab3dc-1627-4775-986e-6b3ea52e7c36@intel.com> (raw)
In-Reply-To: <CAEWA0a5=S+C2pdViHPWykvG0Dj4hbuKFVhSnEzpPWoyOh4oAnQ@mail.gmail.com>
On 5/1/2026 1:50 PM, Andrei Vagin wrote:
>
> This is a different; here, we have two different CPU vendors where XSAVE
> layouts differ. The XSAVE layout itself is not the only reason why migration
> between Intel and AMD cannot work reliably.
When saying CPU A and B, I didn't intend the same vendor but x86 in general.
next prev parent reply other threads:[~2026-05-01 21:04 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-29 0:06 [PATCH] Revert "x86/fpu: Refine and simplify the magic number check during signal return" Andrei Vagin
2026-04-29 7:26 ` Chang S. Bae
2026-04-29 16:44 ` Andrei Vagin
2026-04-29 17:15 ` Chang S. Bae
2026-04-29 20:44 ` Andrei Vagin
2026-04-29 21:44 ` Chang S. Bae
2026-04-30 0:28 ` Andrei Vagin
2026-05-01 18:44 ` Andrei Vagin
2026-05-01 19:13 ` Chang S. Bae
2026-05-01 20:50 ` Andrei Vagin
2026-05-01 21:04 ` Chang S. Bae [this message]
2026-05-01 21:42 ` Andrei Vagin
2026-05-02 19:23 ` Chang S. Bae
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