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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL02EPF0001A0FE.mail.protection.outlook.com (10.167.242.105) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6792.19 via Frontend Transport; Fri, 22 Sep 2023 09:16:25 +0000 Received: from [192.168.137.2] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 22 Sep 2023 04:16:23 -0500 Message-ID: Date: Fri, 22 Sep 2023 11:16:20 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] mtd: rawnand: arasan: Ensure program page operations are successful Content-Language: en-US To: Miquel Raynal CC: Richard Weinberger , Vignesh Raghavendra , Tudor Ambarus , Pratyush Yadav , Michael Walle , , Thomas Petazzoni , References: <20230717194221.229778-1-miquel.raynal@bootlin.com> <20230717194221.229778-2-miquel.raynal@bootlin.com> <20230911175247.44c1d894@xps-13> <20230912161752.581019bc@xps-13> <20230922111437.57804995@xps-13> From: Michal Simek Autocrypt: addr=michal.simek@amd.com; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2023 09:16:25.0432 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 87fcace1-1bec-423a-7a68-08dbbb4c9858 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8358 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org On 9/22/23 11:14, Miquel Raynal wrote: > Hi Michal, > > michal.simek@amd.com wrote on Thu, 21 Sep 2023 12:25:10 +0200: > >> On 9/12/23 16:17, Miquel Raynal wrote: >>> Hi Michal, >>> >>> michal.simek@amd.com wrote on Tue, 12 Sep 2023 15:55:23 +0200: >>> >>>> Hi Miquel, >>>> >>>> On 9/11/23 17:52, Miquel Raynal wrote: >>>>> Hi Michal, >>>>> >>>>> miquel.raynal@bootlin.com wrote on Mon, 17 Jul 2023 21:42:20 +0200: >>>>> >>>> The NAND core complies with the ONFI specification, which itself >>>>>> mentions that after any program or erase operation, a status check >>>>>> should be performed to see whether the operation was finished *and* >>>>>> successful. >>>>>> >>>>>> The NAND core offers helpers to finish a page write (sending the >>>>>> "PAGE PROG" command, waiting for the NAND chip to be ready again, and >>>>>> checking the operation status). But in some cases, advanced controller >>>>>> drivers might want to optimize this and craft their own page write >>>>>> helper to leverage additional hardware capabilities, thus not always >>>>>> using the core facilities. >>>>>> >>>>>> Some drivers, like this one, do not use the core helper to finish a page >>>>>> write because the final cycles are automatically managed by the >>>>>> hardware. In this case, the additional care must be taken to manually >>>>>> perform the final status check. >>>>>> >>>>>> Let's read the NAND chip status at the end of the page write helper and >>>>>> return -EIO upon error. >>>>>> >>>>>> Cc: Michal Simek >>>>>> Cc: stable@vger.kernel.org >>>>>> Fixes: 88ffef1b65cf ("mtd: rawnand: arasan: Support the hardware BCH ECC engine") >>>>>> Signed-off-by: Miquel Raynal >>>>>> >>>>>> --- >>>>>> >>>>>> Hello Michal, >>>>>> >>>>>> I have not tested this, but based on a report on another driver, I >>>>>> believe the status check is also missing here and could sometimes >>>>>> lead to unnoticed partial writes. >>>>>> >>>>>> Please test on your side that everything still works and let me >>>>>> know how it goes. >>>>> >>>>> Any news from the testing team about patches 2/3 and 3/3? >>>> >>>> I asked Amit to test and he didn't get back to me even I asked for it couple of times. >>> >>> Ok. >>> >>>> Can you please tell me how to test it? I will setup HW myself and test it and get back to you. >>> >>> I believe setting up the board to use the hardware BCH engine and >>> performing basic erase/write/read testing with a known file and check >>> it still behaves correctly would work. You can also run >>> >>> nandbiterrs -i /dev/mtdx >>> >>> as a second step and verify there is no difference with and without the >>> patch and finally check the impact: >>> >>> flash_speed -d -c 10 /dev/mtdx >>> (be careful: this is a destructive operation) >> >> Testing team won't see any issue that's why feel free to add my >> Acked-by: Michal Smek > > I think you told me in the last e-mail you tested the pl353 patch, not > the one for the Arasan controller. Shall I add your Acked-by here and > your Tested-by in the other? Yes exactly. I tested pl353 myself. If that log looks good feel free to add my Tested-by tag. And I got information from testing team that they tested Arasan one hence only Ack one. Thanks, Michal