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([2620:10d:c090:500::6:84a4]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1413889bca5sm17673449c88.12.2026.08.14.13.49.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Aug 2026 13:49:24 -0700 (PDT) Message-ID: Subject: Re: [PATCH bpf v2 2/2] selftests/bpf: Check per-CPU address resolution per register From: Eduard Zingerman To: Vineet Gupta , bpf@vger.kernel.org Cc: ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org, x86@kernel.org, stable@vger.kernel.org Date: Fri, 14 Aug 2026 13:49:23 -0700 In-Reply-To: <20260814203248.3714536-3-vineet.gupta@linux.dev> References: <20260814203248.3714536-1-vineet.gupta@linux.dev> <20260814203248.3714536-3-vineet.gupta@linux.dev> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.60.2 (3.60.2-1.fc44) Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Fri, 2026-08-14 at 13:32 -0700, Vineet Gupta wrote: ... > +/* > + * An ld_imm64 of a per-CPU map value is followed by a mov_percpu_addr t= hat > + * reuses the same register, so the register the address lands in decide= s how > + * the JIT encodes the add. On x86 R5, R7, R8 and R9 are the extended > + * registers, whose high bit needs REX.R because the destination sits in > + * ModRM.reg. Check one program per extended register, since getting the > + * prefix wrong resolves the address into whichever register shares the = low > + * three bits instead. > + */ > + > +SEC("raw_tp") > +__description("per-CPU address into r5") > +__success > +__arch_x86_64 > +__jited(" addq %gs:{{.*}}, %r8") > +__naked void percpu_addr_into_r5(void) > +{ > + asm volatile (" \ > + r5 =3D %[percpu_data] ll; \ > + r0 =3D *(u32 *)(r5 + 0); \ > + exit; \ > +" : > + : __imm_addr(percpu_data) > + : __clobber_all); > +} Thank you for adding the tests. Maybe save some space by just packing it as a single test? __jited(" addq %gs:{{.*}}, %...") __jited(" addq %gs:{{.*}}, %...") __jited(" addq %gs:{{.*}}, %...") __jited(" addq %gs:{{.*}}, %...") __jited(" addq %gs:{{.*}}, %...") r0 =3D %[percpu_data] ll; \ r1 =3D %[percpu_data] ll; \ r2 =3D %[percpu_data] ll; \ r3 =3D %[percpu_data] ll; \ r4 =3D %[percpu_data] ll; \ r5 =3D %[percpu_data] ll; \ r6 =3D %[percpu_data] ll; \ r7 =3D %[percpu_data] ll; \ r8 =3D %[percpu_data] ll; \ r9 =3D %[percpu_data] ll; \ More compact and no need to describe in length why only R{5,7,8,9} are sele= cted. ...