* [PATCH 1/2] drm/xe/migrate: fix pat index usage
@ 2024-11-26 18:13 Matthew Auld
2024-11-26 18:13 ` [PATCH 2/2] drm/xe/migrate: use XE_BO_FLAG_PAGETABLE Matthew Auld
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Matthew Auld @ 2024-11-26 18:13 UTC (permalink / raw)
To: intel-xe; +Cc: Matthew Brost, Nirmoy Das, stable
XE_CACHE_WB must be converted into the per-platform pat index for that
particular caching mode, otherwise we are just encoding whatever happens
to be the value of that enum.
Fixes: e8babb280b5e ("drm/xe: Convert multiple bind ops into single job")
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Nirmoy Das <nirmoy.das@intel.com>
Cc: <stable@vger.kernel.org> # v6.12+
---
drivers/gpu/drm/xe/xe_migrate.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index cfd31ae49cc1..48e205a40fd2 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -1350,6 +1350,7 @@ __xe_migrate_update_pgtables(struct xe_migrate *m,
/* For sysmem PTE's, need to map them in our hole.. */
if (!IS_DGFX(xe)) {
+ u16 pat_index = xe->pat.idx[XE_CACHE_WB];
u32 ptes, ofs;
ppgtt_ofs = NUM_KERNEL_PDE - 1;
@@ -1409,7 +1410,7 @@ __xe_migrate_update_pgtables(struct xe_migrate *m,
pt_bo->update_index = current_update;
addr = vm->pt_ops->pte_encode_bo(pt_bo, 0,
- XE_CACHE_WB, 0);
+ pat_index, 0);
bb->cs[bb->len++] = lower_32_bits(addr);
bb->cs[bb->len++] = upper_32_bits(addr);
}
--
2.47.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/2] drm/xe/migrate: use XE_BO_FLAG_PAGETABLE
2024-11-26 18:13 [PATCH 1/2] drm/xe/migrate: fix pat index usage Matthew Auld
@ 2024-11-26 18:13 ` Matthew Auld
2024-11-26 18:27 ` Nirmoy Das
2024-11-26 23:47 ` Matthew Brost
2024-11-26 18:25 ` [PATCH 1/2] drm/xe/migrate: fix pat index usage Nirmoy Das
2024-11-26 23:45 ` Matthew Brost
2 siblings, 2 replies; 6+ messages in thread
From: Matthew Auld @ 2024-11-26 18:13 UTC (permalink / raw)
To: intel-xe; +Cc: Matthew Brost, Nirmoy Das, stable
On some HW we want to avoid the host caching PTEs, since access from GPU
side can be incoherent. However here the special migrate object is
mapping PTEs which are written from the host and potentially cached. Use
XE_BO_FLAG_PAGETABLE to ensure that non-cached mapping is used, on
platforms where this matters.
Fixes: 7a060d786cc1 ("drm/xe/mtl: Map PPGTT as CPU:WC")
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Nirmoy Das <nirmoy.das@intel.com>
Cc: <stable@vger.kernel.org> # v6.8+
---
drivers/gpu/drm/xe/xe_migrate.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 48e205a40fd2..1b97d90aadda 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -209,7 +209,8 @@ static int xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
num_entries * XE_PAGE_SIZE,
ttm_bo_type_kernel,
XE_BO_FLAG_VRAM_IF_DGFX(tile) |
- XE_BO_FLAG_PINNED);
+ XE_BO_FLAG_PINNED |
+ XE_BO_FLAG_PAGETABLE);
if (IS_ERR(bo))
return PTR_ERR(bo);
--
2.47.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 2/2] drm/xe/migrate: use XE_BO_FLAG_PAGETABLE
2024-11-26 18:13 ` [PATCH 2/2] drm/xe/migrate: use XE_BO_FLAG_PAGETABLE Matthew Auld
@ 2024-11-26 18:27 ` Nirmoy Das
2024-11-26 23:47 ` Matthew Brost
1 sibling, 0 replies; 6+ messages in thread
From: Nirmoy Das @ 2024-11-26 18:27 UTC (permalink / raw)
To: Matthew Auld, intel-xe; +Cc: Matthew Brost, Nirmoy Das, stable
On 11/26/2024 7:13 PM, Matthew Auld wrote:
> On some HW we want to avoid the host caching PTEs, since access from GPU
> side can be incoherent. However here the special migrate object is
> mapping PTEs which are written from the host and potentially cached. Use
> XE_BO_FLAG_PAGETABLE to ensure that non-cached mapping is used, on
> platforms where this matters.
>
> Fixes: 7a060d786cc1 ("drm/xe/mtl: Map PPGTT as CPU:WC")
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: Nirmoy Das <nirmoy.das@intel.com>
> Cc: <stable@vger.kernel.org> # v6.8+
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
> drivers/gpu/drm/xe/xe_migrate.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> index 48e205a40fd2..1b97d90aadda 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> @@ -209,7 +209,8 @@ static int xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
> num_entries * XE_PAGE_SIZE,
> ttm_bo_type_kernel,
> XE_BO_FLAG_VRAM_IF_DGFX(tile) |
> - XE_BO_FLAG_PINNED);
> + XE_BO_FLAG_PINNED |
> + XE_BO_FLAG_PAGETABLE);
> if (IS_ERR(bo))
> return PTR_ERR(bo);
>
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 2/2] drm/xe/migrate: use XE_BO_FLAG_PAGETABLE
2024-11-26 18:13 ` [PATCH 2/2] drm/xe/migrate: use XE_BO_FLAG_PAGETABLE Matthew Auld
2024-11-26 18:27 ` Nirmoy Das
@ 2024-11-26 23:47 ` Matthew Brost
1 sibling, 0 replies; 6+ messages in thread
From: Matthew Brost @ 2024-11-26 23:47 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-xe, Nirmoy Das, stable
On Tue, Nov 26, 2024 at 06:13:01PM +0000, Matthew Auld wrote:
> On some HW we want to avoid the host caching PTEs, since access from GPU
> side can be incoherent. However here the special migrate object is
> mapping PTEs which are written from the host and potentially cached. Use
> XE_BO_FLAG_PAGETABLE to ensure that non-cached mapping is used, on
> platforms where this matters.
>
> Fixes: 7a060d786cc1 ("drm/xe/mtl: Map PPGTT as CPU:WC")
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> Cc: Nirmoy Das <nirmoy.das@intel.com>
> Cc: <stable@vger.kernel.org> # v6.8+
> ---
> drivers/gpu/drm/xe/xe_migrate.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> index 48e205a40fd2..1b97d90aadda 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> @@ -209,7 +209,8 @@ static int xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
> num_entries * XE_PAGE_SIZE,
> ttm_bo_type_kernel,
> XE_BO_FLAG_VRAM_IF_DGFX(tile) |
> - XE_BO_FLAG_PINNED);
> + XE_BO_FLAG_PINNED |
> + XE_BO_FLAG_PAGETABLE);
> if (IS_ERR(bo))
> return PTR_ERR(bo);
>
> --
> 2.47.0
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/xe/migrate: fix pat index usage
2024-11-26 18:13 [PATCH 1/2] drm/xe/migrate: fix pat index usage Matthew Auld
2024-11-26 18:13 ` [PATCH 2/2] drm/xe/migrate: use XE_BO_FLAG_PAGETABLE Matthew Auld
@ 2024-11-26 18:25 ` Nirmoy Das
2024-11-26 23:45 ` Matthew Brost
2 siblings, 0 replies; 6+ messages in thread
From: Nirmoy Das @ 2024-11-26 18:25 UTC (permalink / raw)
To: Matthew Auld, intel-xe; +Cc: Matthew Brost, Nirmoy Das, stable
On 11/26/2024 7:13 PM, Matthew Auld wrote:
> XE_CACHE_WB must be converted into the per-platform pat index for that
> particular caching mode, otherwise we are just encoding whatever happens
> to be the value of that enum.
>
> Fixes: e8babb280b5e ("drm/xe: Convert multiple bind ops into single job")
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: Nirmoy Das <nirmoy.das@intel.com>
> Cc: <stable@vger.kernel.org> # v6.12+
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
> drivers/gpu/drm/xe/xe_migrate.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> index cfd31ae49cc1..48e205a40fd2 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> @@ -1350,6 +1350,7 @@ __xe_migrate_update_pgtables(struct xe_migrate *m,
>
> /* For sysmem PTE's, need to map them in our hole.. */
> if (!IS_DGFX(xe)) {
> + u16 pat_index = xe->pat.idx[XE_CACHE_WB];
> u32 ptes, ofs;
>
> ppgtt_ofs = NUM_KERNEL_PDE - 1;
> @@ -1409,7 +1410,7 @@ __xe_migrate_update_pgtables(struct xe_migrate *m,
> pt_bo->update_index = current_update;
>
> addr = vm->pt_ops->pte_encode_bo(pt_bo, 0,
> - XE_CACHE_WB, 0);
> + pat_index, 0);
> bb->cs[bb->len++] = lower_32_bits(addr);
> bb->cs[bb->len++] = upper_32_bits(addr);
> }
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 1/2] drm/xe/migrate: fix pat index usage
2024-11-26 18:13 [PATCH 1/2] drm/xe/migrate: fix pat index usage Matthew Auld
2024-11-26 18:13 ` [PATCH 2/2] drm/xe/migrate: use XE_BO_FLAG_PAGETABLE Matthew Auld
2024-11-26 18:25 ` [PATCH 1/2] drm/xe/migrate: fix pat index usage Nirmoy Das
@ 2024-11-26 23:45 ` Matthew Brost
2 siblings, 0 replies; 6+ messages in thread
From: Matthew Brost @ 2024-11-26 23:45 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-xe, Nirmoy Das, stable
On Tue, Nov 26, 2024 at 06:13:00PM +0000, Matthew Auld wrote:
> XE_CACHE_WB must be converted into the per-platform pat index for that
> particular caching mode, otherwise we are just encoding whatever happens
> to be the value of that enum.
>
> Fixes: e8babb280b5e ("drm/xe: Convert multiple bind ops into single job")
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> Cc: Nirmoy Das <nirmoy.das@intel.com>
> Cc: <stable@vger.kernel.org> # v6.12+
> ---
> drivers/gpu/drm/xe/xe_migrate.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> index cfd31ae49cc1..48e205a40fd2 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> @@ -1350,6 +1350,7 @@ __xe_migrate_update_pgtables(struct xe_migrate *m,
>
> /* For sysmem PTE's, need to map them in our hole.. */
> if (!IS_DGFX(xe)) {
> + u16 pat_index = xe->pat.idx[XE_CACHE_WB];
> u32 ptes, ofs;
>
> ppgtt_ofs = NUM_KERNEL_PDE - 1;
> @@ -1409,7 +1410,7 @@ __xe_migrate_update_pgtables(struct xe_migrate *m,
> pt_bo->update_index = current_update;
>
> addr = vm->pt_ops->pte_encode_bo(pt_bo, 0,
> - XE_CACHE_WB, 0);
> + pat_index, 0);
> bb->cs[bb->len++] = lower_32_bits(addr);
> bb->cs[bb->len++] = upper_32_bits(addr);
> }
> --
> 2.47.0
>
^ permalink raw reply [flat|nested] 6+ messages in thread
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2024-11-26 18:27 ` Nirmoy Das
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