From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EEE4F1DF26E; Wed, 22 Apr 2026 00:57:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776819449; cv=none; b=I/8LXENhLo857b7Q6ht4IiKbWJi3Kuj9co0igP+aYvPw+KeeP+zGtShFmPpUvM+SSYJr/NsSWkaZ93ubX5iHD4GnEZHhFbf3QUWx1nN41rjnd77RQ2Zlbzib7v/ftrrl4+onDWqrbEagm/DcA5dqCiBVsI9LFflqwEg8KUiEkF4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776819449; c=relaxed/simple; bh=nhehAw6Z+DPT+nNjSZV2c7dJLnh4W2YjeY8ZBqsswOs=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=iF4Z9Rth3Lwwa1h0cJMUj8BAGiMsO1BOGyWLfYQ8HBuGmJKjIBwNJeUdb6Lyykyo33H6T6/w4I1sfoi/WQSs5zSxc7y+2Z0pHdt9xlju/Hy+VDBUInnaSEfMPLXWLloYOem8pIJ8J01WYIlhdPN30gMwaBPdVPcZfGpOTXJbWDQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Ow712zn0; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Ow712zn0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776819448; x=1808355448; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=nhehAw6Z+DPT+nNjSZV2c7dJLnh4W2YjeY8ZBqsswOs=; b=Ow712zn0mgufhCneo08gYIOyrqv4WXbNFHeT6vxcMyLB3PIPZMrRtqAr 9AdOj4MudeRoI7r/b6qrTww5N9LpCfbvPDK0uqFGZtVTzsL1YRMjX8s5j Sytg+3wk+WTvErb7RS0cliUWH2zIhEe1yP++WRUJkF3bNbinfJvgAq12O m5+0BSWgt0GZsgB0sVSckRw6wLeP1DGyTNzWiQFp1129P0AnpiO+DGHi6 k4xz6CPHVKoer8dtvp1+S9k3R7NG1AYAr1cxlPlJjXrsU9XqrCh9PlzK8 B16V9fpFleZKjZfFNtjUSMuDXRhEidJl7x34rpsfqs+0DF04aNpBFa2jc w==; X-CSE-ConnectionGUID: qiPHIe0DTLCrCNFeqtYPxA== X-CSE-MsgGUID: 0oNrcRYURmiRR+55gWYPlQ== X-IronPort-AV: E=McAfee;i="6800,10657,11763"; a="77835357" X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="77835357" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 17:57:27 -0700 X-CSE-ConnectionGUID: u7N3OE2PTwK/DKD5a6g9kw== X-CSE-MsgGUID: qniPAnqBRme7nBL9zTBu6Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="255673856" Received: from dapengmi-mobl1.ccr.corp.intel.com (HELO [10.124.241.147]) ([10.124.241.147]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 17:57:23 -0700 Message-ID: Date: Wed, 22 Apr 2026 08:57:20 +0800 Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [Patch v2 1/4] perf/x86/intel: Clear stale ACR mask before updating new mask To: Andi Kleen Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Eranian Stephane , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , stable@vger.kernel.org References: <20260420024528.2130065-1-dapeng1.mi@linux.intel.com> <20260420024528.2130065-2-dapeng1.mi@linux.intel.com> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 4/22/2026 6:29 AM, Andi Kleen wrote: >> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c >> index 4768236c054b..774ae9a4eeaf 100644 >> --- a/arch/x86/events/intel/core.c >> +++ b/arch/x86/events/intel/core.c >> @@ -3334,6 +3334,12 @@ static void intel_pmu_acr_late_setup(struct cpu_hw_events *cpuc) >> struct perf_event *event, *leader; >> int i, j, idx; >> >> + /* Clear stale ACR mask first. */ >> + for (i = 0; i < cpuc->n_events; i++) { >> + event = cpuc->event_list[i]; >> + event->hw.config1 = 0; >> + } > Are you sure nothing else could be using config1? > > In principle ACR events can be used with some config1 setting. Yes, the field "hw.config1" is introduced for support auto counter reload, it's only used to store the ACR counter indices. Thanks. https://lore.kernel.org/all/20250327195217.2683619-6-kan.liang@linux.intel.com/ > > > -Andi