From: Sohil Mehta <sohil.mehta@intel.com>
To: Suchit Karunakaran <suchitkarunakaran@gmail.com>,
<tglx@linutronix.de>, <mingo@redhat.com>, <bp@alien8.de>,
<dave.hansen@linux.intel.com>, <hpa@zytor.com>,
<darwi@linutronix.de>, <peterz@infradead.org>,
<ravi.bangoria@amd.com>
Cc: <skhan@linuxfoundation.org>,
<linux-kernel-mentees@lists.linux.dev>,
<linux-kernel@vger.kernel.org>, <stable@vger.kernel.org>
Subject: Re: [PATCH v5] x86/cpu/intel: Fix the constant_tsc model check for Pentium 4
Date: Wed, 6 Aug 2025 16:31:54 -0700 [thread overview]
Message-ID: <f8f1faa6-d35d-439f-b5c3-2c20f2e2bb8d@intel.com> (raw)
In-Reply-To: <20250806153433.9070-1-suchitkarunakaran@gmail.com>
On 8/6/2025 8:34 AM, Suchit Karunakaran wrote:
> Pentium 4's which are INTEL_P4_PRESCOTT (model 0x03) and later have
> a constant TSC. This was correctly captured until commit fadb6f569b10
> ("x86/cpu/intel: Limit the non-architectural constant_tsc model checks").
>
> In that commit, an error was introduced while selecting the last P4
> model (0x06) as the upper bound. Model 0x06 was transposed to
> INTEL_P4_WILLAMETTE, which is just plain wrong. That was presumably a
> simple typo, probably just copying and pasting the wrong P4 model.
>
> Fix the constant TSC logic to cover all later P4 models. End at
> INTEL_P4_CEDARMILL which accurately corresponds to the last P4 model.
>
> Fixes: fadb6f569b10 ("x86/cpu/intel: Limit the non-architectural constant_tsc model checks")
> Cc: <stable@vger.kernel.org> # v6.15
> Signed-off-by: Suchit Karunakaran <suchitkarunakaran@gmail.com>
> ---
Reviewed-by: Sohil Mehta <sohil.mehta@intel.com>
prev parent reply other threads:[~2025-08-06 23:31 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-06 15:34 [PATCH v5] x86/cpu/intel: Fix the constant_tsc model check for Pentium 4 Suchit Karunakaran
2025-08-06 15:38 ` Suchit Karunakaran
2025-08-06 23:31 ` Sohil Mehta [this message]
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