Re: [PATCH 1/3] drm/bridge: ti-sn65dsi83: fix CHA_DSI_CLK_RANGE rounding

Marek Vasut
2026-02-27T10:39:17Z

On 2/26/26 5:16 PM, Luca Ceresoli wrote:
> The DSI frequency must be in the range:
>
> (CHA_DSI_CLK_RANGE * 5 MHz) <= DSI freq < ((CHA_DSI_CLK_RANGE + 1) * 5 MHz)
>
> So the register value shouldpoint to the lower range value, but

should point (missing space)

> DIV_ROUND_UP() rounds the division to the higher range value, resulting in
> an excess of 1 (unless the frequency is an exact multiple of 5 MHz).
>
> For example for a 437100000 MHz clock CHA_DSI_CLK_RANGE should be 87 (0x57):
>
> (87 * 5 = 435) <= 437.1 < (88 * 5 = 440)
>
> but current code returns 88 (0x58).
>
> Fix the computation by removing the DIV_ROUND_UP().
>
> Fixes: ceb515ba29ba ("drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 driver")
> Cc: stable@vger.kernel.org
> Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>

Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>

Thanks !