* [PATCH v2] drm/i915/dg2: Update workaround 22013059131
@ 2026-03-04 17:12 Jia Yao
2026-03-10 7:50 ` Krzysztof Karas
0 siblings, 1 reply; 2+ messages in thread
From: Jia Yao @ 2026-03-04 17:12 UTC (permalink / raw)
To: intel-gfx
Cc: Jia Yao, Alex Zuo, Shuicheng Lin, Xin Wang, stable, Matt Roper,
Rodrigo Vivi
Setting the LSC chicken bit FORCE_1_SUB_MESSAGE_PER_FRAGMENT is not
required as part of the workaround, so it can be removed.
v2: Update commit message: clarify why LSC chicken bit
FORCE_1_SUB_MESSAGE_PER_FRAGMENT is removed.
Bspec: 54833
Fixes: 645cc0b9d972 ("drm/i915/dg2: Add initial gt/ctx/engine workarounds")
Cc: Alex Zuo <alex.zuo@intel.com>
Cc: Shuicheng Lin <shuicheng.lin@intel.com>
Cc: Xin Wang <x.wang@intel.com>
Cc: stable@vger.kernel.org
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jia Yao <jia.yao@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index f78d991ad7bf..404a6ffafbd0 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2867,10 +2867,6 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
MAXREQS_PER_BANK,
REG_FIELD_PREP(MAXREQS_PER_BANK, 2));
- /* Wa_22013059131:dg2 */
- wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
- FORCE_1_SUB_MESSAGE_PER_FRAGMENT);
-
/*
* Wa_22012654132
*
--
2.43.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH v2] drm/i915/dg2: Update workaround 22013059131
2026-03-04 17:12 [PATCH v2] drm/i915/dg2: Update workaround 22013059131 Jia Yao
@ 2026-03-10 7:50 ` Krzysztof Karas
0 siblings, 0 replies; 2+ messages in thread
From: Krzysztof Karas @ 2026-03-10 7:50 UTC (permalink / raw)
To: Jia Yao
Cc: intel-gfx, Alex Zuo, Shuicheng Lin, Xin Wang, stable, Matt Roper,
Rodrigo Vivi
Hi Jia,
> Setting the LSC chicken bit FORCE_1_SUB_MESSAGE_PER_FRAGMENT is not
> required as part of the workaround, so it can be removed.
>
> v2: Update commit message: clarify why LSC chicken bit
> FORCE_1_SUB_MESSAGE_PER_FRAGMENT is removed.
>
> Bspec: 54833
> Fixes: 645cc0b9d972 ("drm/i915/dg2: Add initial gt/ctx/engine workarounds")
> Cc: Alex Zuo <alex.zuo@intel.com>
> Cc: Shuicheng Lin <shuicheng.lin@intel.com>
> Cc: Xin Wang <x.wang@intel.com>
> Cc: stable@vger.kernel.org
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Jia Yao <jia.yao@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ----
> 1 file changed, 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index f78d991ad7bf..404a6ffafbd0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2867,10 +2867,6 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> MAXREQS_PER_BANK,
> REG_FIELD_PREP(MAXREQS_PER_BANK, 2));
>
> - /* Wa_22013059131:dg2 */
> - wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
> - FORCE_1_SUB_MESSAGE_PER_FRAGMENT);
> -
> /*
> * Wa_22012654132
> *
> --
> 2.43.0
>
The fix looks sane to me:
Reviewed-by: Krzysztof Karas <krzysztof.karas@intel.com>
--
Best Regards,
Krzysztof
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