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[2001:4c4e:24d8:f200:5aa4:d4f9:1f46:dae7]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c255ee75a36sm413076466b.28.2026.08.31.04.39.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 04:39:41 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: christian.koenig@amd.com, alexander.deucher@amd.com, amd-gfx@lists.freedesktop.org Cc: Arunpravin Paneer Selvam , stable@vger.kernel.org, Arunpravin Paneer Selvam Subject: Re: [PATCH] drm/amdgpu: skip the VMID 0 flush for VRAM clear-on-release Date: Mon, 31 Aug 2026 13:39:40 +0200 Message-ID: In-Reply-To: <20260828044734.135460-1-Arunpravin.PaneerSelvam@amd.com> References: <20260828044734.135460-1-Arunpravin.PaneerSelvam@amd.com> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On 2026. augusztus 28., p=C3=A9ntek 6:47:34 k=C3=B6z=C3=A9p-eur=C3=B3pai ny= =C3=A1ri id=C5=91 Arunpravin=20 Paneer Selvam wrote: > Clear-on-release only runs on VRAM, which amdgpu_ttm_map_buffer() reaches > via its direct MC address without programming a GART window, yet the wipe > still forces a VMID 0 flush. Makes sense. We don't need the VM flush when we are not changing the page tables. I agree with the patch, just would like to ask a few questions to better=20 understand the underlying problem: > On GFX11 (e.g. Navi33) that spurious SDMA > flush can wedge the engine What is happening when the SDMA engine is wedged? Can it be recovered by an= =20 SDMA queue reset? Is it just a hang, or can it cause other issues such as p= age=20 faults? > only flush when a GART window is actually used. Does that mean that there is still a risk of the wedge when the GART window= s=20 are used? Can you remind me when/why we need the GART windows exactly? > Fixes: a68c7eaa7a8f ("drm/amdgpu: Enable clear page functionality") > Cc: stable@vger.kernel.org > Cc: Christian K=C3=B6nig > Signed-off-by: Arunpravin Paneer Selvam Reviewed-by: Timur Krist=C3=B3f Thanks and best regards, Timur > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index > 6c07cee8e8777..2e6c98c2f1efa 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > @@ -2578,6 +2578,7 @@ int amdgpu_ttm_clear_buffer(struct > amdgpu_ttm_buffer_entity *entity, struct amdgpu_device *adev =3D > amdgpu_ttm_adev(bo->tbo.bdev); > struct dma_fence *fence =3D NULL; > struct amdgpu_res_cursor dst; > + bool vm_needs_flush; > int r; >=20 > if (!entity) > @@ -2585,6 +2586,8 @@ int amdgpu_ttm_clear_buffer(struct > amdgpu_ttm_buffer_entity *entity, >=20 > amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst); >=20 > + vm_needs_flush =3D bo->tbo.resource->start =3D=3D=20 AMDGPU_BO_INVALID_OFFSET; > + > mutex_lock(&entity->lock); > while (dst.remaining) { > struct dma_fence *next; > @@ -2605,7 +2608,7 @@ int amdgpu_ttm_clear_buffer(struct > amdgpu_ttm_buffer_entity *entity, >=20 > r =3D amdgpu_ttm_fill_mem(adev, entity, > 0, to, cur_size, resv, > - &next, true,=20 k_job_id); > + &next, vm_needs_flush,=20 k_job_id); > if (r) > goto error;