From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from unicorn.mansr.com ([81.2.72.234]:34611 "EHLO unicorn.mansr.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750735AbcBKPRH convert rfc822-to-8bit (ORCPT ); Thu, 11 Feb 2016 10:17:07 -0500 From: =?iso-8859-1?Q?M=E5ns_Rullg=E5rd?= To: Andy Shevchenko Cc: Vinod Koul , dmaengine@vger.kernel.org, Viresh Kumar , stable@vger.kernel.org Subject: Re: [PATCH v1 1/1] dmaengine: dw: disable BLOCK IRQs for non-cyclic xfer References: <1455112782-75078-1-git-send-email-andriy.shevchenko@linux.intel.com> Date: Thu, 11 Feb 2016 15:17:01 +0000 In-Reply-To: <1455112782-75078-1-git-send-email-andriy.shevchenko@linux.intel.com> (Andy Shevchenko's message of "Wed, 10 Feb 2016 15:59:42 +0200") Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8BIT Sender: stable-owner@vger.kernel.org List-ID: Andy Shevchenko writes: > The commit 2895b2cad6e7 ("dmaengine: dw: fix cyclic transfer callbacks") > re-enabled BLOCK interrupts with regard to make cyclic transfers work. However, > this change becomes a regression for non-cyclic transfers as interrupt counters > under stress test had been grown enormously (approximately per 4-5 bytes in the > UART loop back test). > > Taking into consideration above enable BLOCK interrupts if and only if channel > is programmed to perform cyclic transfer. > > Fixes: 2895b2cad6e7 ("dmaengine: dw: fix cyclic transfer callbacks") > Signed-off-by: Andy Shevchenko > Cc: Mans Rullgard > Cc: Viresh Kumar > Cc: > --- > drivers/dma/dw/core.c | 15 ++++++++++----- > 1 file changed, 10 insertions(+), 5 deletions(-) Acked-by: Mans Rullgard Tested-by: Mans Rullgard > diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c > index e893318..5ad0ec1 100644 > --- a/drivers/dma/dw/core.c > +++ b/drivers/dma/dw/core.c > @@ -156,7 +156,6 @@ static void dwc_initialize(struct dw_dma_chan *dwc) > > /* Enable interrupts */ > channel_set_bit(dw, MASK.XFER, dwc->mask); > - channel_set_bit(dw, MASK.BLOCK, dwc->mask); > channel_set_bit(dw, MASK.ERROR, dwc->mask); > > dwc->initialized = true; > @@ -588,6 +587,9 @@ static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, > > spin_unlock_irqrestore(&dwc->lock, flags); > } > + > + /* Re-enable interrupts */ > + channel_set_bit(dw, MASK.BLOCK, dwc->mask); > } > > /* ------------------------------------------------------------------------- */ > @@ -618,11 +620,8 @@ static void dw_dma_tasklet(unsigned long data) > dwc_scan_descriptors(dw, dwc); > } > > - /* > - * Re-enable interrupts. > - */ > + /* Re-enable interrupts */ > channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); > - channel_set_bit(dw, MASK.BLOCK, dw->all_chan_mask); > channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); > } > > @@ -1261,6 +1260,7 @@ static void dwc_free_chan_resources(struct dma_chan *chan) > int dw_dma_cyclic_start(struct dma_chan *chan) > { > struct dw_dma_chan *dwc = to_dw_dma_chan(chan); > + struct dw_dma *dw = to_dw_dma(chan->device); > unsigned long flags; > > if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { > @@ -1269,7 +1269,12 @@ int dw_dma_cyclic_start(struct dma_chan *chan) > } > > spin_lock_irqsave(&dwc->lock, flags); > + > + /* Enable interrupts to perform cyclic transfer */ > + channel_set_bit(dw, MASK.BLOCK, dwc->mask); > + > dwc_dostart(dwc, dwc->cdesc->desc[0]); > + > spin_unlock_irqrestore(&dwc->lock, flags); > > return 0; > -- > 2.7.0 > -- M�ns Rullg�rd