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From: Jarkko Sakkinen <jarkko.sakkinen-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
To: Christophe Ricard
	<christophe.ricard-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: jean-luc.blanc-qxv4g6HH51o@public.gmane.org,
	ashley-fm2HMyfA2y6tG0bUXCXiUA@public.gmane.org,
	tpmdd-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org,
	christophe-h.ricard-qxv4g6HH51o@public.gmane.org,
	Peter Huewe <peter.huewe-d0qZbvYSIPpWk0Htik3J/w@public.gmane.org>,
	benoit.houyere-qxv4g6HH51o@public.gmane.org
Subject: Re: [PATCH v7 7/7] tpm/tpm_tis_spi: Add support for spi phy
Date: Fri, 13 May 2016 16:13:00 +0300	[thread overview]
Message-ID: <20160513131300.GC28421@intel.com> (raw)
In-Reply-To: <1462388788-2410-8-git-send-email-christophe-h.ricard-qxv4g6HH51o@public.gmane.org>

On Wed, May 04, 2016 at 09:06:28PM +0200, Christophe Ricard wrote:
> Spi protocol standardized by the TCG is now supported by most of TPM
> vendors.
> 
> It supports SPI Bit Protocol as describe in the TCG PTP
> specification (chapter 6.4.6 SPI Bit Protocol).
> 
> Irq mode is not supported.
> 
> Signed-off-by: Peter Huewe <peter.huewe-d0qZbvYSIPpWk0Htik3J/w@public.gmane.org>
> Signed-off-by: Alexander Steffen <Alexander.Steffen-d0qZbvYSIPpWk0Htik3J/w@public.gmane.org>
> Signed-off-by: Christophe Ricard <christophe-h.ricard-qxv4g6HH51o@public.gmane.org>

Reviewed-by: Jarkko Sakkinen <jarkko.sakkinen-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>

> ---
>  .../bindings/security/tpm/tpm_tis_spi.txt          |  24 ++
>  drivers/char/tpm/Kconfig                           |  12 +
>  drivers/char/tpm/Makefile                          |   1 +
>  drivers/char/tpm/tpm_tis_spi.c                     | 272 +++++++++++++++++++++
>  4 files changed, 309 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/security/tpm/tpm_tis_spi.txt
>  create mode 100644 drivers/char/tpm/tpm_tis_spi.c
> 
> diff --git a/Documentation/devicetree/bindings/security/tpm/tpm_tis_spi.txt b/Documentation/devicetree/bindings/security/tpm/tpm_tis_spi.txt
> new file mode 100644
> index 0000000..85741cd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/security/tpm/tpm_tis_spi.txt
> @@ -0,0 +1,24 @@
> +Required properties:
> +- compatible: should be one of the following
> +    "st,st33htpm-spi"
> +    "infineon,slb9670"
> +    "tcg,tpm_tis-spi"
> +- spi-max-frequency: Maximum SPI frequency (depends on TPMs).
> +
> +Optional SoC Specific Properties:
> +- pinctrl-names: Contains only one value - "default".
> +- pintctrl-0: Specifies the pin control groups used for this controller.
> +
> +Example (for ARM-based BeagleBoard xM with TPM_TIS on SPI4):
> +
> +&mcspi4 {
> +
> +        status = "okay";
> +
> +        tpm_tis@0 {
> +
> +                compatible = "tcg,tpm_tis-spi";
> +
> +                spi-max-frequency = <10000000>;
> +        };
> +};
> diff --git a/drivers/char/tpm/Kconfig b/drivers/char/tpm/Kconfig
> index 241ff4c..9faa0b1 100644
> --- a/drivers/char/tpm/Kconfig
> +++ b/drivers/char/tpm/Kconfig
> @@ -41,6 +41,18 @@ config TCG_TIS
>  	  within Linux. To compile this driver as a module, choose  M here;
>  	  the module will be called tpm_tis.
>  
> +config TCG_TIS_SPI
> +	tristate "TPM Interface Specification 1.3 Interface / TPM 2.0 FIFO Interface - (SPI)"
> +	depends on SPI
> +	select TCG_TIS_CORE
> +	---help---
> +	  If you have a TPM security chip which is connected to a regular,
> +	  non-tcg SPI master (i.e. most embedded platforms) that is compliant with the
> +	  TCG TIS 1.3 TPM specification (TPM1.2) or the TCG PTP FIFO
> +	  specification (TPM2.0) say Yes and it will be accessible from
> +	  within Linux. To compile this driver as a module, choose  M here;
> +	  the module will be called tpm_tis_spi.
> +
>  config TCG_TIS_I2C_ATMEL
>  	tristate "TPM Interface Specification 1.2 Interface (I2C - Atmel)"
>  	depends on I2C
> diff --git a/drivers/char/tpm/Makefile b/drivers/char/tpm/Makefile
> index 662221f..a385fb8 100644
> --- a/drivers/char/tpm/Makefile
> +++ b/drivers/char/tpm/Makefile
> @@ -14,6 +14,7 @@ endif
>  endif
>  obj-$(CONFIG_TCG_TIS_CORE) += tpm_tis_core.o
>  obj-$(CONFIG_TCG_TIS) += tpm_tis.o
> +obj-$(CONFIG_TCG_TIS_SPI) += tpm_tis_spi.o
>  obj-$(CONFIG_TCG_TIS_I2C_ATMEL) += tpm_i2c_atmel.o
>  obj-$(CONFIG_TCG_TIS_I2C_INFINEON) += tpm_i2c_infineon.o
>  obj-$(CONFIG_TCG_TIS_I2C_NUVOTON) += tpm_i2c_nuvoton.o
> diff --git a/drivers/char/tpm/tpm_tis_spi.c b/drivers/char/tpm/tpm_tis_spi.c
> new file mode 100644
> index 0000000..dbaad9c
> --- /dev/null
> +++ b/drivers/char/tpm/tpm_tis_spi.c
> @@ -0,0 +1,272 @@
> +/*
> + * Copyright (C) 2015 Infineon Technologies AG
> + * Copyright (C) 2016 STMicroelectronics SAS
> + *
> + * Authors:
> + * Peter Huewe <peter.huewe-d0qZbvYSIPpWk0Htik3J/w@public.gmane.org>
> + * Christophe Ricard <christophe-h.ricard-qxv4g6HH51o@public.gmane.org>
> + *
> + * Maintained by: <tpmdd-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>
> + *
> + * Device driver for TCG/TCPA TPM (trusted platform module).
> + * Specifications at www.trustedcomputinggroup.org
> + *
> + * This device driver implements the TPM interface as defined in
> + * the TCG TPM Interface Spec version 1.3, revision 27 via _raw/native
> + * SPI access_.
> + *
> + * It is based on the original tpm_tis device driver from Leendert van
> + * Dorn and Kyleen Hall and Jarko Sakkinnen.

I think that it is sufficient to say that this would just say that this
is derived works from the original tpm_tis driver. No need for author
names.

/Jarkko

> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation, version 2 of the
> + * License.
> + */
> +
> +#include <linux/init.h>
> +#include <linux/module.h>
> +#include <linux/moduleparam.h>
> +#include <linux/slab.h>
> +#include <linux/interrupt.h>
> +#include <linux/wait.h>
> +#include <linux/acpi.h>
> +#include <linux/freezer.h>
> +
> +#include <linux/module.h>
> +#include <linux/spi/spi.h>
> +#include <linux/gpio.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_gpio.h>
> +#include <linux/tpm.h>
> +#include "tpm.h"
> +#include "tpm_tis_core.h"
> +
> +#define MAX_SPI_FRAMESIZE 64
> +
> +struct tpm_tis_spi_phy {
> +	struct tpm_tis_data priv;
> +	struct spi_device *spi_device;
> +
> +	u8 tx_buf[MAX_SPI_FRAMESIZE + 4];
> +	u8 rx_buf[MAX_SPI_FRAMESIZE + 4];
> +};
> +
> +static inline struct tpm_tis_spi_phy *to_tpm_tis_spi_phy(struct tpm_tis_data *data)
> +{
> +	return container_of(data, struct tpm_tis_spi_phy, priv);
> +}
> +
> +static int tpm_tis_spi_read_bytes(struct tpm_tis_data *data, u32 addr,
> +				  u16 len, u8 *result)
> +{
> +	struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data);
> +	int ret, i;
> +	struct spi_message m;
> +	struct spi_transfer spi_xfer = {
> +		.tx_buf = phy->tx_buf,
> +		.rx_buf = phy->rx_buf,
> +		.len = 4,
> +	};
> +
> +	if (len > MAX_SPI_FRAMESIZE)
> +		return -ENOMEM;
> +
> +	phy->tx_buf[0] = 0x80 | (len - 1);
> +	phy->tx_buf[1] = 0xd4;
> +	phy->tx_buf[2] = (addr >> 8)  & 0xFF;
> +	phy->tx_buf[3] = addr	      & 0xFF;
> +
> +	spi_xfer.cs_change = 1;
> +	spi_message_init(&m);
> +	spi_message_add_tail(&spi_xfer, &m);
> +
> +	spi_bus_lock(phy->spi_device->master);
> +	ret = spi_sync_locked(phy->spi_device, &m);
> +	if (ret < 0)
> +		goto exit;
> +
> +	memset(phy->tx_buf, 0, len);
> +
> +	/* According to TCG PTP specification, if there is no TPM present at
> +	 * all, then the design has a weak pull-up on MISO. If a TPM is not
> +	 * present, a pull-up on MISO means that the SB controller sees a 1,
> +	 * and will latch in 0xFF on the read.
> +	 */
> +	for (i = 0; (phy->rx_buf[0] & 0x01) == 0 && i < TPM_RETRY; i++) {
> +		spi_xfer.len = 1;
> +		spi_message_init(&m);
> +		spi_message_add_tail(&spi_xfer, &m);
> +		ret = spi_sync_locked(phy->spi_device, &m);
> +		if (ret < 0)
> +			goto exit;
> +	}
> +
> +	spi_xfer.cs_change = 0;
> +	spi_xfer.len = len;
> +	spi_xfer.rx_buf = result;
> +
> +	spi_message_init(&m);
> +	spi_message_add_tail(&spi_xfer, &m);
> +	ret = spi_sync_locked(phy->spi_device, &m);
> +
> +exit:
> +	spi_bus_unlock(phy->spi_device->master);
> +	return ret;
> +}
> +
> +static int tpm_tis_spi_write_bytes(struct tpm_tis_data *data, u32 addr,
> +				   u16 len, u8 *value)
> +{
> +	struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data);
> +	int ret, i;
> +	struct spi_message m;
> +	struct spi_transfer spi_xfer = {
> +		.tx_buf = phy->tx_buf,
> +		.rx_buf = phy->rx_buf,
> +		.len = 4,
> +	};
> +
> +	if (len > MAX_SPI_FRAMESIZE)
> +		return -ENOMEM;
> +
> +	phy->tx_buf[0] = len - 1;
> +	phy->tx_buf[1] = 0xd4;
> +	phy->tx_buf[2] = (addr >> 8)  & 0xFF;
> +	phy->tx_buf[3] = addr         & 0xFF;
> +
> +	spi_xfer.cs_change = 1;
> +	spi_message_init(&m);
> +	spi_message_add_tail(&spi_xfer, &m);
> +
> +	spi_bus_lock(phy->spi_device->master);
> +	ret = spi_sync_locked(phy->spi_device, &m);
> +	if (ret < 0)
> +		goto exit;
> +
> +	memset(phy->tx_buf, 0, len);
> +
> +	/* According to TCG PTP specification, if there is no TPM present at
> +	 * all, then the design has a weak pull-up on MISO. If a TPM is not
> +	 * present, a pull-up on MISO means that the SB controller sees a 1,
> +	 * and will latch in 0xFF on the read.
> +	 */
> +	for (i = 0; (phy->rx_buf[0] & 0x01) == 0 && i < TPM_RETRY; i++) {
> +		spi_xfer.len = 1;
> +		spi_message_init(&m);
> +		spi_message_add_tail(&spi_xfer, &m);
> +		ret = spi_sync_locked(phy->spi_device, &m);
> +		if (ret < 0)
> +			goto exit;
> +	}
> +
> +	spi_xfer.len = len;
> +	spi_xfer.tx_buf = value;
> +	spi_xfer.cs_change = 0;
> +	spi_xfer.tx_buf = value;
> +	spi_message_init(&m);
> +	spi_message_add_tail(&spi_xfer, &m);
> +	ret = spi_sync_locked(phy->spi_device, &m);
> +
> +exit:
> +	spi_bus_unlock(phy->spi_device->master);
> +	return ret;
> +}
> +
> +static int tpm_tis_spi_read16(struct tpm_tis_data *data, u32 addr, u16 *result)
> +{
> +	int rc;
> +
> +	rc = data->phy_ops->read_bytes(data, addr, sizeof(u16), (u8 *)result);
> +	if (!rc)
> +		*result = le16_to_cpu(*result);
> +	return rc;
> +}
> +
> +static int tpm_tis_spi_read32(struct tpm_tis_data *data, u32 addr, u32 *result)
> +{
> +	int rc;
> +
> +	rc = data->phy_ops->read_bytes(data, addr, sizeof(u32), (u8 *)result);
> +	if (!rc)
> +		*result = le32_to_cpu(*result);
> +	return rc;
> +}
> +
> +static int tpm_tis_spi_write32(struct tpm_tis_data *data, u32 addr, u32 value)
> +{
> +	value = cpu_to_le32(value);
> +	return data->phy_ops->write_bytes(data, addr, sizeof(u32),
> +					   (u8 *)&value);
> +}
> +
> +static const struct tpm_tis_phy_ops tpm_spi_phy_ops = {
> +	.read_bytes = tpm_tis_spi_read_bytes,
> +	.write_bytes = tpm_tis_spi_write_bytes,
> +	.read16 = tpm_tis_spi_read16,
> +	.read32 = tpm_tis_spi_read32,
> +	.write32 = tpm_tis_spi_write32,
> +};
> +
> +static int tpm_tis_spi_probe(struct spi_device *dev)
> +{
> +	struct tpm_tis_spi_phy *phy;
> +
> +	phy = devm_kzalloc(&dev->dev, sizeof(struct tpm_tis_spi_phy),
> +			   GFP_KERNEL);
> +	if (!phy)
> +		return -ENOMEM;
> +
> +	phy->spi_device = dev;
> +
> +	return tpm_tis_core_init(&dev->dev, &phy->priv, -1, &tpm_spi_phy_ops,
> +				 NULL);
> +}
> +
> +static SIMPLE_DEV_PM_OPS(tpm_tis_pm, tpm_pm_suspend, tpm_tis_resume);
> +
> +static int tpm_tis_spi_remove(struct spi_device *dev)
> +{
> +	struct tpm_chip *chip = spi_get_drvdata(dev);
> +
> +	tpm_chip_unregister(chip);
> +	tpm_tis_remove(chip);
> +	return 0;
> +}
> +
> +static const struct spi_device_id tpm_tis_spi_id[] = {
> +	{"tpm_tis_spi", 0},
> +	{}
> +};
> +MODULE_DEVICE_TABLE(spi, tpm_tis_spi_id);
> +
> +static const struct of_device_id of_tis_spi_match[] = {
> +	{ .compatible = "st,st33htpm-spi", },
> +	{ .compatible = "infineon,slb9670", },
> +	{ .compatible = "tcg,tpm_tis-spi", },
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, of_tis_spi_match);
> +
> +static const struct acpi_device_id acpi_tis_spi_match[] = {
> +	{"SMO0768", 0},
> +	{}
> +};
> +MODULE_DEVICE_TABLE(acpi, acpi_tis_spi_match);
> +
> +static struct spi_driver tpm_tis_spi_driver = {
> +	.driver = {
> +		.owner = THIS_MODULE,
> +		.name = "tpm_tis_spi",
> +		.pm = &tpm_tis_pm,
> +		.of_match_table = of_match_ptr(of_tis_spi_match),
> +		.acpi_match_table = ACPI_PTR(acpi_tis_spi_match),
> +	},
> +	.probe = tpm_tis_spi_probe,
> +	.remove = tpm_tis_spi_remove,
> +	.id_table = tpm_tis_spi_id,
> +};
> +module_spi_driver(tpm_tis_spi_driver);
> +
> +MODULE_DESCRIPTION("TPM Driver for native SPI access");
> +MODULE_LICENSE("GPL");
> -- 
> 2.1.4
> 

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      parent reply	other threads:[~2016-05-13 13:13 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-04 19:06 [PATCH v7 0/7] Rework of tpm_tis to share common logic accross phy's (lpc/spi/-i2c-) Christophe Ricard
     [not found] ` <1462388788-2410-1-git-send-email-christophe-h.ricard-qxv4g6HH51o@public.gmane.org>
2016-05-04 19:06   ` [PATCH v7 1/7] tpm: Add include guards in tpm.h Christophe Ricard
2016-05-04 19:06   ` [PATCH v7 2/7] tpm: tpm_tis: Share common data between phys Christophe Ricard
     [not found]     ` <1462388788-2410-3-git-send-email-christophe-h.ricard-qxv4g6HH51o@public.gmane.org>
2016-05-09 13:23       ` Jarkko Sakkinen
     [not found]         ` <20160509132312.GA21366-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2016-05-13  8:34           ` Christophe Henri RICARD
2016-05-13 13:28             ` Jarkko Sakkinen
2016-05-04 19:06   ` [PATCH v7 3/7] tpm_tis: Introduce intermediate layer for TPM access Christophe Ricard
     [not found]     ` <1462388788-2410-4-git-send-email-christophe-h.ricard-qxv4g6HH51o@public.gmane.org>
2016-05-13 12:54       ` Jarkko Sakkinen
2016-05-04 19:06   ` [PATCH v7 4/7] devicetree: Add infineon to vendor-prefix.txt Christophe Ricard
2016-05-04 19:06   ` [PATCH v7 5/7] devicetree: Add Trusted Computing Group " Christophe Ricard
2016-05-04 19:06   ` [PATCH v7 6/7] tpm/tpm_tis: Split tpm_tis driver into a core and TCG TIS compliant phy Christophe Ricard
2016-05-04 19:06   ` [PATCH v7 7/7] tpm/tpm_tis_spi: Add support for spi phy Christophe Ricard
     [not found]     ` <1462388788-2410-8-git-send-email-christophe-h.ricard-qxv4g6HH51o@public.gmane.org>
2016-05-13 13:13       ` Jarkko Sakkinen [this message]

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