[PATCH 00/24] clk: Remove passing of negative errors through unsigned return

[PATCH 00/24] clk: Remove passing of negative errors through unsigned return

[Andrew Goodbody]

This series removes the passing of negative errors through the .get_rate
function in the clk_ops struct. This function returns an unsigned long.
The only value guaranteed to not be a valid clock rate is 0. This will
also bring the drivers more in sync with Linux to allow for easier code
porting and other maintenance in the future.
Another series will address the calling of clk_get_rate and associated
error handling.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
---
Andrew Goodbody (24):
      clk: meson: Remove negative error returns from clk_get_rate
      clk: sifive: Remove negative error returns from clk_get_rate
      clk: armada-37xx: Remove negative error returns from clk_get_rate
      clk: thead: th1520-ap: Remove negative error returns from clk_get_rate
      clk: ccf: Remove negative error returns from clk_get_rate
      clk: at91: Remove negative error returns from clk_get_rate
      clk: renesas: Remove negative error returns from clk_get_rate
      clk: rockchip: Remove negative error returns from clk_get_rate
      clk: Remove negative error returns from clk_get_rate
      clk: starfive: Remove negative error returns from clk_get_rate
      clk: altera: Remove negative error returns from clk_get_rate
      clk: uniphier: Remove negative error returns from clk_get_rate
      clk: aspeed: Remove negative error returns from clk_get_rate
      clk: nuvoton: Remove negative error returns from clk_get_rate
      clk: exynos: Remove negative error returns from clk_get_rate
      clk: imx: Remove negative error returns from clk_get_rate
      clk: ti: Remove negative error returns from clk_get_rate
      clk: mediatek: Remove negative error returns from clk_get_rate
      clk: owl: Remove negative error returns from clk_get_rate
      clk: tegra: Remove negative error returns from clk_get_rate
      clk: adi: Remove negative error returns from clk_get_rate
      clk: sophgo: Remove negative error returns from clk_get_rate
      clk: stm32: Remove negative error returns from clk_get_rate
      clk: x86: Remove negative error returns from clk_get_rate

 drivers/clk/adi/clk-shared.c             |  2 +-
 drivers/clk/altera/clk-agilex.c          |  2 +-
 drivers/clk/altera/clk-agilex5.c         |  2 +-
 drivers/clk/altera/clk-n5x.c             |  2 +-
 drivers/clk/aspeed/clk_ast2500.c         |  2 +-
 drivers/clk/aspeed/clk_ast2600.c         |  2 +-
 drivers/clk/at91/compat.c                |  6 ++--
 drivers/clk/clk-hsdk-cgu.c               |  2 +-
 drivers/clk/clk-uclass.c                 |  4 +--
 drivers/clk/clk.c                        |  2 +-
 drivers/clk/clk_fixed_factor.c           |  4 +--
 drivers/clk/clk_k210.c                   |  6 ++--
 drivers/clk/clk_sandbox.c                |  4 +--
 drivers/clk/clk_scmi.c                   |  4 +--
 drivers/clk/clk_vexpress_osc.c           |  2 +-
 drivers/clk/clk_zynq.c                   |  4 +--
 drivers/clk/clk_zynqmp.c                 | 40 ++++++++++-----------
 drivers/clk/exynos/clk-exynos7420.c      |  2 +-
 drivers/clk/imx/clk-imx8qm.c             |  6 ++--
 drivers/clk/imx/clk-imx8qxp.c            |  6 ++--
 drivers/clk/imx/clk-imxrt1170.c          |  2 +-
 drivers/clk/imx/clk-pllv3.c              |  2 +-
 drivers/clk/intel/clk_intel.c            |  2 +-
 drivers/clk/mediatek/clk-mtk.c           |  2 +-
 drivers/clk/meson/a1.c                   | 10 +++---
 drivers/clk/meson/axg.c                  | 10 +++---
 drivers/clk/meson/g12a.c                 | 36 +++++++++----------
 drivers/clk/meson/gxbb.c                 | 20 +++++------
 drivers/clk/mvebu/armada-37xx-periph.c   |  2 +-
 drivers/clk/mvebu/armada-37xx-tbg.c      |  2 +-
 drivers/clk/nuvoton/clk_npcm.c           | 10 +++---
 drivers/clk/owl/clk_owl.c                |  2 +-
 drivers/clk/renesas/clk-rcar-gen2.c      |  8 ++---
 drivers/clk/renesas/rzg2l-cpg.c          |  8 ++---
 drivers/clk/rockchip/clk_px30.c          | 24 ++++++-------
 drivers/clk/rockchip/clk_rk3036.c        |  2 +-
 drivers/clk/rockchip/clk_rk3066.c        |  8 ++---
 drivers/clk/rockchip/clk_rk3128.c        |  6 ++--
 drivers/clk/rockchip/clk_rk3188.c        |  6 ++--
 drivers/clk/rockchip/clk_rk322x.c        |  4 +--
 drivers/clk/rockchip/clk_rk3288.c        |  6 ++--
 drivers/clk/rockchip/clk_rk3308.c        | 26 +++++++-------
 drivers/clk/rockchip/clk_rk3328.c        |  6 ++--
 drivers/clk/rockchip/clk_rk3368.c        |  8 ++---
 drivers/clk/rockchip/clk_rk3399.c        | 12 +++----
 drivers/clk/rockchip/clk_rk3528.c        | 20 +++++------
 drivers/clk/rockchip/clk_rk3568.c        | 62 ++++++++++++++++----------------
 drivers/clk/rockchip/clk_rk3576.c        | 36 +++++++++----------
 drivers/clk/rockchip/clk_rk3588.c        | 32 ++++++++---------
 drivers/clk/rockchip/clk_rv1108.c        |  4 +--
 drivers/clk/rockchip/clk_rv1126.c        | 52 +++++++++++++--------------
 drivers/clk/sifive/sifive-prci.c         |  8 ++---
 drivers/clk/sophgo/clk-cv1800b.c         |  2 +-
 drivers/clk/starfive/clk-jh7110-pll.c    |  2 +-
 drivers/clk/stm32/clk-stm32-core.c       |  4 +--
 drivers/clk/stm32/clk-stm32f.c           |  6 ++--
 drivers/clk/stm32/clk-stm32h7.c          |  4 +--
 drivers/clk/tegra/tegra-car-clk.c        |  2 +-
 drivers/clk/tegra/tegra186-clk.c         |  2 +-
 drivers/clk/thead/clk-th1520-ap.c        |  2 +-
 drivers/clk/ti/clk-am3-dpll-x2.c         |  4 +--
 drivers/clk/ti/clk-divider.c             |  4 +--
 drivers/clk/ti/clk-mux.c                 |  2 +-
 drivers/clk/ti/clk-sci.c                 |  2 +-
 drivers/clk/uniphier/clk-uniphier-core.c |  2 +-
 65 files changed, 290 insertions(+), 290 deletions(-)
---
base-commit: ecdc3872a767fb045be3296d4317ae978a14b022
change-id: 20251010-clk_ops-3b7cc9ccd070

Best regards,
-- 
Andrew Goodbody <andrew.goodbody@linaro.org>

[PATCH 01/24] clk: meson: Remove negative error returns from clk_get_rate

[Andrew Goodbody]

clk_get_rate() returns a ulong so do not attempt to pass negative error
codes through it.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
---
 drivers/clk/meson/a1.c   | 10 +++++-----
 drivers/clk/meson/axg.c  | 10 +++++-----
 drivers/clk/meson/g12a.c | 36 ++++++++++++++++++------------------
 drivers/clk/meson/gxbb.c | 20 ++++++++++----------
 4 files changed, 38 insertions(+), 38 deletions(-)

diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c
index a1b8d79149102183402f470a60511d5300d0232c..78cad13239ca174a30f88cb2b18191cea74d6248 100644
--- a/drivers/clk/meson/a1.c
+++ b/drivers/clk/meson/a1.c
@@ -359,7 +359,7 @@ static ulong meson_div_get_rate(struct clk *clk, unsigned long id)
 
 	info = meson_clk_get_info(clk, id, MESON_CLK_DIV);
 	if (IS_ERR(info))
-		return PTR_ERR(info);
+		return 0;
 
 	/* Actual divider value is (field value + 1), hence the increment */
 	n = GET_PARM_VALUE(priv, info->parm) + 1;
@@ -402,7 +402,7 @@ static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
 
 	info = meson_clk_get_info(clk, id, MESON_CLK_ANY);
 	if (IS_ERR(info))
-		return PTR_ERR(info);
+		return 0;
 
 	pm = &info->parm[0];
 	pn = &info->parm[1];
@@ -411,7 +411,7 @@ static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
 	m = GET_PARM_VALUE(priv, pm);
 
 	if (n == 0)
-		return -EINVAL;
+		return 0;
 
 	parent = info->parents[0];
 	parent_rate_mhz = meson_clk_get_rate_by_id(clk, parent) / 1000000;
@@ -453,13 +453,13 @@ static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
 
 		ret = clk_get_by_name(clk->dev, info->name, &external_clk);
 		if (ret)
-			return ret;
+			return 0;
 
 		rate = clk_get_rate(&external_clk);
 		break;
 	}
 	default:
-		rate = -EINVAL;
+		rate = 0;
 		break;
 	}
 
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index c421a622a587d2eddef70d28b65e560722cf7f62..e0b41811b0dfcc59f9a57366639ff2133209b697 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -104,7 +104,7 @@ static unsigned long meson_clk81_get_rate(struct clk *clk)
 		parent_rate = XTAL_RATE;
 		break;
 	case 1:
-		return -ENOENT;
+		return 0;
 	default:
 		parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]);
 	}
@@ -123,7 +123,7 @@ static long mpll_rate_from_params(unsigned long parent_rate,
 	unsigned long divisor = (SDM_DEN * n2) + sdm;
 
 	if (n2 < N2_MIN)
-		return -EINVAL;
+		return 0;
 
 	return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
 }
@@ -171,7 +171,7 @@ static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
 		pn2 = &meson_mpll2_parm[1];
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL);
@@ -219,7 +219,7 @@ static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
 		pod = &meson_sys_pll_parm[2];
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	regmap_read(priv->map, pn->reg_off, &reg);
@@ -272,7 +272,7 @@ static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
 			rate = meson_clk81_get_rate(clk);
 			break;
 		}
-		return -ENOENT;
+		return 0;
 	}
 
 	debug("clock %lu has rate %lu\n", id, rate);
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index a7a42b2edb6a5b98612fb71fec6d17b1f3ab77c8..910b91e874bfdf6753ffc40bec7cd3a94e0b41ad 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -264,7 +264,7 @@ static ulong meson_div_get_rate(struct clk *clk, unsigned long id)
 		parent = meson_hdmi_div_parent;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	regmap_read(priv->map, parm->reg_off, &reg);
@@ -273,8 +273,8 @@ static ulong meson_div_get_rate(struct clk *clk, unsigned long id)
 	debug("%s: div of %ld is %d\n", __func__, id, reg + 1);
 
 	parent_rate = meson_clk_get_rate_by_id(clk, parent);
-	if (IS_ERR_VALUE(parent_rate))
-		return parent_rate;
+	if (!parent_rate)
+		return 0;
 
 	debug("%s: parent rate of %ld is %d\n", __func__, id, parent_rate);
 
@@ -323,12 +323,12 @@ static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
 		parent = meson_hdmi_div_parent;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	parent_rate = meson_clk_get_rate_by_id(clk, parent);
-	if (IS_ERR_VALUE(parent_rate))
-		return parent_rate;
+	if (!parent_rate)
+		return 0;
 
 	debug("%s: parent rate of %ld is %ld\n", __func__, id, parent_rate);
 
@@ -348,15 +348,15 @@ static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
 			return ret;
 
 		parent_rate = meson_clk_get_rate_by_id(clk, parent);
-		if (IS_ERR_VALUE(parent_rate))
-			return parent_rate;
+		if (!parent_rate)
+			return 0;
 
 		new_div = DIV_ROUND_CLOSEST(parent_rate, rate);
 
 		debug("%s: new new div of %ld is %d\n", __func__, id, new_div);
 
 		if (!new_div || new_div > (1 << parm->width))
-			return -EINVAL;
+			return 0;
 	}
 
 	debug("%s: setting div of %ld to %d\n", __func__, id, new_div);
@@ -471,7 +471,7 @@ static ulong meson_mux_get_parent(struct clk *clk, unsigned long id)
 		parents = meson_hdmi_mux_parents;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	regmap_read(priv->map, parm->reg_off, &reg);
@@ -560,8 +560,8 @@ static ulong meson_mux_get_rate(struct clk *clk, unsigned long id)
 {
 	int parent = meson_mux_get_parent(clk, id);
 
-	if (IS_ERR_VALUE(parent))
-		return parent;
+	if (!parent)
+		return 0;
 
 	return meson_clk_get_rate_by_id(clk, parent);
 }
@@ -588,7 +588,7 @@ static unsigned long meson_clk81_get_rate(struct clk *clk)
 
 	switch (reg) {
 	case 1:
-		return -ENOENT;
+		return 0;
 	default:
 		parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]);
 	}
@@ -655,12 +655,12 @@ static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
 		pn2 = &meson_mpll2_parm[1];
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL);
-	if (IS_ERR_VALUE(parent_rate))
-		return parent_rate;
+	if (!parent_rate)
+		return 0;
 
 	regmap_read(priv->map, psdm->reg_off, &reg);
 	sdm = PARM_GET(psdm->width, psdm->shift, reg);
@@ -711,7 +711,7 @@ static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
 		pod = &meson_sys_pll_parm[2];
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	regmap_read(priv->map, pn->reg_off, &reg);
@@ -851,7 +851,7 @@ static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
 			rate = meson_clk81_get_rate(clk);
 			break;
 		}
-		return -ENOENT;
+		return 0;
 	}
 
 	debug("clock %lu has rate %lu\n", id, rate);
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 51f124869c9c4043dfe047cf2f694bf59df7e87f..6dcfd084b8f93ade3fe1270db48f91f87cb61d26 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -306,7 +306,7 @@ static ulong meson_div_get_rate(struct clk *clk, unsigned long id)
 		parent = meson_hdmi_div_parent;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	regmap_read(priv->map, parm->reg_off, &reg);
@@ -315,8 +315,8 @@ static ulong meson_div_get_rate(struct clk *clk, unsigned long id)
 	debug("%s: div of %ld is %d\n", __func__, id, reg + 1);
 
 	parent_rate = meson_clk_get_rate_by_id(clk, parent);
-	if (IS_ERR_VALUE(parent_rate))
-		return parent_rate;
+	if (!parent_rate)
+		return 0;
 
 	debug("%s: parent rate of %ld is %d\n", __func__, id, parent_rate);
 
@@ -596,8 +596,8 @@ static ulong meson_mux_get_rate(struct clk *clk, unsigned long id)
 {
 	int parent = meson_mux_get_parent(clk, id);
 
-	if (IS_ERR_VALUE(parent))
-		return parent;
+	if (parent < 0)
+		return 0;
 
 	return meson_clk_get_rate_by_id(clk, parent);
 }
@@ -627,7 +627,7 @@ static unsigned long meson_clk81_get_rate(struct clk *clk)
 		parent_rate = XTAL_RATE;
 		break;
 	case 1:
-		return -ENOENT;
+		return 0;
 	default:
 		parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]);
 	}
@@ -695,12 +695,12 @@ static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
 		pn2 = &meson_mpll2_parm[1];
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL);
-	if (IS_ERR_VALUE(parent_rate))
-		return parent_rate;
+	if (!parent_rate)
+		return 0;
 
 	regmap_read(priv->map, psdm->reg_off, &reg);
 	sdm = PARM_GET(psdm->width, psdm->shift, reg);
@@ -833,7 +833,7 @@ static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
 			rate = meson_clk81_get_rate(clk);
 			break;
 		}
-		return -ENOENT;
+		return 0;
 	}
 
 	debug("clock %lu has rate %lu\n", id, rate);

-- 
2.47.3

[PATCH 02/24] clk: sifive: Remove negative error returns from clk_get_rate

[Andrew Goodbody]

clk_get_rate() returns a ulong so do not attempt to pass negative error
codes through it.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
---
 drivers/clk/sifive/sifive-prci.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c
index de55504b5c90785f8d5f1f66eb914847feb4a495..01fcc85ab23ff56886638cc0581b5389012de154 100644
--- a/drivers/clk/sifive/sifive-prci.c
+++ b/drivers/clk/sifive/sifive-prci.c
@@ -548,11 +548,11 @@ static ulong sifive_prci_parent_rate(struct __prci_clock *pc, struct prci_clk_de
 		}
 
 		if (i >= data->num_clks)
-			return -ENXIO;
+			return 0;
 
 		p = &data->clks[i];
 		if (!p->pd || !p->ops->recalc_rate)
-			return -ENXIO;
+			return 0;
 
 		return p->ops->recalc_rate(p, sifive_prci_parent_rate(p, data));
 	}
@@ -572,11 +572,11 @@ static ulong sifive_prci_get_rate(struct clk *clk)
 		(struct prci_clk_desc *)dev_get_driver_data(clk->dev);
 
 	if (data->num_clks <= clk->id)
-		return -ENXIO;
+		return 0;
 
 	pc = &data->clks[clk->id];
 	if (!pc->pd || !pc->ops->recalc_rate)
-		return -ENXIO;
+		return 0;
 
 	return pc->ops->recalc_rate(pc, sifive_prci_parent_rate(pc, data));
 }

-- 
2.47.3

[PATCH 03/24] clk: armada-37xx: Remove negative error returns from clk_get_rate

[Andrew Goodbody]

clk_get_rate() returns a ulong so do not attempt to pass negative error
codes through it.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
---
 drivers/clk/mvebu/armada-37xx-periph.c | 2 +-
 drivers/clk/mvebu/armada-37xx-tbg.c    | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c
index 30330393f760fe34b3c78f23b617309b18903477..938881056d373e9978ff34376edc76527ebe4c0f 100644
--- a/drivers/clk/mvebu/armada-37xx-periph.c
+++ b/drivers/clk/mvebu/armada-37xx-periph.c
@@ -325,7 +325,7 @@ static ulong armada_37xx_periph_clk_get_rate(struct clk *clk)
 	struct a37xx_periphclk *priv = dev_get_priv(clk->dev);
 
 	if (clk->id >= priv->count)
-		return -EINVAL;
+		return 0;
 
 	return periph_clk_get_rate(priv, clk->id);
 }
diff --git a/drivers/clk/mvebu/armada-37xx-tbg.c b/drivers/clk/mvebu/armada-37xx-tbg.c
index c1bab84c070e35f3ce739cfce2e1468157ebe71b..d61b1d34fc64cfff473ead2bf8b0e929d4957994 100644
--- a/drivers/clk/mvebu/armada-37xx-tbg.c
+++ b/drivers/clk/mvebu/armada-37xx-tbg.c
@@ -88,7 +88,7 @@ static ulong armada_37xx_tbg_clk_get_rate(struct clk *clk)
 	struct a37xx_tbgclk *priv = dev_get_priv(clk->dev);
 
 	if (clk->id >= NUM_TBG)
-		return -ENODEV;
+		return 0;
 
 	return priv->rates[clk->id];
 }

-- 
2.47.3

[PATCH 04/24] clk: thead: th1520-ap: Remove negative error returns from clk_get_rate

[Andrew Goodbody]

clk_get_rate() returns a ulong so do not attempt to pass negative error
codes through it.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
---
 drivers/clk/thead/clk-th1520-ap.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c
index 6899e1b595a7148a118d3a615d5dfea4b4fb5b96..e913621967eb131b534e8f5b928687967a02a30e 100644
--- a/drivers/clk/thead/clk-th1520-ap.c
+++ b/drivers/clk/thead/clk-th1520-ap.c
@@ -985,7 +985,7 @@ static ulong th1520_clk_get_rate(struct clk *clk)
 
 	ret = clk_get_by_id(clk->id, &c);
 	if (ret)
-		return ret;
+		return 0;
 
 	return clk_get_rate(c);
 }

-- 
2.47.3

[PATCH 05/24] clk: ccf: Remove negative error returns from clk_get_rate

[Andrew Goodbody]

clk_get_rate() returns a ulong so do not attempt to pass negative error
codes through it.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
---
 drivers/clk/clk.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index b8c2e8d531b91f986995d15669620feff936e617..eb3b58edd2669cdff0f72ee9daad083d063c4dd8 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -84,7 +84,7 @@ ulong ccf_clk_get_rate(struct clk *clk)
 	int err = clk_get_by_id(clk->id, &c);
 
 	if (err)
-		return err;
+		return 0;
 	return clk_get_rate(c);
 }
 

-- 
2.47.3

[PATCH 06/24] clk: at91: Remove negative error returns from clk_get_rate

[Andrew Goodbody]

clk_get_rate() returns a ulong so do not attempt to pass negative error
codes through it.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
---
 drivers/clk/at91/compat.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/at91/compat.c b/drivers/clk/at91/compat.c
index 1d738f160b6e0881ac6ca6730e54f016e9899b27..ffc3168400b276a57f7dbe6f80f813571118cead 100644
--- a/drivers/clk/at91/compat.c
+++ b/drivers/clk/at91/compat.c
@@ -291,7 +291,7 @@ static ulong at91_plladiv_clk_get_rate(struct clk *clk)
 
 	ret = clk_get_by_index(clk->dev, 0, &source);
 	if (ret)
-		return -EINVAL;
+		return 0;
 
 	clk_rate = clk_get_rate(&source);
 	if (readl(&pmc->mckr) & AT91_PMC_MCKR_PLLADIV_2)
@@ -387,7 +387,7 @@ static ulong system_clk_get_rate(struct clk *clk)
 
 	ret = clk_get_by_index(clk->dev, 0, &clk_dev);
 	if (ret)
-		return -EINVAL;
+		return 0;
 
 	return clk_get_rate(&clk_dev);
 }
@@ -522,7 +522,7 @@ static ulong periph_get_rate(struct clk *clk)
 
 	ret = clk_get_by_index(dev, 0, &clk_dev);
 	if (ret)
-		return ret;
+		return 0;
 
 	return clk_get_rate(&clk_dev);
 }

-- 
2.47.3

[PATCH 07/24] clk: renesas: Remove negative error returns from clk_get_rate

[Andrew Goodbody]

clk_get_rate() returns a ulong so do not attempt to pass negative error
codes through it.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
---
 drivers/clk/renesas/clk-rcar-gen2.c | 8 ++++----
 drivers/clk/renesas/rzg2l-cpg.c     | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c
index 9b6fce4675c018ad72eeefe3939bacbf65ffc428..4cdcc0fe71946d3055caae3ac7eb8e36c0b9b507 100644
--- a/drivers/clk/renesas/clk-rcar-gen2.c
+++ b/drivers/clk/renesas/clk-rcar-gen2.c
@@ -82,7 +82,7 @@ static ulong gen2_clk_get_rate(struct clk *clk)
 	ret = renesas_clk_get_parent(clk, info, &parent);
 	if (ret) {
 		printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
-		return ret;
+		return 0;
 	}
 
 	if (renesas_clk_is_mod(clk)) {
@@ -94,7 +94,7 @@ static ulong gen2_clk_get_rate(struct clk *clk)
 
 	ret = renesas_clk_get_core(clk, info, &core);
 	if (ret)
-		return ret;
+		return 0;
 
 	switch (core->type) {
 	case CLK_TYPE_IN:
@@ -112,7 +112,7 @@ static ulong gen2_clk_get_rate(struct clk *clk)
 			return rate;
 		}
 
-		return -EINVAL;
+		return 0;
 
 	case CLK_TYPE_FF:
 		rate = (gen2_clk_get_rate(&parent) * core->mult) / core->div;
@@ -198,7 +198,7 @@ static ulong gen2_clk_get_rate(struct clk *clk)
 
 	printf("%s[%i] unknown fail\n", __func__, __LINE__);
 
-	return -ENOENT;
+	return 0;
 }
 
 static int gen2_clk_setup_mmcif_div(struct clk *clk, ulong rate)
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 7fce1f70d13805fff452b60ce6ec16e4439e28d0..ecdd6c6e52695658d032b805425480cf60a1be59 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -225,7 +225,7 @@ static ulong rzg2l_core_clk_get_rate(struct udevice *dev, const struct cpg_core_
 		return rzg2l_div_clk_get_rate(dev, cc);
 	default:
 		dev_err(dev, "get_rate needed for clock %u, type %d\n", cc->id, cc->type);
-		return -ENOSYS;
+		return 0;
 	}
 }
 
@@ -244,7 +244,7 @@ static ulong rzg2l_cpg_clk_get_rate_by_id(struct udevice *dev, unsigned int id)
 		}
 
 		dev_err(dev, "Module clock ID %u not found\n", cpg_clk_id);
-		return -ENODEV;
+		return 0;
 	}
 
 	for (i = 0; i < data->info->num_core_clks; i++) {
@@ -253,7 +253,7 @@ static ulong rzg2l_cpg_clk_get_rate_by_id(struct udevice *dev, unsigned int id)
 	}
 
 	dev_err(dev, "Core clock ID %u not found\n", cpg_clk_id);
-	return -ENODEV;
+	return 0;
 }
 
 static ulong rzg2l_cpg_clk_get_rate_by_name(struct udevice *dev, const char *name)
@@ -272,7 +272,7 @@ static ulong rzg2l_cpg_clk_get_rate_by_name(struct udevice *dev, const char *nam
 	}
 
 	dev_err(dev, "Clock name %s not found\n", name);
-	return -EINVAL;
+	return 0;
 }
 
 static ulong rzg2l_cpg_clk_get_rate(struct clk *clk)

-- 
2.47.3

[PATCH 08/24] clk: rockchip: Remove negative error returns from clk_get_rate

[Andrew Goodbody]

clk_get_rate() returns a ulong so do not attempt to pass negative error
codes through it.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
---
 drivers/clk/rockchip/clk_px30.c   | 24 +++++++--------
 drivers/clk/rockchip/clk_rk3036.c |  2 +-
 drivers/clk/rockchip/clk_rk3066.c |  8 ++---
 drivers/clk/rockchip/clk_rk3128.c |  6 ++--
 drivers/clk/rockchip/clk_rk3188.c |  6 ++--
 drivers/clk/rockchip/clk_rk322x.c |  4 +--
 drivers/clk/rockchip/clk_rk3288.c |  6 ++--
 drivers/clk/rockchip/clk_rk3308.c | 26 ++++++++--------
 drivers/clk/rockchip/clk_rk3328.c |  6 ++--
 drivers/clk/rockchip/clk_rk3368.c |  8 ++---
 drivers/clk/rockchip/clk_rk3399.c | 12 ++++----
 drivers/clk/rockchip/clk_rk3528.c | 20 ++++++-------
 drivers/clk/rockchip/clk_rk3568.c | 62 +++++++++++++++++++--------------------
 drivers/clk/rockchip/clk_rk3576.c | 36 +++++++++++------------
 drivers/clk/rockchip/clk_rk3588.c | 32 ++++++++++----------
 drivers/clk/rockchip/clk_rv1108.c |  4 +--
 drivers/clk/rockchip/clk_rv1126.c | 52 ++++++++++++++++----------------
 17 files changed, 157 insertions(+), 157 deletions(-)

diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c
index ad7e1c0f2460e3deb5bf24ff6e80ef8c6e80139c..e289cd60775f6e771e9afaabf70feb81bc904f08 100644
--- a/drivers/clk/rockchip/clk_px30.c
+++ b/drivers/clk/rockchip/clk_px30.c
@@ -308,7 +308,7 @@ static ulong px30_i2c_get_clk(struct px30_clk_priv *priv, ulong clk_id)
 		break;
 	default:
 		printf("do not support this i2c bus\n");
-		return -EINVAL;
+		return 0;
 	}
 
 	return DIV_TO_RATE(priv->gpll_hz, div);
@@ -436,7 +436,7 @@ static ulong px30_i2s_get_clk(struct px30_clk_priv *priv, ulong clk_id)
 		break;
 	default:
 		printf("do not support this i2s bus\n");
-		return -EINVAL;
+		return 0;
 	}
 
 	return clk_src * n / m;
@@ -523,7 +523,7 @@ static ulong px30_mmc_get_clk(struct px30_clk_priv *priv, uint clk_id)
 		con_id = 20;
 		break;
 	default:
-		return -EINVAL;
+		return 0;
 	}
 
 	con = readl(&cru->clksel_con[con_id]);
@@ -621,7 +621,7 @@ static ulong px30_pwm_get_clk(struct px30_clk_priv *priv, ulong clk_id)
 		break;
 	default:
 		printf("do not support this pwm bus\n");
-		return -EINVAL;
+		return 0;
 	}
 
 	return DIV_TO_RATE(priv->gpll_hz, div);
@@ -726,7 +726,7 @@ static ulong px30_spi_get_clk(struct px30_clk_priv *priv, ulong clk_id)
 		break;
 	default:
 		printf("do not support this pwm bus\n");
-		return -EINVAL;
+		return 0;
 	}
 
 	return DIV_TO_RATE(priv->gpll_hz, div);
@@ -786,7 +786,7 @@ static ulong px30_vop_get_clk(struct px30_clk_priv *priv, ulong clk_id)
 		parent = rkclk_pll_get_rate(&cru->pll[NPLL], &cru->mode, NPLL);
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return DIV_TO_RATE(parent, div);
@@ -883,7 +883,7 @@ static ulong px30_bus_get_clk(struct px30_clk_priv *priv, ulong clk_id)
 		div = (con & BUS_PCLK_DIV_MASK) >> BUS_PCLK_DIV_SHIFT;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return DIV_TO_RATE(parent, div);
@@ -949,7 +949,7 @@ static ulong px30_peri_get_clk(struct px30_clk_priv *priv, ulong clk_id)
 		parent = priv->gpll_hz;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return DIV_TO_RATE(parent, div);
@@ -1007,7 +1007,7 @@ static ulong px30_crypto_get_clk(struct px30_clk_priv *priv, ulong clk_id)
 		parent = priv->gpll_hz;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return DIV_TO_RATE(parent, div);
@@ -1189,7 +1189,7 @@ static ulong px30_clk_get_rate(struct clk *clk)
 
 	if (!priv->gpll_hz && clk->id > ARMCLK) {
 		printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
-		return -ENOENT;
+		return 0;
 	}
 
 	debug("%s %ld\n", __func__, clk->id);
@@ -1268,7 +1268,7 @@ static ulong px30_clk_get_rate(struct clk *clk)
 		break;
 #endif
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return rate;
@@ -1704,7 +1704,7 @@ static ulong px30_pmuclk_get_rate(struct clk *clk)
 		rate = px30_pmu_uart0_get_clk(priv);
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return rate;
diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c
index 274428f2b4bd5e0b52818b4dca898acb45b68055..f41f8dff789fcddd097924cdfa2e00541f8a764d 100644
--- a/drivers/clk/rockchip/clk_rk3036.c
+++ b/drivers/clk/rockchip/clk_rk3036.c
@@ -287,7 +287,7 @@ static ulong rk3036_clk_get_rate(struct clk *clk)
 	case 0 ... 63:
 		return rkclk_pll_get_rate(priv->cru, clk->id);
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
diff --git a/drivers/clk/rockchip/clk_rk3066.c b/drivers/clk/rockchip/clk_rk3066.c
index f7dea7859f7444de8f4531044b4ea521d56c1826..b2d61532af30ab15c386f502902bd7049c19ba8b 100644
--- a/drivers/clk/rockchip/clk_rk3066.c
+++ b/drivers/clk/rockchip/clk_rk3066.c
@@ -272,7 +272,7 @@ static ulong rk3066_clk_mmc_get_clk(struct rk3066_cru *cru, uint gclk_rate,
 		div = bitfield_extract_by_mask(con, SDIO_DIV_MASK);
 		break;
 	default:
-		return -EINVAL;
+		return 0;
 	}
 
 	return DIV_TO_RATE(gclk_rate, div) / 2;
@@ -330,7 +330,7 @@ static ulong rk3066_clk_spi_get_clk(struct rk3066_cru *cru, uint gclk_rate,
 		div = bitfield_extract_by_mask(con, SPI1_DIV_MASK);
 		break;
 	default:
-		return -EINVAL;
+		return 0;
 	}
 
 	return DIV_TO_RATE(gclk_rate, div);
@@ -376,7 +376,7 @@ static ulong rk3066_clk_saradc_get_clk(struct rk3066_cru *cru, int periph)
 		div = bitfield_extract_by_mask(con, TSADC_DIV_MASK);
 		break;
 	default:
-		return -EINVAL;
+		return 0;
 	}
 	return DIV_TO_RATE(PERI_PCLK_HZ, div);
 }
@@ -534,7 +534,7 @@ static ulong rk3066_clk_get_rate(struct clk *clk)
 	case SCLK_UART3:
 		return OSC_HZ;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return new_rate;
diff --git a/drivers/clk/rockchip/clk_rk3128.c b/drivers/clk/rockchip/clk_rk3128.c
index a07285593b554b8855048e25e4b9a52ad55a9dde..d149fe66eea878d80fcfe40356d57f4d39004229 100644
--- a/drivers/clk/rockchip/clk_rk3128.c
+++ b/drivers/clk/rockchip/clk_rk3128.c
@@ -360,7 +360,7 @@ static ulong rk3128_peri_get_pclk(struct rk3128_cru *cru, ulong clk_id)
 		break;
 	default:
 		printf("do not support this peripheral bus\n");
-		return -EINVAL;
+		return 0;
 	}
 
 	return DIV_TO_RATE(PERI_ACLK_HZ, div);
@@ -475,7 +475,7 @@ static ulong rk3128_vop_get_rate(struct rk3128_cru *cru, ulong clk_id)
 		parent = rkclk_pll_get_rate(cru, CLK_CODEC);
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 	return DIV_TO_RATE(parent, div);
 }
@@ -500,7 +500,7 @@ static ulong rk3128_clk_get_rate(struct clk *clk)
 	case ACLK_VIO1:
 		return rk3128_vop_get_rate(priv->cru, clk->id);
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c
index d8b03e1d7ab3d9636467fe235a5b432418b9c382..c54a0af788bf0c03693b1ff2edf6170cdfd5a282 100644
--- a/drivers/clk/rockchip/clk_rk3188.c
+++ b/drivers/clk/rockchip/clk_rk3188.c
@@ -281,7 +281,7 @@ static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate,
 		div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK;
 		break;
 	default:
-		return -EINVAL;
+		return 0;
 	}
 
 	return DIV_TO_RATE(gclk_rate, div) / 2;
@@ -339,7 +339,7 @@ static ulong rockchip_spi_get_clk(struct rk3188_cru *cru, uint gclk_rate,
 		div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
 		break;
 	default:
-		return -EINVAL;
+		return 0;
 	}
 
 	return DIV_TO_RATE(gclk_rate, div);
@@ -489,7 +489,7 @@ static ulong rk3188_clk_get_rate(struct clk *clk)
 	case PCLK_I2C4:
 		return gclk_rate;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return new_rate;
diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c
index 9b71fd863bad48832d0f0915e30d627102710fc0..fdb7ab0ec9612a7b5a6cf2d5531e9076e97e7202 100644
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -234,7 +234,7 @@ static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
 		div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
 		break;
 	default:
-		return -EINVAL;
+		return 0;
 	}
 
 	src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
@@ -367,7 +367,7 @@ static ulong rk322x_clk_get_rate(struct clk *clk)
 		rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return rate;
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index a4ff1c41abb8c1ff563dad4c042d240dd05b9186..bd1e778dc3603e5bd4444cb100cf36d78191ea14 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -599,7 +599,7 @@ static ulong rockchip_mmc_get_clk(struct rockchip_cru *cru, uint gclk_rate,
 		div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT;
 		break;
 	default:
-		return -EINVAL;
+		return 0;
 	}
 
 	src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
@@ -679,7 +679,7 @@ static ulong rockchip_spi_get_clk(struct rockchip_cru *cru, uint gclk_rate,
 		div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT;
 		break;
 	default:
-		return -EINVAL;
+		return 0;
 	}
 	assert(mux == SPI0_PLL_SELECT_GENERAL);
 
@@ -782,7 +782,7 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
 		new_rate = rockchip_saradc_get_clk(priv->cru);
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return new_rate;
diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c
index e73bb6790af262c81a2ae11d94d700ec307d8861..1d0293bbf32e00e155771a61bc30ffa8cc4636b5 100644
--- a/drivers/clk/rockchip/clk_rk3308.c
+++ b/drivers/clk/rockchip/clk_rk3308.c
@@ -195,7 +195,7 @@ static ulong rk3308_i2c_get_clk(struct clk *clk)
 		break;
 	default:
 		printf("do not support this i2c bus\n");
-		return -EINVAL;
+		return 0;
 	}
 
 	con = readl(&cru->clksel_con[con_id]);
@@ -301,7 +301,7 @@ static ulong rk3308_mmc_get_clk(struct clk *clk)
 		con_id = 41;
 		break;
 	default:
-		return -EINVAL;
+		return 0;
 	}
 
 	con = readl(&cru->clksel_con[con_id]);
@@ -430,7 +430,7 @@ static ulong rk3308_spi_get_clk(struct clk *clk)
 		break;
 	default:
 		printf("do not support this spi bus\n");
-		return -EINVAL;
+		return 0;
 	}
 
 	con = readl(&cru->clksel_con[con_id]);
@@ -524,7 +524,7 @@ static ulong rk3308_uart_get_clk(struct clk *clk)
 		break;
 	default:
 		printf("do not support this uart interface\n");
-		return -EINVAL;
+		return 0;
 	}
 
 	con = readl(&cru->clksel_con[con_id]);
@@ -546,7 +546,7 @@ static ulong rk3308_uart_get_clk(struct clk *clk)
 		break;
 	default:
 		printf("do not support this uart pll sel\n");
-		return -EINVAL;
+		return 0;
 	}
 
 	return DIV_TO_RATE(parent, div);
@@ -578,11 +578,11 @@ static ulong rk3308_vop_get_clk(struct clk *clk)
 			break;
 		default:
 			printf("do not support this vop pll sel\n");
-			return -EINVAL;
+			return 0;
 		}
 	} else {
 		printf("do not support this vop sel\n");
-		return -EINVAL;
+		return 0;
 	}
 
 	return DIV_TO_RATE(parent, div);
@@ -663,7 +663,7 @@ static ulong rk3308_bus_get_clk(struct rk3308_clk_priv *priv, ulong clk_id)
 		div = (con & BUS_PCLK_DIV_MASK) >> BUS_PCLK_DIV_SHIFT;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return DIV_TO_RATE(parent, div);
@@ -726,7 +726,7 @@ static ulong rk3308_peri_get_clk(struct rk3308_clk_priv *priv, ulong clk_id)
 		div = (con & PERI_PCLK_DIV_MASK) >> PERI_PCLK_DIV_SHIFT;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return DIV_TO_RATE(parent, div);
@@ -785,7 +785,7 @@ static ulong rk3308_audio_get_clk(struct rk3308_clk_priv *priv, ulong clk_id)
 		div = (con & AUDIO_PCLK_DIV_MASK) >> AUDIO_PCLK_DIV_SHIFT;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return DIV_TO_RATE(parent, div);
@@ -842,7 +842,7 @@ static ulong rk3308_crypto_get_clk(struct rk3308_clk_priv *priv, ulong clk_id)
 		parent = priv->vpll0_hz;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return DIV_TO_RATE(parent, div);
@@ -891,7 +891,7 @@ static ulong rk3308_rtc32k_get_clk(struct rk3308_clk_priv *priv, ulong clk_id)
 	con = readl(&cru->clksel_con[2]);
 	if ((con & CLK_RTC32K_SEL_MASK) >> CLK_RTC32K_SEL_SHIFT !=
 	    CLK_RTC32K_FRAC_DIV)
-		return -EINVAL;
+		return 0;
 
 	fracdiv = readl(&cru->clksel_con[3]);
 	m = fracdiv & CLK_RTC32K_FRAC_NUMERATOR_MASK;
@@ -1004,7 +1004,7 @@ static ulong rk3308_clk_get_rate(struct clk *clk)
 		rate = rk3308_rtc32k_get_clk(priv, clk->id);
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return rate;
diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
index 7701a9734ee07ec0e89a1f780b21f3305527f7fc..eed871ea65ce3f3fc92b2b312bd260d686f590a5 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -357,7 +357,7 @@ static ulong rk3328_i2c_get_clk(struct rk3328_cru *cru, ulong clk_id)
 		break;
 	default:
 		printf("do not support this i2c bus\n");
-		return -EINVAL;
+		return 0;
 	}
 
 	return DIV_TO_RATE(GPLL_HZ, div);
@@ -459,7 +459,7 @@ static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
 		con_id = 32;
 		break;
 	default:
-		return -EINVAL;
+		return 0;
 	}
 	con = readl(&cru->clksel_con[con_id]);
 	div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
@@ -708,7 +708,7 @@ static ulong rk3328_clk_get_rate(struct clk *clk)
 		rate = OSC_HZ;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return rate;
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index 630253fbb1df5f9e43e2b00b72fdf812eae8bbb7..87447ea2ff7d97aa64980d4a0457e91fb8ba70d8 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -174,7 +174,7 @@ static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
 		con_id = 48;
 		break;
 	default:
-		return -EINVAL;
+		return 0;
 	}
 
 	con = readl(&cru->clksel_con[con_id]);
@@ -190,7 +190,7 @@ static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
 		break;
 	case MMC_PLL_SEL_USBPHY_480M:
 	default:
-		return -EINVAL;
+		return 0;
 	}
 	div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT;
 	rate = DIV_TO_RATE(pll_rate, div);
@@ -391,7 +391,7 @@ static ulong rk3368_spi_get_clk(struct rk3368_cru *cru, ulong clk_id)
 
 	default:
 		pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
-		return -EINVAL;
+		return 0;
 	}
 
 	val = readl(&cru->clksel_con[spiclk->reg]);
@@ -479,7 +479,7 @@ static ulong rk3368_clk_get_rate(struct clk *clk)
 		rate = rk3368_saradc_get_clk(priv->cru);
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return rate;
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 6e87db18be075d519d097d31a51a3398d389d45d..0f32c9c8f078aee29e094d127f13d2a60f811cb7 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -546,7 +546,7 @@ static ulong rk3399_i2c_get_clk(struct rockchip_cru *cru, ulong clk_id)
 		break;
 	default:
 		printf("do not support this i2c bus\n");
-		return -EINVAL;
+		return 0;
 	}
 
 	return DIV_TO_RATE(GPLL_HZ, div);
@@ -641,7 +641,7 @@ static ulong rk3399_spi_get_clk(struct rockchip_cru *cru, ulong clk_id)
 
 	default:
 		pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
-		return -EINVAL;
+		return 0;
 	}
 
 	val = readl(&cru->clksel_con[spiclk->reg]);
@@ -744,7 +744,7 @@ static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id)
 		div = 1;
 		break;
 	default:
-		return -EINVAL;
+		return 0;
 	}
 
 	div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
@@ -1003,7 +1003,7 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
 		break;
 	default:
 		log_debug("Unknown clock %lu\n", clk->id);
-		return -ENOENT;
+		return 0;
 	}
 
 	return rate;
@@ -1557,7 +1557,7 @@ static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id)
 		break;
 	default:
 		printf("do not support this i2c bus\n");
-		return -EINVAL;
+		return 0;
 	}
 
 	return DIV_TO_RATE(PPLL_HZ, div);
@@ -1621,7 +1621,7 @@ static ulong rk3399_pmuclk_get_rate(struct clk *clk)
 		rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id);
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return rate;
diff --git a/drivers/clk/rockchip/clk_rk3528.c b/drivers/clk/rockchip/clk_rk3528.c
index d58557ff56de1b5e69cf0f51aa6ac9ab99bafd5f..fe5cdb18f645acdf93826f76cdf74d4fdf375295 100644
--- a/drivers/clk/rockchip/clk_rk3528.c
+++ b/drivers/clk/rockchip/clk_rk3528.c
@@ -239,7 +239,7 @@ static ulong rk3528_ppll_matrix_get_rate(struct rk3528_clk_priv *priv,
 		reg = &cru->clksel_con[60];
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	div = (readl(reg) & mask) >> shift;
@@ -378,7 +378,7 @@ static ulong rk3528_cgpll_matrix_get_rate(struct rk3528_clk_priv *priv,
 		break;
 
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	if (sel_mask) {
@@ -575,7 +575,7 @@ static ulong rk3528_i2c_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
 		break;
 
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	if (is_pmucru)
@@ -692,7 +692,7 @@ static ulong rk3528_spi_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
 		shift = CLK_SPI1_SEL_SHIFT;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	con = readl(&cru->clksel_con[id]);
@@ -765,7 +765,7 @@ static ulong rk3528_pwm_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
 		break;
 
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	con = readl(&cru->clksel_con[id]);
@@ -838,7 +838,7 @@ static ulong rk3528_adc_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
 		break;
 
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return DIV_TO_RATE(OSC_HZ, div);
@@ -1045,7 +1045,7 @@ static ulong rk3528_dclk_vop_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
 		break;
 
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	con = readl(&cru->clksel_con[id]);
@@ -1177,7 +1177,7 @@ static ulong rk3528_uart_get_rate(struct rk3528_clk_priv *priv, ulong clk_id)
 		break;
 
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	con = readl(&cru->clksel_con[id - 2]);
@@ -1310,7 +1310,7 @@ static ulong rk3528_clk_get_rate(struct clk *clk)
 	if (!priv->gpll_hz || !priv->cpll_hz) {
 		printf("%s: gpll=%lu, cpll=%ld\n",
 		       __func__, priv->gpll_hz, priv->cpll_hz);
-		return -ENOENT;
+		return 0;
 	}
 
 	switch (clk->id) {
@@ -1416,7 +1416,7 @@ static ulong rk3528_clk_get_rate(struct clk *clk)
 		rate = rk3528_ppll_matrix_get_rate(priv, clk->id);
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return rate;
diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c
index 533031caead6818fe41774c9efee969fdd428dbc..93b9af79d0a47f4d87e801ea2105505389d9ec5d 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -233,7 +233,7 @@ static ulong rk3568_i2c_get_pmuclk(struct rk3568_pmuclk_priv *priv,
 		div = (con & CLK_I2C0_DIV_MASK) >> CLK_I2C0_DIV_SHIFT;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return DIV_TO_RATE(priv->ppll_hz, div);
@@ -277,7 +277,7 @@ static ulong rk3568_pwm_get_pmuclk(struct rk3568_pmuclk_priv *priv,
 			parent = priv->ppll_hz;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return DIV_TO_RATE(parent, div);
@@ -353,7 +353,7 @@ static ulong rk3568_pmuclk_get_rate(struct clk *clk)
 
 	if (!priv->ppll_hz) {
 		printf("%s ppll=%lu\n", __func__, priv->ppll_hz);
-		return -ENOENT;
+		return 0;
 	}
 
 	debug("%s %ld\n", __func__, clk->id);
@@ -380,7 +380,7 @@ static ulong rk3568_pmuclk_get_rate(struct clk *clk)
 		rate = rk3568_pmu_get_pmuclk(priv);
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return rate;
@@ -641,7 +641,7 @@ static ulong rk3568_cpll_div_get_rate(struct rk3568_clk_priv *priv,
 		shift = CPLL_25M_DIV_SHIFT;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	div = (readl(&cru->clksel_con[con]) & mask) >> shift;
@@ -741,7 +741,7 @@ static ulong rk3568_bus_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
 			rate = OSC_HZ;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return rate;
@@ -821,7 +821,7 @@ static ulong rk3568_perimid_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
 			rate = OSC_HZ;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return rate;
@@ -924,7 +924,7 @@ static ulong rk3568_top_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
 			rate = OSC_HZ;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return rate;
@@ -1022,7 +1022,7 @@ static ulong rk3568_i2c_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
 			rate = OSC_HZ;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return rate;
@@ -1078,7 +1078,7 @@ static ulong rk3568_spi_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
 		sel = (con & CLK_SPI3_SEL_MASK) >> CLK_SPI3_SEL_SHIFT;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	switch (sel) {
@@ -1089,7 +1089,7 @@ static ulong rk3568_spi_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
 	case CLK_SPI_SEL_CPLL_100M:
 		return 100 * MHz;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -1152,7 +1152,7 @@ static ulong rk3568_pwm_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
 		sel = (con & CLK_PWM3_SEL_MASK) >> CLK_PWM3_SEL_SHIFT;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	switch (sel) {
@@ -1163,7 +1163,7 @@ static ulong rk3568_pwm_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
 	case CLK_PWM_SEL_CPLL_100M:
 		return 100 * MHz;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -1226,7 +1226,7 @@ static ulong rk3568_adc_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
 		prate = rk3568_adc_get_clk(priv, CLK_TSADC_TSEN);
 		return DIV_TO_RATE(prate, div);
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -1331,7 +1331,7 @@ static ulong rk3568_crypto_get_rate(struct rk3568_clk_priv *priv, ulong clk_id)
 		else
 			return 100 * MHz;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -1418,7 +1418,7 @@ static ulong rk3568_sdmmc_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
 		sel = (con & CLK_SDMMC2_SEL_MASK) >> CLK_SDMMC2_SEL_SHIFT;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	switch (sel) {
@@ -1435,7 +1435,7 @@ static ulong rk3568_sdmmc_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
 	case CLK_SDMMC_SEL_750K:
 		return 750 * KHz;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -1517,7 +1517,7 @@ static ulong rk3568_sfc_get_clk(struct rk3568_clk_priv *priv)
 	case SCLK_SFC_SEL_150M:
 		return 150 * MHz;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -1565,7 +1565,7 @@ static ulong rk3568_nand_get_clk(struct rk3568_clk_priv *priv)
 	case NCLK_NANDC_SEL_24M:
 		return OSC_HZ;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -1619,7 +1619,7 @@ static ulong rk3568_emmc_get_clk(struct rk3568_clk_priv *priv)
 	case CCLK_EMMC_SEL_24M:
 		return OSC_HZ;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -1677,7 +1677,7 @@ static ulong rk3568_emmc_get_bclk(struct rk3568_clk_priv *priv)
 	case BCLK_EMMC_SEL_125M:
 		return 125 * MHz;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -1765,7 +1765,7 @@ static ulong rk3568_dclk_vop_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
 		conid = 41;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	con = readl(&cru->clksel_con[conid]);
@@ -1781,7 +1781,7 @@ static ulong rk3568_dclk_vop_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
 	else if (sel == DCLK_VOP_SEL_CPLL)
 		parent = priv->cpll_hz;
 	else
-		return -ENOENT;
+		return 0;
 
 	return DIV_TO_RATE(parent, div);
 }
@@ -1886,7 +1886,7 @@ static ulong rk3568_gmac_src_get_clk(struct rk3568_clk_priv *priv,
 	case CLK_MAC0_2TOP_SEL_PPLL:
 		return rk3568_pmu_pll_get_rate(priv, HPLL);
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -1936,7 +1936,7 @@ static ulong rk3568_gmac_out_get_clk(struct rk3568_clk_priv *priv,
 	case CLK_MAC0_OUT_SEL_24M:
 		return OSC_HZ;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -1989,7 +1989,7 @@ static ulong rk3568_gmac_ptp_ref_get_clk(struct rk3568_clk_priv *priv,
 	case CLK_GMAC0_PTP_REF_SEL_24M:
 		return OSC_HZ;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -2074,7 +2074,7 @@ static ulong rk3568_ebc_get_clk(struct rk3568_clk_priv *priv)
 	case DCLK_EBC_SEL_GPLL_200M:
 		return 200 * MHz;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -2127,7 +2127,7 @@ static ulong rk3568_rkvdec_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
 			p_rate = priv->gpll_hz;
 		return DIV_TO_RATE(p_rate, div);
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -2216,7 +2216,7 @@ static ulong rk3568_uart_get_rate(struct rk3568_clk_priv *priv, ulong clk_id)
 		reg = 68;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 	con = readl(&cru->clksel_con[reg]);
 	src = (con & CLK_UART_SEL_MASK) >> CLK_UART_SEL_SHIFT;
@@ -2323,7 +2323,7 @@ static ulong rk3568_clk_get_rate(struct clk *clk)
 
 	if (!priv->gpll_hz) {
 		printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
-		return -ENOENT;
+		return 0;
 	}
 
 	switch (clk->id) {
@@ -2487,7 +2487,7 @@ static ulong rk3568_clk_get_rate(struct clk *clk)
 		rate = rk3568_cpll_div_get_rate(priv, clk->id);
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return rate;
diff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c
index 125b08ee8322e26ae91b3e8ef8c1fc398db2eab8..3f87b0e26b80085a9bf1bf597995b8a40451bf0d 100644
--- a/drivers/clk/rockchip/clk_rk3576.c
+++ b/drivers/clk/rockchip/clk_rk3576.c
@@ -164,7 +164,7 @@ static ulong rk3576_bus_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
 			rate = OSC_HZ;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return rate;
@@ -281,7 +281,7 @@ static ulong rk3576_top_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
 			rate = OSC_HZ;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return rate;
@@ -406,7 +406,7 @@ static ulong rk3576_i2c_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
 		break;
 
 	default:
-		return -ENOENT;
+		return 0;
 	}
 	if (sel == CLK_I2C_SEL_200M)
 		rate = 200 * MHz;
@@ -509,7 +509,7 @@ static ulong rk3576_spi_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
 		sel = (con & CLK_SPI4_SEL_MASK) >> CLK_SPI4_SEL_SHIFT;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	switch (sel) {
@@ -522,7 +522,7 @@ static ulong rk3576_spi_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
 	case CLK_SPI_SEL_OSC:
 		return OSC_HZ;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -593,7 +593,7 @@ static ulong rk3576_pwm_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
 		sel = (con & CLK_PMU1PWM_SEL_MASK) >> CLK_PMU1PWM_SEL_SHIFT;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	switch (sel) {
@@ -604,7 +604,7 @@ static ulong rk3576_pwm_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
 	case CLK_PWM_SEL_OSC:
 		return OSC_HZ;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -667,7 +667,7 @@ static ulong rk3576_adc_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
 		prate = OSC_HZ;
 		return DIV_TO_RATE(prate, div);
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -808,7 +808,7 @@ static ulong rk3576_mmc_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
 		return DIV_TO_RATE(prate, div);
 
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -992,7 +992,7 @@ static ulong rk3576_aclk_vop_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
 			return OSC_HZ;
 
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -1106,7 +1106,7 @@ static ulong rk3576_dclk_vop_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
 		sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	if (sel == DCLK_VOP_SRC_SEL_VPLL)
@@ -1249,7 +1249,7 @@ static ulong rk3576_clk_csihost_get_clk(struct rk3576_clk_priv *priv, ulong clk_
 		sel = (con & CLK_DSIHOST0_SEL_MASK) >> CLK_DSIHOST0_SEL_SHIFT;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	if (sel == CLK_DSIHOST0_SEL_VPLL)
@@ -1384,7 +1384,7 @@ static ulong rk3576_dclk_ebc_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
 		m >>= CLK_UART_FRAC_DENOMINATOR_SHIFT;
 		return parent * n / m;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -1552,7 +1552,7 @@ static ulong rk3576_gmac_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
 		div = (con & CLK_GMAC1_125M_DIV_MASK) >> CLK_GMAC1_125M_DIV_SHIFT;
 		return DIV_TO_RATE(priv->cpll_hz, div);
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -1634,7 +1634,7 @@ static ulong rk3576_uart_frac_get_rate(struct rk3576_clk_priv *priv, ulong clk_i
 		reg = 25;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 	con = readl(&cru->clksel_con[reg + 1]);
 	p_src = (con & CLK_UART_SRC_SEL_MASK) >> CLK_UART_SRC_SEL_SHIFT;
@@ -1760,7 +1760,7 @@ static ulong rk3576_uart_get_rate(struct rk3576_clk_priv *priv, ulong clk_id)
 		con = readl(&cru->clksel_con[70]);
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 	if (clk_id == SCLK_UART1) {
 		src = (con & CLK_UART1_SRC_SEL_SHIFT) >> CLK_UART1_SRC_SEL_SHIFT;
@@ -1899,7 +1899,7 @@ static ulong rk3576_clk_get_rate(struct clk *clk)
 
 	if (!priv->gpll_hz) {
 		printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
-		return -ENOENT;
+		return 0;
 	}
 
 	if (!priv->ppll_hz) {
@@ -2051,7 +2051,7 @@ static ulong rk3576_clk_get_rate(struct clk *clk)
 		break;
 
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return rate;
diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c
index 8c3a113526f902ef25bd0f661b28a021b18744f2..d04698f2aec3bd10fd9e820cb3eae15f39e3d6ca 100644
--- a/drivers/clk/rockchip/clk_rk3588.c
+++ b/drivers/clk/rockchip/clk_rk3588.c
@@ -188,7 +188,7 @@ static ulong rk3588_center_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
 			rate = OSC_HZ;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return rate;
@@ -300,7 +300,7 @@ static ulong rk3588_top_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
 			rate = OSC_HZ;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return rate;
@@ -402,7 +402,7 @@ static ulong rk3588_i2c_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
 		sel = (con & CLK_I2C8_SEL_MASK) >> CLK_I2C8_SEL_SHIFT;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 	if (sel == CLK_I2C_SEL_200M)
 		rate = 200 * MHz;
@@ -491,7 +491,7 @@ static ulong rk3588_spi_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
 		sel = (con & CLK_SPI4_SEL_MASK) >> CLK_SPI4_SEL_SHIFT;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	switch (sel) {
@@ -575,7 +575,7 @@ static ulong rk3588_pwm_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
 		sel = (con & CLK_PMU1PWM_SEL_MASK) >> CLK_PMU1PWM_SEL_SHIFT;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	switch (sel) {
@@ -659,7 +659,7 @@ static ulong rk3588_adc_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
 			prate = 100 * MHz;
 		return DIV_TO_RATE(prate, div);
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -785,7 +785,7 @@ static ulong rk3588_mmc_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
 			prate = priv->gpll_hz;
 		return DIV_TO_RATE(prate, div);
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -892,7 +892,7 @@ static ulong rk3588_aux16m_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
 		div = (con & CLK_AUX16MHZ_1_DIV_MASK) >> CLK_AUX16MHZ_1_DIV_SHIFT;
 		return DIV_TO_RATE(parent, div);
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -971,7 +971,7 @@ static ulong rk3588_aclk_vop_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
 		else
 			return OSC_HZ;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -1069,7 +1069,7 @@ static ulong rk3588_dclk_vop_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
 		sel = (con & DCLK3_VOP_SRC_SEL_MASK) >> DCLK3_VOP_SRC_SEL_SHIFT;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	if (sel == DCLK_VOP_SRC_SEL_AUPLL)
@@ -1224,7 +1224,7 @@ static ulong rk3588_gmac_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
 		div = (con & CLK_GMAC_50M_DIV_MASK) >> CLK_GMAC_50M_DIV_SHIFT;
 		return DIV_TO_RATE(priv->cpll_hz, div);
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
@@ -1304,7 +1304,7 @@ static ulong rk3588_uart_get_rate(struct rk3588_clk_priv *priv, ulong clk_id)
 		reg = 57;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 	con = readl(&cru->clksel_con[reg + 2]);
 	src = (con & CLK_UART_SEL_MASK) >> CLK_UART_SEL_SHIFT;
@@ -1430,7 +1430,7 @@ static ulong rk3588_pciephy_get_rate(struct rk3588_clk_priv *priv, ulong clk_id)
 		div = (con & CLK_PCIE_PHY2_PLL_DIV_MASK) >> CLK_PCIE_PHY2_PLL_DIV_SHIFT;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	if (src == CLK_PCIE_PHY_REF_SEL_PPLL)
@@ -1487,7 +1487,7 @@ static ulong rk3588_clk_get_rate(struct clk *clk)
 
 	if (!priv->gpll_hz) {
 		printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
-		return -ENOENT;
+		return 0;
 	}
 
 	if (!priv->ppll_hz) {
@@ -1644,7 +1644,7 @@ static ulong rk3588_clk_get_rate(struct clk *clk)
 		break;
 #endif
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return rate;
@@ -2083,7 +2083,7 @@ static ulong rk3588_scru_clk_get_rate(struct clk *clk)
 		else
 			return OSC_HZ;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c
index 75202a66aa68c1a4f820bab29b317ea484f95632..abec0444fbb0aa9d992b844d08cf5826e5fe2fc1 100644
--- a/drivers/clk/rockchip/clk_rv1108.c
+++ b/drivers/clk/rockchip/clk_rv1108.c
@@ -441,7 +441,7 @@ static ulong rv1108_i2c_get_clk(struct rv1108_cru *cru, ulong clk_id)
 		break;
 	default:
 		printf("do not support this i2c bus\n");
-		return -EINVAL;
+		return 0;
 	}
 
 	return DIV_TO_RATE(GPLL_HZ, div);
@@ -568,7 +568,7 @@ static ulong rv1108_clk_get_rate(struct clk *clk)
 	case SCLK_EMMC_SAMPLE:
 		return rv1108_mmc_get_clk(priv->cru);
 	default:
-		return -ENOENT;
+		return 0;
 	}
 }
 
diff --git a/drivers/clk/rockchip/clk_rv1126.c b/drivers/clk/rockchip/clk_rv1126.c
index aeeea95691479e8a6a450fb25b27f1b86d9494cb..073a8dd620843931816803f23ecafadf143c350d 100644
--- a/drivers/clk/rockchip/clk_rv1126.c
+++ b/drivers/clk/rockchip/clk_rv1126.c
@@ -201,7 +201,7 @@ static ulong rv1126_i2c_get_pmuclk(struct rv1126_pmuclk_priv *priv,
 		div = (con & CLK_I2C1_DIV_MASK) >> CLK_I2C1_DIV_SHIFT;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return DIV_TO_RATE(priv->gpll_hz, div);
@@ -254,7 +254,7 @@ static ulong rv1126_pwm_get_pmuclk(struct rv1126_pmuclk_priv *priv,
 			return OSC_HZ;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return DIV_TO_RATE(priv->gpll_hz, div);
@@ -372,7 +372,7 @@ static ulong rv1126_pmuclk_get_rate(struct clk *clk)
 
 	if (!priv->gpll_hz) {
 		printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
-		return -ENOENT;
+		return 0;
 	}
 
 	debug("%s %ld\n", __func__, clk->id);
@@ -399,7 +399,7 @@ static ulong rv1126_pmuclk_get_rate(struct clk *clk)
 		break;
 	default:
 		debug("%s: Unsupported CLK#%ld\n", __func__, clk->id);
-		return -ENOENT;
+		return 0;
 	}
 
 	return rate;
@@ -602,7 +602,7 @@ static ulong rv1126_pdbus_get_clk(struct rv1126_clk_priv *priv, ulong clk_id)
 		else if (sel == ACLK_PDBUS_SEL_CPLL)
 			parent = priv->cpll_hz;
 		else
-			return -ENOENT;
+			return 0;
 		break;
 	case HCLK_PDBUS:
 		con = readl(&cru->clksel_con[2]);
@@ -613,7 +613,7 @@ static ulong rv1126_pdbus_get_clk(struct rv1126_clk_priv *priv, ulong clk_id)
 		else if (sel == HCLK_PDBUS_SEL_CPLL)
 			parent = priv->cpll_hz;
 		else
-			return -ENOENT;
+			return 0;
 		break;
 	case PCLK_PDBUS:
 	case PCLK_WDT:
@@ -625,10 +625,10 @@ static ulong rv1126_pdbus_get_clk(struct rv1126_clk_priv *priv, ulong clk_id)
 		else if (sel == PCLK_PDBUS_SEL_CPLL)
 			parent = priv->cpll_hz;
 		else
-			return -ENOENT;
+			return 0;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return DIV_TO_RATE(parent, div);
@@ -698,7 +698,7 @@ static ulong rv1126_pdphp_get_clk(struct rv1126_clk_priv *priv, ulong clk_id)
 		parent = priv->gpll_hz;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return DIV_TO_RATE(parent, div);
@@ -781,7 +781,7 @@ static ulong rv1126_i2c_get_clk(struct rv1126_clk_priv *priv, ulong clk_id)
 		div = (con & CLK_I2C5_DIV_MASK) >> CLK_I2C5_DIV_SHIFT;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return DIV_TO_RATE(priv->gpll_hz, div);
@@ -921,7 +921,7 @@ static ulong rv1126_crypto_get_clk(struct rv1126_clk_priv *priv, ulong clk_id)
 		else if (sel == CLK_CRYPTO_CORE_SEL_CPLL)
 			parent = priv->cpll_hz;
 		else
-			return -ENOENT;
+			return 0;
 		break;
 	case CLK_CRYPTO_PKA:
 		con = readl(&cru->clksel_con[7]);
@@ -932,7 +932,7 @@ static ulong rv1126_crypto_get_clk(struct rv1126_clk_priv *priv, ulong clk_id)
 		else if (sel == CLK_CRYPTO_PKA_SEL_CPLL)
 			parent = priv->cpll_hz;
 		else
-			return -ENOENT;
+			return 0;
 		break;
 	case ACLK_CRYPTO:
 		con = readl(&cru->clksel_con[4]);
@@ -943,10 +943,10 @@ static ulong rv1126_crypto_get_clk(struct rv1126_clk_priv *priv, ulong clk_id)
 		else if (sel == ACLK_CRYPTO_SEL_CPLL)
 			parent = priv->cpll_hz;
 		else
-			return -ENOENT;
+			return 0;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	return DIV_TO_RATE(parent, div);
@@ -1011,7 +1011,7 @@ static ulong rv1126_mmc_get_clk(struct rv1126_clk_priv *priv, ulong clk_id)
 		con_id = 57;
 		break;
 	default:
-		return -ENOENT;
+		return 0;
 	}
 
 	con = readl(&cru->clksel_con[con_id]);
@@ -1024,7 +1024,7 @@ static ulong rv1126_mmc_get_clk(struct rv1126_clk_priv *priv, ulong clk_id)
 	else if (sel == EMMC_SEL_XIN24M)
 		return DIV_TO_RATE(OSC_HZ, div) / 2;
 
-	return -ENOENT;
+	return 0;
 }
 
 static ulong rv1126_mmc_set_clk(struct rv1126_clk_priv *priv, ulong clk_id,
@@ -1085,7 +1085,7 @@ static ulong rv1126_sfc_get_clk(struct rv1126_clk_priv *priv)
 	else if (sel == SCLK_SFC_SEL_CPLL)
 		parent = priv->cpll_hz;
 	else
-		return -ENOENT;
+		return 0;
 
 	return DIV_TO_RATE(parent, div);
 }
@@ -1117,7 +1117,7 @@ static ulong rv1126_nand_get_clk(struct rv1126_clk_priv *priv)
 	else if (sel == CLK_NANDC_SEL_CPLL)
 		parent = priv->cpll_hz;
 	else
-		return -ENOENT;
+		return 0;
 
 	return DIV_TO_RATE(parent, div);
 }
@@ -1149,7 +1149,7 @@ static ulong rv1126_aclk_vop_get_clk(struct rv1126_clk_priv *priv)
 	else if (sel == ACLK_PDVO_SEL_CPLL)
 		parent = priv->cpll_hz;
 	else
-		return -ENOENT;
+		return 0;
 
 	return DIV_TO_RATE(parent, div);
 }
@@ -1182,7 +1182,7 @@ static ulong rv1126_dclk_vop_get_clk(struct rv1126_clk_priv *priv)
 	else if (sel == DCLK_VOP_SEL_CPLL)
 		parent = priv->cpll_hz;
 	else
-		return -ENOENT;
+		return 0;
 
 	return DIV_TO_RATE(parent, div);
 }
@@ -1245,7 +1245,7 @@ static ulong rv1126_scr1_get_clk(struct rv1126_clk_priv *priv)
 	else if (sel == CLK_SCR1_SEL_CPLL)
 		parent = priv->cpll_hz;
 	else
-		return -ENOENT;
+		return 0;
 
 	return DIV_TO_RATE(parent, div);
 }
@@ -1278,7 +1278,7 @@ static ulong rv1126_gmac_src_get_clk(struct rv1126_clk_priv *priv)
 	else if (sel == CLK_GMAC_SRC_SEL_GPLL)
 		parent = priv->gpll_hz;
 	else
-		return -ENOENT;
+		return 0;
 
 	return DIV_TO_RATE(parent, div);
 }
@@ -1311,7 +1311,7 @@ static ulong rv1126_gmac_out_get_clk(struct rv1126_clk_priv *priv)
 	else if (sel == CLK_GMAC_OUT_SEL_GPLL)
 		parent = priv->gpll_hz;
 	else
-		return -ENOENT;
+		return 0;
 
 	return DIV_TO_RATE(parent, div);
 }
@@ -1386,7 +1386,7 @@ static ulong rv1126_dclk_decom_get_clk(struct rv1126_clk_priv *priv)
 	else if (sel == DCLK_DECOM_SEL_CPLL)
 		parent = priv->cpll_hz;
 	else
-		return -ENOENT;
+		return 0;
 
 	return DIV_TO_RATE(parent, div);
 }
@@ -1413,7 +1413,7 @@ static ulong rv1126_clk_get_rate(struct clk *clk)
 
 	if (!priv->gpll_hz) {
 		printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
-		return -ENOENT;
+		return 0;
 	}
 
 	switch (clk->id) {
@@ -1509,7 +1509,7 @@ static ulong rv1126_clk_get_rate(struct clk *clk)
 		break;
 	default:
 		debug("%s: Unsupported CLK#%ld\n", __func__, clk->id);
-		return -ENOENT;
+		return 0;
 	}
 
 	return rate;

-- 
2.47.3

[PATCH 10/24] clk: starfive: Remove negative error returns from clk_get_rate

[Andrew Goodbody]

clk_get_rate() returns a ulong so do not attempt to pass negative error
codes through it.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
---
 drivers/clk/starfive/clk-jh7110-pll.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c
index f8af17227c502a39cc8f4b77f52a3d88fed210a9..12dd14c02c683bb860743bcb994b549e7a8f74bb 100644
--- a/drivers/clk/starfive/clk-jh7110-pll.c
+++ b/drivers/clk/starfive/clk-jh7110-pll.c
@@ -292,7 +292,7 @@ static ulong jh7110_pllx_recalc_rate(struct clk *clk)
 	else if (dacpd == 0 && dsmpd == 0)
 		do_div(frac, 1 << 24);
 	else
-		return -EINVAL;
+		return 0;
 
 	refclk *= (fbdiv + frac);
 	do_div(refclk, prediv * postdiv1);

-- 
2.47.3

[PATCH 12/24] clk: uniphier: Remove negative error returns from clk_get_rate

[Andrew Goodbody]

clk_get_rate() returns a ulong so do not attempt to pass negative error
codes through it.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
---
 drivers/clk/uniphier/clk-uniphier-core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c
index 33369c93916b06a68f81db056988bd4954adae4c..32e1d7efb86e835a47e0c51bf913fbca4dcb6071 100644
--- a/drivers/clk/uniphier/clk-uniphier-core.c
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -168,7 +168,7 @@ static unsigned long uniphier_clk_get_rate(struct clk *clk)
 
 	data = uniphier_clk_get_data(priv, clk->id);
 	if (!data)
-		return -ENODEV;
+		return 0;
 
 	return __uniphier_clk_get_rate(priv, data);
 }

-- 
2.47.3

[PATCH 14/24] clk: nuvoton: Remove negative error returns from clk_get_rate

[Andrew Goodbody]

clk_get_rate() returns a ulong so do not attempt to pass negative error
codes through it.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
---
 drivers/clk/nuvoton/clk_npcm.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/nuvoton/clk_npcm.c b/drivers/clk/nuvoton/clk_npcm.c
index 18cb9cddbf38f4f68f9d035079ff147a4409878e..304c5f2ca07ba3c3e285494ca07330e572b4cac7 100644
--- a/drivers/clk/nuvoton/clk_npcm.c
+++ b/drivers/clk/nuvoton/clk_npcm.c
@@ -177,11 +177,11 @@ static ulong npcm_clk_get_fout(struct clk *clk)
 
 	parent_rate = npcm_clk_get_fin(clk);
 	if (!parent_rate)
-		return -EINVAL;
+		return 0;
 
 	div = npcm_clk_get_div(clk);
 	if (!div)
-		return -EINVAL;
+		return 0;
 
 	debug("fout of clk%lu = (%lu / %u)\n", clk->id, parent_rate, div);
 	return (parent_rate / div);
@@ -199,12 +199,12 @@ static ulong npcm_clk_get_pll_fout(struct clk *clk)
 
 	pll = npcm_clk_pll_get(priv->clk_data, clk->id);
 	if (!pll)
-		return -ENODEV;
+		return 0;
 
 	parent.id = pll->parent_id;
 	ret = clk_request(clk->dev, &parent);
 	if (ret)
-		return ret;
+		return 0;
 
 	parent_rate = clk_get_rate(&parent);
 
@@ -236,7 +236,7 @@ static ulong npcm_clk_get_rate(struct clk *clk)
 		if (!ret)
 			return clk_get_rate(&refclk);
 		else
-			return ret;
+			return 0;
 	}
 
 	if (clk->id >= clk_data->pll0_id &&

-- 
2.47.3

[PATCH 15/24] clk: exynos: Remove negative error returns from clk_get_rate

[Andrew Goodbody]

clk_get_rate() returns a ulong so do not attempt to pass negative error
codes through it.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
---
 drivers/clk/exynos/clk-exynos7420.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c
index 7de4e688f036d47adfa22c841400770b1b1ed3b3..494f5623259945376475c53dcd8d5b5fbf635b0f 100644
--- a/drivers/clk/exynos/clk-exynos7420.c
+++ b/drivers/clk/exynos/clk-exynos7420.c
@@ -199,7 +199,7 @@ static ulong exynos7420_peric1_get_rate(struct clk *clk)
 	case SCLK_UART2:
 		ret = clk_get_by_index(clk->dev, 3, &in_clk);
 		if (ret < 0)
-			return ret;
+			return 0;
 		freq = clk_get_rate(&in_clk);
 		break;
 	}

-- 
2.47.3

[PATCH 20/24] clk: tegra: Remove negative error returns from clk_get_rate

[Andrew Goodbody]

clk_get_rate() returns a ulong so do not attempt to pass negative error
codes through it.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
---
 drivers/clk/tegra/tegra-car-clk.c | 2 +-
 drivers/clk/tegra/tegra186-clk.c  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/tegra/tegra-car-clk.c b/drivers/clk/tegra/tegra-car-clk.c
index 880dd4f6ece9fde3ef3dd9d457e717ce4c237e29..19ca5583a53427d05936cf65b6a32237d91df4ae 100644
--- a/drivers/clk/tegra/tegra-car-clk.c
+++ b/drivers/clk/tegra/tegra-car-clk.c
@@ -57,7 +57,7 @@ static ulong tegra_car_clk_get_rate(struct clk *clk)
 		return clock_get_periph_rate(clk->id, parent);
 	}
 
-	return -1U;
+	return 0;
 }
 
 static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate)
diff --git a/drivers/clk/tegra/tegra186-clk.c b/drivers/clk/tegra/tegra186-clk.c
index ec52326c3b365eac9845e2fb98531ae0da2f486a..8c364e2dd3412d1298bd39178f19b3cb609aba5a 100644
--- a/drivers/clk/tegra/tegra186-clk.c
+++ b/drivers/clk/tegra/tegra186-clk.c
@@ -23,7 +23,7 @@ static ulong tegra186_clk_get_rate(struct clk *clk)
 	ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp,
 			sizeof(resp));
 	if (ret < 0)
-		return ret;
+		return 0;
 
 	return resp.clk_get_rate.rate;
 }

-- 
2.47.3

[PATCH 24/24] clk: x86: Remove negative error returns from clk_get_rate

[Andrew Goodbody]

clk_get_rate() returns a ulong so do not attempt to pass negative error
codes through it.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
---
 drivers/clk/intel/clk_intel.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/intel/clk_intel.c b/drivers/clk/intel/clk_intel.c
index a677a7caac7c84e5576a8b228e8ce4493a2e92b3..b5f3e800431314f4c2617133c1afad99dac35787 100644
--- a/drivers/clk/intel/clk_intel.c
+++ b/drivers/clk/intel/clk_intel.c
@@ -15,7 +15,7 @@ static ulong intel_clk_get_rate(struct clk *clk)
 		/* Hard-coded to 133MHz on current platforms */
 		return 133333333;
 	default:
-		return -ENODEV;
+		return 0;
 	}
 }
 

-- 
2.47.3

Re: [PATCH 04/24] clk: thead: th1520-ap: Remove negative error returns from clk_get_rate

[Yao Zi]

On Wed, Oct 15, 2025 at 03:32:09PM +0100, Andrew Goodbody wrote:
> clk_get_rate() returns a ulong so do not attempt to pass negative error
> codes through it.
> 
> Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
> ---
>  drivers/clk/thead/clk-th1520-ap.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

I want to switch to ccf_clk_* in the future, but this patch looks good
to me as a fix alone.

Acked-by: Yao Zi <ziyao@disroot.org>

Tested on Lichee Pi 4A board with no regression found.

Best regards,
Yao Zi

> diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c
> index 6899e1b595a7148a118d3a615d5dfea4b4fb5b96..e913621967eb131b534e8f5b928687967a02a30e 100644
> --- a/drivers/clk/thead/clk-th1520-ap.c
> +++ b/drivers/clk/thead/clk-th1520-ap.c
> @@ -985,7 +985,7 @@ static ulong th1520_clk_get_rate(struct clk *clk)
>  
>  	ret = clk_get_by_id(clk->id, &c);
>  	if (ret)
> -		return ret;
> +		return 0;
>  
>  	return clk_get_rate(c);
>  }
> 
> -- 
> 2.47.3
> 

Re: [PATCH 23/24] clk: stm32: Remove negative error returns from clk_get_rate

[Patrice CHOTARD]

On 10/15/25 16:32, Andrew Goodbody wrote:
> clk_get_rate() returns a ulong so do not attempt to pass negative error
> codes through it.
> 
> Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
> ---
>  drivers/clk/stm32/clk-stm32-core.c | 4 ++--
>  drivers/clk/stm32/clk-stm32f.c     | 6 +++---
>  drivers/clk/stm32/clk-stm32h7.c    | 4 ++--
>  3 files changed, 7 insertions(+), 7 deletions(-)


Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>

Thanks
Patrice

> 
> diff --git a/drivers/clk/stm32/clk-stm32-core.c b/drivers/clk/stm32/clk-stm32-core.c
> index 858f122db1a6db02eadc110a7b3e14192654d8ff..5220d49d4206808734f9838d3e55298cf6b163ab 100644
> --- a/drivers/clk/stm32/clk-stm32-core.c
> +++ b/drivers/clk/stm32/clk-stm32-core.c
> @@ -106,11 +106,11 @@ static ulong stm32_clk_get_rate(struct clk *clk)
>  	struct clk *c = NULL;
>  
>  	if (!clk->id || clk_get_by_id(clk->id, &c))
> -		return -ENOENT;
> +		return 0;
>  
>  	ops = clk_dev_ops(c->dev);
>  	if (!ops->get_rate)
> -		return -ENOSYS;
> +		return 0;
>  
>  	return ops->get_rate(c);
>  }
> diff --git a/drivers/clk/stm32/clk-stm32f.c b/drivers/clk/stm32/clk-stm32f.c
> index fceb3c44b94e4e4f5249ff1bc99c7ae4adba4316..db64139d13d4b3fff74838d9e14ae6c5e61c7941 100644
> --- a/drivers/clk/stm32/clk-stm32f.c
> +++ b/drivers/clk/stm32/clk-stm32f.c
> @@ -310,7 +310,7 @@ static unsigned long stm32_clk_get_pllsai_rate(struct stm32_clk *priv,
>  		break;
>  	default:
>  		log_err("incorrect PLLSAI output %d\n", output);
> -		return -EINVAL;
> +		return 0;
>  	}
>  
>  	return (stm32_clk_get_pllsai_vco_rate(priv) / pll_div_output);
> @@ -414,7 +414,7 @@ static ulong stm32_clk_get_rate(struct clk *clk)
>  		vco = (priv->hse_rate / pllm) * plln;
>  		sysclk = vco / pllp;
>  	} else {
> -		return -EINVAL;
> +		return 0;
>  	}
>  
>  	switch (clk->id) {
> @@ -491,7 +491,7 @@ static ulong stm32_clk_get_rate(struct clk *clk)
>  
>  	default:
>  		dev_err(clk->dev, "clock index %ld out of range\n", clk->id);
> -		return -EINVAL;
> +		return 0;
>  	}
>  }
>  
> diff --git a/drivers/clk/stm32/clk-stm32h7.c b/drivers/clk/stm32/clk-stm32h7.c
> index df82db69738a5d9704592d5cdbec52125c0620a1..eb8fb72976b60c8016408693631470a0e369e8cb 100644
> --- a/drivers/clk/stm32/clk-stm32h7.c
> +++ b/drivers/clk/stm32/clk-stm32h7.c
> @@ -573,7 +573,7 @@ static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs,
>  		break;
>  	}
>  
> -	return -EINVAL;
> +	return 0;
>  }
>  
>  static u32 stm32_get_apb_psc(struct stm32_rcc_regs *regs, enum apb apb)
> @@ -780,7 +780,7 @@ static ulong stm32_clk_get_rate(struct clk *clk)
>  	default:
>  		dev_err(clk->dev, "unexpected gate_offset value (0x%x)\n",
>  			gate_offset);
> -		return -EINVAL;
> +		return 0;
>  		break;
>  	}
>  }
> 

Re: [PATCH 21/24] clk: adi: Remove negative error returns from clk_get_rate

[Greg Malysa]

On Wed, Oct 15, 2025 at 10:33 AM Andrew Goodbody
<andrew.goodbody@linaro.org> wrote:
>
> clk_get_rate() returns a ulong so do not attempt to pass negative error
> codes through it.
>
> Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
> ---
>  drivers/clk/adi/clk-shared.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/adi/clk-shared.c b/drivers/clk/adi/clk-shared.c
> index dcadcafa9d236882af8c7b397eeeeb44461a23cb..600e22940e8cb60b1e510a74ee8068ccf0c7848a 100644
> --- a/drivers/clk/adi/clk-shared.c
> +++ b/drivers/clk/adi/clk-shared.c
> @@ -16,7 +16,7 @@ static ulong adi_get_rate(struct clk *clk)
>
>         ret = clk_get_by_id(clk->id, &c);
>         if (ret)
> -               return ret;
> +               return 0;
>
>         return clk_get_rate(c);
>  }
>
> --
> 2.47.3
>

Reviewed-by: Greg Malysa <malysagreg@gmail.com>

Tested on my sc573 and sc598 boards, looks good.

Thanks,
Greg

Re: [PATCH 10/24] clk: starfive: Remove negative error returns from clk_get_rate

[Hal Feng]

> On 15.10.25 22:32, Andrew Goodbody wrote:
> clk_get_rate() returns a ulong so do not attempt to pass negative error codes
> through it.
> 
> Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>

Reviewed-by: Hal Feng <hal.feng@starfivetech.com>

Best regards,
Hal Feng

> ---
>  drivers/clk/starfive/clk-jh7110-pll.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-
> jh7110-pll.c
> index
> f8af17227c502a39cc8f4b77f52a3d88fed210a9..12dd14c02c683bb860743
> bcb994b549e7a8f74bb 100644
> --- a/drivers/clk/starfive/clk-jh7110-pll.c
> +++ b/drivers/clk/starfive/clk-jh7110-pll.c
> @@ -292,7 +292,7 @@ static ulong jh7110_pllx_recalc_rate(struct clk *clk)
>  	else if (dacpd == 0 && dsmpd == 0)
>  		do_div(frac, 1 << 24);
>  	else
> -		return -EINVAL;
> +		return 0;
> 
>  	refclk *= (fbdiv + frac);
>  	do_div(refclk, prediv * postdiv1);
> 
> --
> 2.47.3

Re: [PATCH 00/24] clk: Remove passing of negative errors through unsigned return

[Simon Glass]

Hi Andrew,

On Wed, 15 Oct 2025 at 15:32, Andrew Goodbody
<andrew.goodbody@linaro.org> wrote:
>
> This series removes the passing of negative errors through the .get_rate
> function in the clk_ops struct. This function returns an unsigned long.
> The only value guaranteed to not be a valid clock rate is 0. This will
> also bring the drivers more in sync with Linux to allow for easier code
> porting and other maintenance in the future.
> Another series will address the calling of clk_get_rate and associated
> error handling.

Some indication of the problem you ran into would be useful here.

>
> Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
> ---
> Andrew Goodbody (24):
>       clk: meson: Remove negative error returns from clk_get_rate
>       clk: sifive: Remove negative error returns from clk_get_rate
>       clk: armada-37xx: Remove negative error returns from clk_get_rate
>       clk: thead: th1520-ap: Remove negative error returns from clk_get_rate
>       clk: ccf: Remove negative error returns from clk_get_rate
>       clk: at91: Remove negative error returns from clk_get_rate
>       clk: renesas: Remove negative error returns from clk_get_rate
>       clk: rockchip: Remove negative error returns from clk_get_rate
>       clk: Remove negative error returns from clk_get_rate
>       clk: starfive: Remove negative error returns from clk_get_rate
>       clk: altera: Remove negative error returns from clk_get_rate
>       clk: uniphier: Remove negative error returns from clk_get_rate
>       clk: aspeed: Remove negative error returns from clk_get_rate
>       clk: nuvoton: Remove negative error returns from clk_get_rate
>       clk: exynos: Remove negative error returns from clk_get_rate
>       clk: imx: Remove negative error returns from clk_get_rate
>       clk: ti: Remove negative error returns from clk_get_rate
>       clk: mediatek: Remove negative error returns from clk_get_rate
>       clk: owl: Remove negative error returns from clk_get_rate
>       clk: tegra: Remove negative error returns from clk_get_rate
>       clk: adi: Remove negative error returns from clk_get_rate
>       clk: sophgo: Remove negative error returns from clk_get_rate
>       clk: stm32: Remove negative error returns from clk_get_rate
>       clk: x86: Remove negative error returns from clk_get_rate
>
>  drivers/clk/adi/clk-shared.c             |  2 +-
>  drivers/clk/altera/clk-agilex.c          |  2 +-
>  drivers/clk/altera/clk-agilex5.c         |  2 +-
>  drivers/clk/altera/clk-n5x.c             |  2 +-
>  drivers/clk/aspeed/clk_ast2500.c         |  2 +-
>  drivers/clk/aspeed/clk_ast2600.c         |  2 +-
>  drivers/clk/at91/compat.c                |  6 ++--
>  drivers/clk/clk-hsdk-cgu.c               |  2 +-
>  drivers/clk/clk-uclass.c                 |  4 +--
>  drivers/clk/clk.c                        |  2 +-
>  drivers/clk/clk_fixed_factor.c           |  4 +--
>  drivers/clk/clk_k210.c                   |  6 ++--
>  drivers/clk/clk_sandbox.c                |  4 +--
>  drivers/clk/clk_scmi.c                   |  4 +--
>  drivers/clk/clk_vexpress_osc.c           |  2 +-
>  drivers/clk/clk_zynq.c                   |  4 +--
>  drivers/clk/clk_zynqmp.c                 | 40 ++++++++++-----------
>  drivers/clk/exynos/clk-exynos7420.c      |  2 +-
>  drivers/clk/imx/clk-imx8qm.c             |  6 ++--
>  drivers/clk/imx/clk-imx8qxp.c            |  6 ++--
>  drivers/clk/imx/clk-imxrt1170.c          |  2 +-
>  drivers/clk/imx/clk-pllv3.c              |  2 +-
>  drivers/clk/intel/clk_intel.c            |  2 +-
>  drivers/clk/mediatek/clk-mtk.c           |  2 +-
>  drivers/clk/meson/a1.c                   | 10 +++---
>  drivers/clk/meson/axg.c                  | 10 +++---
>  drivers/clk/meson/g12a.c                 | 36 +++++++++----------
>  drivers/clk/meson/gxbb.c                 | 20 +++++------
>  drivers/clk/mvebu/armada-37xx-periph.c   |  2 +-
>  drivers/clk/mvebu/armada-37xx-tbg.c      |  2 +-
>  drivers/clk/nuvoton/clk_npcm.c           | 10 +++---
>  drivers/clk/owl/clk_owl.c                |  2 +-
>  drivers/clk/renesas/clk-rcar-gen2.c      |  8 ++---
>  drivers/clk/renesas/rzg2l-cpg.c          |  8 ++---
>  drivers/clk/rockchip/clk_px30.c          | 24 ++++++-------
>  drivers/clk/rockchip/clk_rk3036.c        |  2 +-
>  drivers/clk/rockchip/clk_rk3066.c        |  8 ++---
>  drivers/clk/rockchip/clk_rk3128.c        |  6 ++--
>  drivers/clk/rockchip/clk_rk3188.c        |  6 ++--
>  drivers/clk/rockchip/clk_rk322x.c        |  4 +--
>  drivers/clk/rockchip/clk_rk3288.c        |  6 ++--
>  drivers/clk/rockchip/clk_rk3308.c        | 26 +++++++-------
>  drivers/clk/rockchip/clk_rk3328.c        |  6 ++--
>  drivers/clk/rockchip/clk_rk3368.c        |  8 ++---
>  drivers/clk/rockchip/clk_rk3399.c        | 12 +++----
>  drivers/clk/rockchip/clk_rk3528.c        | 20 +++++------
>  drivers/clk/rockchip/clk_rk3568.c        | 62 ++++++++++++++++----------------
>  drivers/clk/rockchip/clk_rk3576.c        | 36 +++++++++----------
>  drivers/clk/rockchip/clk_rk3588.c        | 32 ++++++++---------
>  drivers/clk/rockchip/clk_rv1108.c        |  4 +--
>  drivers/clk/rockchip/clk_rv1126.c        | 52 +++++++++++++--------------
>  drivers/clk/sifive/sifive-prci.c         |  8 ++---
>  drivers/clk/sophgo/clk-cv1800b.c         |  2 +-
>  drivers/clk/starfive/clk-jh7110-pll.c    |  2 +-
>  drivers/clk/stm32/clk-stm32-core.c       |  4 +--
>  drivers/clk/stm32/clk-stm32f.c           |  6 ++--
>  drivers/clk/stm32/clk-stm32h7.c          |  4 +--
>  drivers/clk/tegra/tegra-car-clk.c        |  2 +-
>  drivers/clk/tegra/tegra186-clk.c         |  2 +-
>  drivers/clk/thead/clk-th1520-ap.c        |  2 +-
>  drivers/clk/ti/clk-am3-dpll-x2.c         |  4 +--
>  drivers/clk/ti/clk-divider.c             |  4 +--
>  drivers/clk/ti/clk-mux.c                 |  2 +-
>  drivers/clk/ti/clk-sci.c                 |  2 +-
>  drivers/clk/uniphier/clk-uniphier-core.c |  2 +-
>  65 files changed, 290 insertions(+), 290 deletions(-)
> ---
> base-commit: ecdc3872a767fb045be3296d4317ae978a14b022
> change-id: 20251010-clk_ops-3b7cc9ccd070
>
> Best regards,
> --
> Andrew Goodbody <andrew.goodbody@linaro.org>
>

If you don't return an error, we cannot tell if the operation
succeeded, or not. U-Boot needs to be deterministic and we need to be
able to debug errors and detect them at runtime.

We use ulong for the return value as a bit of a compromise, since it
is inefficient to use 64-bit on a 32-bit machine. Ideally it would be
long, but some clock rates are 3GHz and it would be confusing to cast
to ulong before using the value.

An alternative we discussed was to return an integer error with the
clock rate returned in a parameter, but that seemed less efficient.

With 64-bit machines, there really isn't a problem. Just checking for
a negative value is good enough, since the clock rate isn't going to
be 9 exahertz(?). Values between -CONFIG_ERR_PTR_OFFSET and 0 are
errors and are defined to be so.

If you want clk_get_rate() to work like Linux (suppress / ignore
errors?), that's fine, but please create a clk_get_rate_err() (or
similar) which actually returns the correct error, and keep the error
return on the uclass interface. It is not uncommon to have the uclass
do some processing on values passed to/from driver. This allows people
who care to obtain the error.

Regards,
Simon

Re: [PATCH 01/24] clk: meson: Remove negative error returns from clk_get_rate

[Simon Glass]

Hi Andrew,

On Wed, 15 Oct 2025 at 15:32, Andrew Goodbody
<andrew.goodbody@linaro.org> wrote:
>
> clk_get_rate() returns a ulong so do not attempt to pass negative error
> codes through it.
>
> Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
> ---
>  drivers/clk/meson/a1.c   | 10 +++++-----
>  drivers/clk/meson/axg.c  | 10 +++++-----
>  drivers/clk/meson/g12a.c | 36 ++++++++++++++++++------------------
>  drivers/clk/meson/gxbb.c | 20 ++++++++++----------
>  4 files changed, 38 insertions(+), 38 deletions(-)
>

Don't change the driver interface...just update the uclass.

Regards,
Simon

Re: [PATCH 00/24] clk: Remove passing of negative errors through unsigned return

[Tom Rini]

[-- Attachment #1: Type: text/plain, Size: 8183 bytes --]

On Sat, Oct 18, 2025 at 09:34:42AM +0100, Simon Glass wrote:
> Hi Andrew,
> 
> On Wed, 15 Oct 2025 at 15:32, Andrew Goodbody
> <andrew.goodbody@linaro.org> wrote:
> >
> > This series removes the passing of negative errors through the .get_rate
> > function in the clk_ops struct. This function returns an unsigned long.
> > The only value guaranteed to not be a valid clock rate is 0. This will
> > also bring the drivers more in sync with Linux to allow for easier code
> > porting and other maintenance in the future.
> > Another series will address the calling of clk_get_rate and associated
> > error handling.
> 
> Some indication of the problem you ran into would be useful here.

The problem statement is in the paragraph you're quoting. The numerical
value of -ENOENT is a valid clock rate.

> > Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
> > ---
> > Andrew Goodbody (24):
> >       clk: meson: Remove negative error returns from clk_get_rate
> >       clk: sifive: Remove negative error returns from clk_get_rate
> >       clk: armada-37xx: Remove negative error returns from clk_get_rate
> >       clk: thead: th1520-ap: Remove negative error returns from clk_get_rate
> >       clk: ccf: Remove negative error returns from clk_get_rate
> >       clk: at91: Remove negative error returns from clk_get_rate
> >       clk: renesas: Remove negative error returns from clk_get_rate
> >       clk: rockchip: Remove negative error returns from clk_get_rate
> >       clk: Remove negative error returns from clk_get_rate
> >       clk: starfive: Remove negative error returns from clk_get_rate
> >       clk: altera: Remove negative error returns from clk_get_rate
> >       clk: uniphier: Remove negative error returns from clk_get_rate
> >       clk: aspeed: Remove negative error returns from clk_get_rate
> >       clk: nuvoton: Remove negative error returns from clk_get_rate
> >       clk: exynos: Remove negative error returns from clk_get_rate
> >       clk: imx: Remove negative error returns from clk_get_rate
> >       clk: ti: Remove negative error returns from clk_get_rate
> >       clk: mediatek: Remove negative error returns from clk_get_rate
> >       clk: owl: Remove negative error returns from clk_get_rate
> >       clk: tegra: Remove negative error returns from clk_get_rate
> >       clk: adi: Remove negative error returns from clk_get_rate
> >       clk: sophgo: Remove negative error returns from clk_get_rate
> >       clk: stm32: Remove negative error returns from clk_get_rate
> >       clk: x86: Remove negative error returns from clk_get_rate
> >
> >  drivers/clk/adi/clk-shared.c             |  2 +-
> >  drivers/clk/altera/clk-agilex.c          |  2 +-
> >  drivers/clk/altera/clk-agilex5.c         |  2 +-
> >  drivers/clk/altera/clk-n5x.c             |  2 +-
> >  drivers/clk/aspeed/clk_ast2500.c         |  2 +-
> >  drivers/clk/aspeed/clk_ast2600.c         |  2 +-
> >  drivers/clk/at91/compat.c                |  6 ++--
> >  drivers/clk/clk-hsdk-cgu.c               |  2 +-
> >  drivers/clk/clk-uclass.c                 |  4 +--
> >  drivers/clk/clk.c                        |  2 +-
> >  drivers/clk/clk_fixed_factor.c           |  4 +--
> >  drivers/clk/clk_k210.c                   |  6 ++--
> >  drivers/clk/clk_sandbox.c                |  4 +--
> >  drivers/clk/clk_scmi.c                   |  4 +--
> >  drivers/clk/clk_vexpress_osc.c           |  2 +-
> >  drivers/clk/clk_zynq.c                   |  4 +--
> >  drivers/clk/clk_zynqmp.c                 | 40 ++++++++++-----------
> >  drivers/clk/exynos/clk-exynos7420.c      |  2 +-
> >  drivers/clk/imx/clk-imx8qm.c             |  6 ++--
> >  drivers/clk/imx/clk-imx8qxp.c            |  6 ++--
> >  drivers/clk/imx/clk-imxrt1170.c          |  2 +-
> >  drivers/clk/imx/clk-pllv3.c              |  2 +-
> >  drivers/clk/intel/clk_intel.c            |  2 +-
> >  drivers/clk/mediatek/clk-mtk.c           |  2 +-
> >  drivers/clk/meson/a1.c                   | 10 +++---
> >  drivers/clk/meson/axg.c                  | 10 +++---
> >  drivers/clk/meson/g12a.c                 | 36 +++++++++----------
> >  drivers/clk/meson/gxbb.c                 | 20 +++++------
> >  drivers/clk/mvebu/armada-37xx-periph.c   |  2 +-
> >  drivers/clk/mvebu/armada-37xx-tbg.c      |  2 +-
> >  drivers/clk/nuvoton/clk_npcm.c           | 10 +++---
> >  drivers/clk/owl/clk_owl.c                |  2 +-
> >  drivers/clk/renesas/clk-rcar-gen2.c      |  8 ++---
> >  drivers/clk/renesas/rzg2l-cpg.c          |  8 ++---
> >  drivers/clk/rockchip/clk_px30.c          | 24 ++++++-------
> >  drivers/clk/rockchip/clk_rk3036.c        |  2 +-
> >  drivers/clk/rockchip/clk_rk3066.c        |  8 ++---
> >  drivers/clk/rockchip/clk_rk3128.c        |  6 ++--
> >  drivers/clk/rockchip/clk_rk3188.c        |  6 ++--
> >  drivers/clk/rockchip/clk_rk322x.c        |  4 +--
> >  drivers/clk/rockchip/clk_rk3288.c        |  6 ++--
> >  drivers/clk/rockchip/clk_rk3308.c        | 26 +++++++-------
> >  drivers/clk/rockchip/clk_rk3328.c        |  6 ++--
> >  drivers/clk/rockchip/clk_rk3368.c        |  8 ++---
> >  drivers/clk/rockchip/clk_rk3399.c        | 12 +++----
> >  drivers/clk/rockchip/clk_rk3528.c        | 20 +++++------
> >  drivers/clk/rockchip/clk_rk3568.c        | 62 ++++++++++++++++----------------
> >  drivers/clk/rockchip/clk_rk3576.c        | 36 +++++++++----------
> >  drivers/clk/rockchip/clk_rk3588.c        | 32 ++++++++---------
> >  drivers/clk/rockchip/clk_rv1108.c        |  4 +--
> >  drivers/clk/rockchip/clk_rv1126.c        | 52 +++++++++++++--------------
> >  drivers/clk/sifive/sifive-prci.c         |  8 ++---
> >  drivers/clk/sophgo/clk-cv1800b.c         |  2 +-
> >  drivers/clk/starfive/clk-jh7110-pll.c    |  2 +-
> >  drivers/clk/stm32/clk-stm32-core.c       |  4 +--
> >  drivers/clk/stm32/clk-stm32f.c           |  6 ++--
> >  drivers/clk/stm32/clk-stm32h7.c          |  4 +--
> >  drivers/clk/tegra/tegra-car-clk.c        |  2 +-
> >  drivers/clk/tegra/tegra186-clk.c         |  2 +-
> >  drivers/clk/thead/clk-th1520-ap.c        |  2 +-
> >  drivers/clk/ti/clk-am3-dpll-x2.c         |  4 +--
> >  drivers/clk/ti/clk-divider.c             |  4 +--
> >  drivers/clk/ti/clk-mux.c                 |  2 +-
> >  drivers/clk/ti/clk-sci.c                 |  2 +-
> >  drivers/clk/uniphier/clk-uniphier-core.c |  2 +-
> >  65 files changed, 290 insertions(+), 290 deletions(-)
> > ---
> > base-commit: ecdc3872a767fb045be3296d4317ae978a14b022
> > change-id: 20251010-clk_ops-3b7cc9ccd070
> >
> > Best regards,
> > --
> > Andrew Goodbody <andrew.goodbody@linaro.org>
> >
> 
> If you don't return an error, we cannot tell if the operation
> succeeded, or not. U-Boot needs to be deterministic and we need to be
> able to debug errors and detect them at runtime.
> 
> We use ulong for the return value as a bit of a compromise, since it
> is inefficient to use 64-bit on a 32-bit machine. Ideally it would be
> long, but some clock rates are 3GHz and it would be confusing to cast
> to ulong before using the value.
> 
> An alternative we discussed was to return an integer error with the
> clock rate returned in a parameter, but that seemed less efficient.
> 
> With 64-bit machines, there really isn't a problem. Just checking for
> a negative value is good enough, since the clock rate isn't going to
> be 9 exahertz(?). Values between -CONFIG_ERR_PTR_OFFSET and 0 are
> errors and are defined to be so.
> 
> If you want clk_get_rate() to work like Linux (suppress / ignore
> errors?), that's fine, but please create a clk_get_rate_err() (or
> similar) which actually returns the correct error, and keep the error
> return on the uclass interface. It is not uncommon to have the uclass
> do some processing on values passed to/from driver. This allows people
> who care to obtain the error.

This is moving things in the right direction of having the error
reporting and handling done where it can be done correctly. If there's
further parts of the Linux kernel-like API we need, we can take those
next.

-- 
Tom

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH 00/24] clk: Remove passing of negative errors through unsigned return

[Philipp Tomsich]

On Sat, 18 Oct 2025 at 16:04, Tom Rini <trini@konsulko.com> wrote:
>
> On Sat, Oct 18, 2025 at 09:34:42AM +0100, Simon Glass wrote:
> > Hi Andrew,
> >
> > On Wed, 15 Oct 2025 at 15:32, Andrew Goodbody
> > <andrew.goodbody@linaro.org> wrote:
> > >
> > > This series removes the passing of negative errors through the .get_rate
> > > function in the clk_ops struct. This function returns an unsigned long.
> > > The only value guaranteed to not be a valid clock rate is 0. This will
> > > also bring the drivers more in sync with Linux to allow for easier code
> > > porting and other maintenance in the future.
> > > Another series will address the calling of clk_get_rate and associated
> > > error handling.

Just one concern: this series drops all indications of what happened
(as in "cause").  We shouldn't postpone the changes to refactor the
error reporting/handling.

As is, this change is error-prone: this series would wipe out all the
cause-indications and checking the later adding of error handling
would have to be manually checked to see if the same error causes have
been added back in for the new mechanism.
I would prefer to see the code changes sequenced such that any
additional error reporting functions are introduced and wired up,
before wrapping those up in a clk_get_rate() that omits the cause for
failures.

Cheers,
Philipp.

> > Some indication of the problem you ran into would be useful here.
>
> The problem statement is in the paragraph you're quoting. The numerical
> value of -ENOENT is a valid clock rate.
>
> > > Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
> > > ---
> > > Andrew Goodbody (24):
> > >       clk: meson: Remove negative error returns from clk_get_rate
> > >       clk: sifive: Remove negative error returns from clk_get_rate
> > >       clk: armada-37xx: Remove negative error returns from clk_get_rate
> > >       clk: thead: th1520-ap: Remove negative error returns from clk_get_rate
> > >       clk: ccf: Remove negative error returns from clk_get_rate
> > >       clk: at91: Remove negative error returns from clk_get_rate
> > >       clk: renesas: Remove negative error returns from clk_get_rate
> > >       clk: rockchip: Remove negative error returns from clk_get_rate
> > >       clk: Remove negative error returns from clk_get_rate
> > >       clk: starfive: Remove negative error returns from clk_get_rate
> > >       clk: altera: Remove negative error returns from clk_get_rate
> > >       clk: uniphier: Remove negative error returns from clk_get_rate
> > >       clk: aspeed: Remove negative error returns from clk_get_rate
> > >       clk: nuvoton: Remove negative error returns from clk_get_rate
> > >       clk: exynos: Remove negative error returns from clk_get_rate
> > >       clk: imx: Remove negative error returns from clk_get_rate
> > >       clk: ti: Remove negative error returns from clk_get_rate
> > >       clk: mediatek: Remove negative error returns from clk_get_rate
> > >       clk: owl: Remove negative error returns from clk_get_rate
> > >       clk: tegra: Remove negative error returns from clk_get_rate
> > >       clk: adi: Remove negative error returns from clk_get_rate
> > >       clk: sophgo: Remove negative error returns from clk_get_rate
> > >       clk: stm32: Remove negative error returns from clk_get_rate
> > >       clk: x86: Remove negative error returns from clk_get_rate
> > >
> > >  drivers/clk/adi/clk-shared.c             |  2 +-
> > >  drivers/clk/altera/clk-agilex.c          |  2 +-
> > >  drivers/clk/altera/clk-agilex5.c         |  2 +-
> > >  drivers/clk/altera/clk-n5x.c             |  2 +-
> > >  drivers/clk/aspeed/clk_ast2500.c         |  2 +-
> > >  drivers/clk/aspeed/clk_ast2600.c         |  2 +-
> > >  drivers/clk/at91/compat.c                |  6 ++--
> > >  drivers/clk/clk-hsdk-cgu.c               |  2 +-
> > >  drivers/clk/clk-uclass.c                 |  4 +--
> > >  drivers/clk/clk.c                        |  2 +-
> > >  drivers/clk/clk_fixed_factor.c           |  4 +--
> > >  drivers/clk/clk_k210.c                   |  6 ++--
> > >  drivers/clk/clk_sandbox.c                |  4 +--
> > >  drivers/clk/clk_scmi.c                   |  4 +--
> > >  drivers/clk/clk_vexpress_osc.c           |  2 +-
> > >  drivers/clk/clk_zynq.c                   |  4 +--
> > >  drivers/clk/clk_zynqmp.c                 | 40 ++++++++++-----------
> > >  drivers/clk/exynos/clk-exynos7420.c      |  2 +-
> > >  drivers/clk/imx/clk-imx8qm.c             |  6 ++--
> > >  drivers/clk/imx/clk-imx8qxp.c            |  6 ++--
> > >  drivers/clk/imx/clk-imxrt1170.c          |  2 +-
> > >  drivers/clk/imx/clk-pllv3.c              |  2 +-
> > >  drivers/clk/intel/clk_intel.c            |  2 +-
> > >  drivers/clk/mediatek/clk-mtk.c           |  2 +-
> > >  drivers/clk/meson/a1.c                   | 10 +++---
> > >  drivers/clk/meson/axg.c                  | 10 +++---
> > >  drivers/clk/meson/g12a.c                 | 36 +++++++++----------
> > >  drivers/clk/meson/gxbb.c                 | 20 +++++------
> > >  drivers/clk/mvebu/armada-37xx-periph.c   |  2 +-
> > >  drivers/clk/mvebu/armada-37xx-tbg.c      |  2 +-
> > >  drivers/clk/nuvoton/clk_npcm.c           | 10 +++---
> > >  drivers/clk/owl/clk_owl.c                |  2 +-
> > >  drivers/clk/renesas/clk-rcar-gen2.c      |  8 ++---
> > >  drivers/clk/renesas/rzg2l-cpg.c          |  8 ++---
> > >  drivers/clk/rockchip/clk_px30.c          | 24 ++++++-------
> > >  drivers/clk/rockchip/clk_rk3036.c        |  2 +-
> > >  drivers/clk/rockchip/clk_rk3066.c        |  8 ++---
> > >  drivers/clk/rockchip/clk_rk3128.c        |  6 ++--
> > >  drivers/clk/rockchip/clk_rk3188.c        |  6 ++--
> > >  drivers/clk/rockchip/clk_rk322x.c        |  4 +--
> > >  drivers/clk/rockchip/clk_rk3288.c        |  6 ++--
> > >  drivers/clk/rockchip/clk_rk3308.c        | 26 +++++++-------
> > >  drivers/clk/rockchip/clk_rk3328.c        |  6 ++--
> > >  drivers/clk/rockchip/clk_rk3368.c        |  8 ++---
> > >  drivers/clk/rockchip/clk_rk3399.c        | 12 +++----
> > >  drivers/clk/rockchip/clk_rk3528.c        | 20 +++++------
> > >  drivers/clk/rockchip/clk_rk3568.c        | 62 ++++++++++++++++----------------
> > >  drivers/clk/rockchip/clk_rk3576.c        | 36 +++++++++----------
> > >  drivers/clk/rockchip/clk_rk3588.c        | 32 ++++++++---------
> > >  drivers/clk/rockchip/clk_rv1108.c        |  4 +--
> > >  drivers/clk/rockchip/clk_rv1126.c        | 52 +++++++++++++--------------
> > >  drivers/clk/sifive/sifive-prci.c         |  8 ++---
> > >  drivers/clk/sophgo/clk-cv1800b.c         |  2 +-
> > >  drivers/clk/starfive/clk-jh7110-pll.c    |  2 +-
> > >  drivers/clk/stm32/clk-stm32-core.c       |  4 +--
> > >  drivers/clk/stm32/clk-stm32f.c           |  6 ++--
> > >  drivers/clk/stm32/clk-stm32h7.c          |  4 +--
> > >  drivers/clk/tegra/tegra-car-clk.c        |  2 +-
> > >  drivers/clk/tegra/tegra186-clk.c         |  2 +-
> > >  drivers/clk/thead/clk-th1520-ap.c        |  2 +-
> > >  drivers/clk/ti/clk-am3-dpll-x2.c         |  4 +--
> > >  drivers/clk/ti/clk-divider.c             |  4 +--
> > >  drivers/clk/ti/clk-mux.c                 |  2 +-
> > >  drivers/clk/ti/clk-sci.c                 |  2 +-
> > >  drivers/clk/uniphier/clk-uniphier-core.c |  2 +-
> > >  65 files changed, 290 insertions(+), 290 deletions(-)
> > > ---
> > > base-commit: ecdc3872a767fb045be3296d4317ae978a14b022
> > > change-id: 20251010-clk_ops-3b7cc9ccd070
> > >
> > > Best regards,
> > > --
> > > Andrew Goodbody <andrew.goodbody@linaro.org>
> > >
> >
> > If you don't return an error, we cannot tell if the operation
> > succeeded, or not. U-Boot needs to be deterministic and we need to be
> > able to debug errors and detect them at runtime.
> >
> > We use ulong for the return value as a bit of a compromise, since it
> > is inefficient to use 64-bit on a 32-bit machine. Ideally it would be
> > long, but some clock rates are 3GHz and it would be confusing to cast
> > to ulong before using the value.
> >
> > An alternative we discussed was to return an integer error with the
> > clock rate returned in a parameter, but that seemed less efficient.
> >
> > With 64-bit machines, there really isn't a problem. Just checking for
> > a negative value is good enough, since the clock rate isn't going to
> > be 9 exahertz(?). Values between -CONFIG_ERR_PTR_OFFSET and 0 are
> > errors and are defined to be so.
> >
> > If you want clk_get_rate() to work like Linux (suppress / ignore
> > errors?), that's fine, but please create a clk_get_rate_err() (or
> > similar) which actually returns the correct error, and keep the error
> > return on the uclass interface. It is not uncommon to have the uclass
> > do some processing on values passed to/from driver. This allows people
> > who care to obtain the error.
>
> This is moving things in the right direction of having the error
> reporting and handling done where it can be done correctly. If there's
> further parts of the Linux kernel-like API we need, we can take those
> next.
>
> --
> Tom

Re: [PATCH 00/24] clk: Remove passing of negative errors through unsigned return

[Simon Glass]

Hi Tom, Andrew,

On Sat, 18 Oct 2025 at 15:04, Tom Rini <trini@konsulko.com> wrote:
>
> On Sat, Oct 18, 2025 at 09:34:42AM +0100, Simon Glass wrote:
> > Hi Andrew,
> >
> > On Wed, 15 Oct 2025 at 15:32, Andrew Goodbody
> > <andrew.goodbody@linaro.org> wrote:
> > >
> > > This series removes the passing of negative errors through the .get_rate
> > > function in the clk_ops struct. This function returns an unsigned long.
> > > The only value guaranteed to not be a valid clock rate is 0. This will
> > > also bring the drivers more in sync with Linux to allow for easier code
> > > porting and other maintenance in the future.
> > > Another series will address the calling of clk_get_rate and associated
> > > error handling.
> >
> > Some indication of the problem you ran into would be useful here.
>
> The problem statement is in the paragraph you're quoting. The numerical
> value of -ENOENT is a valid clock rate.

No, I mean a problem with a board, or something like that. We are
talking here about not being able to return a valid clock rate between
4294967040 and 4294967295, which is only even a theoretical problem on
32-bit machines. So I think it is reasonable to include a motivation.


>
> > > Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
> > > ---
> > > Andrew Goodbody (24):
> > >       clk: meson: Remove negative error returns from clk_get_rate
> > >       clk: sifive: Remove negative error returns from clk_get_rate
> > >       clk: armada-37xx: Remove negative error returns from clk_get_rate
> > >       clk: thead: th1520-ap: Remove negative error returns from clk_get_rate
> > >       clk: ccf: Remove negative error returns from clk_get_rate
> > >       clk: at91: Remove negative error returns from clk_get_rate
> > >       clk: renesas: Remove negative error returns from clk_get_rate
> > >       clk: rockchip: Remove negative error returns from clk_get_rate
> > >       clk: Remove negative error returns from clk_get_rate
> > >       clk: starfive: Remove negative error returns from clk_get_rate
> > >       clk: altera: Remove negative error returns from clk_get_rate
> > >       clk: uniphier: Remove negative error returns from clk_get_rate
> > >       clk: aspeed: Remove negative error returns from clk_get_rate
> > >       clk: nuvoton: Remove negative error returns from clk_get_rate
> > >       clk: exynos: Remove negative error returns from clk_get_rate
> > >       clk: imx: Remove negative error returns from clk_get_rate
> > >       clk: ti: Remove negative error returns from clk_get_rate
> > >       clk: mediatek: Remove negative error returns from clk_get_rate
> > >       clk: owl: Remove negative error returns from clk_get_rate
> > >       clk: tegra: Remove negative error returns from clk_get_rate
> > >       clk: adi: Remove negative error returns from clk_get_rate
> > >       clk: sophgo: Remove negative error returns from clk_get_rate
> > >       clk: stm32: Remove negative error returns from clk_get_rate
> > >       clk: x86: Remove negative error returns from clk_get_rate
> > >
> > >  drivers/clk/adi/clk-shared.c             |  2 +-
> > >  drivers/clk/altera/clk-agilex.c          |  2 +-
> > >  drivers/clk/altera/clk-agilex5.c         |  2 +-
> > >  drivers/clk/altera/clk-n5x.c             |  2 +-
> > >  drivers/clk/aspeed/clk_ast2500.c         |  2 +-
> > >  drivers/clk/aspeed/clk_ast2600.c         |  2 +-
> > >  drivers/clk/at91/compat.c                |  6 ++--
> > >  drivers/clk/clk-hsdk-cgu.c               |  2 +-
> > >  drivers/clk/clk-uclass.c                 |  4 +--
> > >  drivers/clk/clk.c                        |  2 +-
> > >  drivers/clk/clk_fixed_factor.c           |  4 +--
> > >  drivers/clk/clk_k210.c                   |  6 ++--
> > >  drivers/clk/clk_sandbox.c                |  4 +--
> > >  drivers/clk/clk_scmi.c                   |  4 +--
> > >  drivers/clk/clk_vexpress_osc.c           |  2 +-
> > >  drivers/clk/clk_zynq.c                   |  4 +--
> > >  drivers/clk/clk_zynqmp.c                 | 40 ++++++++++-----------
> > >  drivers/clk/exynos/clk-exynos7420.c      |  2 +-
> > >  drivers/clk/imx/clk-imx8qm.c             |  6 ++--
> > >  drivers/clk/imx/clk-imx8qxp.c            |  6 ++--
> > >  drivers/clk/imx/clk-imxrt1170.c          |  2 +-
> > >  drivers/clk/imx/clk-pllv3.c              |  2 +-
> > >  drivers/clk/intel/clk_intel.c            |  2 +-
> > >  drivers/clk/mediatek/clk-mtk.c           |  2 +-
> > >  drivers/clk/meson/a1.c                   | 10 +++---
> > >  drivers/clk/meson/axg.c                  | 10 +++---
> > >  drivers/clk/meson/g12a.c                 | 36 +++++++++----------
> > >  drivers/clk/meson/gxbb.c                 | 20 +++++------
> > >  drivers/clk/mvebu/armada-37xx-periph.c   |  2 +-
> > >  drivers/clk/mvebu/armada-37xx-tbg.c      |  2 +-
> > >  drivers/clk/nuvoton/clk_npcm.c           | 10 +++---
> > >  drivers/clk/owl/clk_owl.c                |  2 +-
> > >  drivers/clk/renesas/clk-rcar-gen2.c      |  8 ++---
> > >  drivers/clk/renesas/rzg2l-cpg.c          |  8 ++---
> > >  drivers/clk/rockchip/clk_px30.c          | 24 ++++++-------
> > >  drivers/clk/rockchip/clk_rk3036.c        |  2 +-
> > >  drivers/clk/rockchip/clk_rk3066.c        |  8 ++---
> > >  drivers/clk/rockchip/clk_rk3128.c        |  6 ++--
> > >  drivers/clk/rockchip/clk_rk3188.c        |  6 ++--
> > >  drivers/clk/rockchip/clk_rk322x.c        |  4 +--
> > >  drivers/clk/rockchip/clk_rk3288.c        |  6 ++--
> > >  drivers/clk/rockchip/clk_rk3308.c        | 26 +++++++-------
> > >  drivers/clk/rockchip/clk_rk3328.c        |  6 ++--
> > >  drivers/clk/rockchip/clk_rk3368.c        |  8 ++---
> > >  drivers/clk/rockchip/clk_rk3399.c        | 12 +++----
> > >  drivers/clk/rockchip/clk_rk3528.c        | 20 +++++------
> > >  drivers/clk/rockchip/clk_rk3568.c        | 62 ++++++++++++++++----------------
> > >  drivers/clk/rockchip/clk_rk3576.c        | 36 +++++++++----------
> > >  drivers/clk/rockchip/clk_rk3588.c        | 32 ++++++++---------
> > >  drivers/clk/rockchip/clk_rv1108.c        |  4 +--
> > >  drivers/clk/rockchip/clk_rv1126.c        | 52 +++++++++++++--------------
> > >  drivers/clk/sifive/sifive-prci.c         |  8 ++---
> > >  drivers/clk/sophgo/clk-cv1800b.c         |  2 +-
> > >  drivers/clk/starfive/clk-jh7110-pll.c    |  2 +-
> > >  drivers/clk/stm32/clk-stm32-core.c       |  4 +--
> > >  drivers/clk/stm32/clk-stm32f.c           |  6 ++--
> > >  drivers/clk/stm32/clk-stm32h7.c          |  4 +--
> > >  drivers/clk/tegra/tegra-car-clk.c        |  2 +-
> > >  drivers/clk/tegra/tegra186-clk.c         |  2 +-
> > >  drivers/clk/thead/clk-th1520-ap.c        |  2 +-
> > >  drivers/clk/ti/clk-am3-dpll-x2.c         |  4 +--
> > >  drivers/clk/ti/clk-divider.c             |  4 +--
> > >  drivers/clk/ti/clk-mux.c                 |  2 +-
> > >  drivers/clk/ti/clk-sci.c                 |  2 +-
> > >  drivers/clk/uniphier/clk-uniphier-core.c |  2 +-
> > >  65 files changed, 290 insertions(+), 290 deletions(-)
> > > ---
> > > base-commit: ecdc3872a767fb045be3296d4317ae978a14b022
> > > change-id: 20251010-clk_ops-3b7cc9ccd070
> > >
> > > Best regards,
> > > --
> > > Andrew Goodbody <andrew.goodbody@linaro.org>
> > >
> >
> > If you don't return an error, we cannot tell if the operation
> > succeeded, or not. U-Boot needs to be deterministic and we need to be
> > able to debug errors and detect them at runtime.
> >
> > We use ulong for the return value as a bit of a compromise, since it
> > is inefficient to use 64-bit on a 32-bit machine. Ideally it would be
> > long, but some clock rates are 3GHz and it would be confusing to cast
> > to ulong before using the value.
> >
> > An alternative we discussed was to return an integer error with the
> > clock rate returned in a parameter, but that seemed less efficient.
> >
> > With 64-bit machines, there really isn't a problem. Just checking for
> > a negative value is good enough, since the clock rate isn't going to
> > be 9 exahertz(?). Values between -CONFIG_ERR_PTR_OFFSET and 0 are
> > errors and are defined to be so.
> >
> > If you want clk_get_rate() to work like Linux (suppress / ignore
> > errors?), that's fine, but please create a clk_get_rate_err() (or
> > similar) which actually returns the correct error, and keep the error
> > return on the uclass interface. It is not uncommon to have the uclass
> > do some processing on values passed to/from driver. This allows people
> > who care to obtain the error.
>
> This is moving things in the right direction of having the error
> reporting and handling done where it can be done correctly. If there's
> further parts of the Linux kernel-like API we need, we can take those
> next.

Here is part of the patch:

--- a/drivers/clk/meson/a1.c
+++ b/drivers/clk/meson/a1.c
@@ -359,7 +359,7 @@ static ulong meson_div_get_rate(struct clk *clk,
unsigned long id)

        info = meson_clk_get_info(clk, id, MESON_CLK_DIV);
        if (IS_ERR(info))
-               return PTR_ERR(info);
+               return 0;

I don't see anything in that fragment other than just ignoring errors.

Please, put this handling in the uclass function.

Regards,
Simon

Re: [PATCH 00/24] clk: Remove passing of negative errors through unsigned return

[Svyatoslav Ryhel]

нд, 19 жовт. 2025 р. о 16:05 Simon Glass <sjg@chromium.org> пише:
>
> Hi Tom, Andrew,
>
> On Sat, 18 Oct 2025 at 15:04, Tom Rini <trini@konsulko.com> wrote:
> >
> > On Sat, Oct 18, 2025 at 09:34:42AM +0100, Simon Glass wrote:
> > > Hi Andrew,
> > >
> > > On Wed, 15 Oct 2025 at 15:32, Andrew Goodbody
> > > <andrew.goodbody@linaro.org> wrote:
> > > >
> > > > This series removes the passing of negative errors through the .get_rate
> > > > function in the clk_ops struct. This function returns an unsigned long.
> > > > The only value guaranteed to not be a valid clock rate is 0. This will
> > > > also bring the drivers more in sync with Linux to allow for easier code
> > > > porting and other maintenance in the future.
> > > > Another series will address the calling of clk_get_rate and associated
> > > > error handling.
> > >
> > > Some indication of the problem you ran into would be useful here.
> >
> > The problem statement is in the paragraph you're quoting. The numerical
> > value of -ENOENT is a valid clock rate.
>
> No, I mean a problem with a board, or something like that. We are
> talking here about not being able to return a valid clock rate between
> 4294967040 and 4294967295, which is only even a theoretical problem on
> 32-bit machines. So I think it is reasonable to include a motivation.
>
>
> >
> > > > Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
> > > > ---
> > > > Andrew Goodbody (24):
> > > >       clk: meson: Remove negative error returns from clk_get_rate
> > > >       clk: sifive: Remove negative error returns from clk_get_rate
> > > >       clk: armada-37xx: Remove negative error returns from clk_get_rate
> > > >       clk: thead: th1520-ap: Remove negative error returns from clk_get_rate
> > > >       clk: ccf: Remove negative error returns from clk_get_rate
> > > >       clk: at91: Remove negative error returns from clk_get_rate
> > > >       clk: renesas: Remove negative error returns from clk_get_rate
> > > >       clk: rockchip: Remove negative error returns from clk_get_rate
> > > >       clk: Remove negative error returns from clk_get_rate
> > > >       clk: starfive: Remove negative error returns from clk_get_rate
> > > >       clk: altera: Remove negative error returns from clk_get_rate
> > > >       clk: uniphier: Remove negative error returns from clk_get_rate
> > > >       clk: aspeed: Remove negative error returns from clk_get_rate
> > > >       clk: nuvoton: Remove negative error returns from clk_get_rate
> > > >       clk: exynos: Remove negative error returns from clk_get_rate
> > > >       clk: imx: Remove negative error returns from clk_get_rate
> > > >       clk: ti: Remove negative error returns from clk_get_rate
> > > >       clk: mediatek: Remove negative error returns from clk_get_rate
> > > >       clk: owl: Remove negative error returns from clk_get_rate
> > > >       clk: tegra: Remove negative error returns from clk_get_rate
> > > >       clk: adi: Remove negative error returns from clk_get_rate
> > > >       clk: sophgo: Remove negative error returns from clk_get_rate
> > > >       clk: stm32: Remove negative error returns from clk_get_rate
> > > >       clk: x86: Remove negative error returns from clk_get_rate
> > > >
> > > >  drivers/clk/adi/clk-shared.c             |  2 +-
> > > >  drivers/clk/altera/clk-agilex.c          |  2 +-
> > > >  drivers/clk/altera/clk-agilex5.c         |  2 +-
> > > >  drivers/clk/altera/clk-n5x.c             |  2 +-
> > > >  drivers/clk/aspeed/clk_ast2500.c         |  2 +-
> > > >  drivers/clk/aspeed/clk_ast2600.c         |  2 +-
> > > >  drivers/clk/at91/compat.c                |  6 ++--
> > > >  drivers/clk/clk-hsdk-cgu.c               |  2 +-
> > > >  drivers/clk/clk-uclass.c                 |  4 +--
> > > >  drivers/clk/clk.c                        |  2 +-
> > > >  drivers/clk/clk_fixed_factor.c           |  4 +--
> > > >  drivers/clk/clk_k210.c                   |  6 ++--
> > > >  drivers/clk/clk_sandbox.c                |  4 +--
> > > >  drivers/clk/clk_scmi.c                   |  4 +--
> > > >  drivers/clk/clk_vexpress_osc.c           |  2 +-
> > > >  drivers/clk/clk_zynq.c                   |  4 +--
> > > >  drivers/clk/clk_zynqmp.c                 | 40 ++++++++++-----------
> > > >  drivers/clk/exynos/clk-exynos7420.c      |  2 +-
> > > >  drivers/clk/imx/clk-imx8qm.c             |  6 ++--
> > > >  drivers/clk/imx/clk-imx8qxp.c            |  6 ++--
> > > >  drivers/clk/imx/clk-imxrt1170.c          |  2 +-
> > > >  drivers/clk/imx/clk-pllv3.c              |  2 +-
> > > >  drivers/clk/intel/clk_intel.c            |  2 +-
> > > >  drivers/clk/mediatek/clk-mtk.c           |  2 +-
> > > >  drivers/clk/meson/a1.c                   | 10 +++---
> > > >  drivers/clk/meson/axg.c                  | 10 +++---
> > > >  drivers/clk/meson/g12a.c                 | 36 +++++++++----------
> > > >  drivers/clk/meson/gxbb.c                 | 20 +++++------
> > > >  drivers/clk/mvebu/armada-37xx-periph.c   |  2 +-
> > > >  drivers/clk/mvebu/armada-37xx-tbg.c      |  2 +-
> > > >  drivers/clk/nuvoton/clk_npcm.c           | 10 +++---
> > > >  drivers/clk/owl/clk_owl.c                |  2 +-
> > > >  drivers/clk/renesas/clk-rcar-gen2.c      |  8 ++---
> > > >  drivers/clk/renesas/rzg2l-cpg.c          |  8 ++---
> > > >  drivers/clk/rockchip/clk_px30.c          | 24 ++++++-------
> > > >  drivers/clk/rockchip/clk_rk3036.c        |  2 +-
> > > >  drivers/clk/rockchip/clk_rk3066.c        |  8 ++---
> > > >  drivers/clk/rockchip/clk_rk3128.c        |  6 ++--
> > > >  drivers/clk/rockchip/clk_rk3188.c        |  6 ++--
> > > >  drivers/clk/rockchip/clk_rk322x.c        |  4 +--
> > > >  drivers/clk/rockchip/clk_rk3288.c        |  6 ++--
> > > >  drivers/clk/rockchip/clk_rk3308.c        | 26 +++++++-------
> > > >  drivers/clk/rockchip/clk_rk3328.c        |  6 ++--
> > > >  drivers/clk/rockchip/clk_rk3368.c        |  8 ++---
> > > >  drivers/clk/rockchip/clk_rk3399.c        | 12 +++----
> > > >  drivers/clk/rockchip/clk_rk3528.c        | 20 +++++------
> > > >  drivers/clk/rockchip/clk_rk3568.c        | 62 ++++++++++++++++----------------
> > > >  drivers/clk/rockchip/clk_rk3576.c        | 36 +++++++++----------
> > > >  drivers/clk/rockchip/clk_rk3588.c        | 32 ++++++++---------
> > > >  drivers/clk/rockchip/clk_rv1108.c        |  4 +--
> > > >  drivers/clk/rockchip/clk_rv1126.c        | 52 +++++++++++++--------------
> > > >  drivers/clk/sifive/sifive-prci.c         |  8 ++---
> > > >  drivers/clk/sophgo/clk-cv1800b.c         |  2 +-
> > > >  drivers/clk/starfive/clk-jh7110-pll.c    |  2 +-
> > > >  drivers/clk/stm32/clk-stm32-core.c       |  4 +--
> > > >  drivers/clk/stm32/clk-stm32f.c           |  6 ++--
> > > >  drivers/clk/stm32/clk-stm32h7.c          |  4 +--
> > > >  drivers/clk/tegra/tegra-car-clk.c        |  2 +-
> > > >  drivers/clk/tegra/tegra186-clk.c         |  2 +-
> > > >  drivers/clk/thead/clk-th1520-ap.c        |  2 +-
> > > >  drivers/clk/ti/clk-am3-dpll-x2.c         |  4 +--
> > > >  drivers/clk/ti/clk-divider.c             |  4 +--
> > > >  drivers/clk/ti/clk-mux.c                 |  2 +-
> > > >  drivers/clk/ti/clk-sci.c                 |  2 +-
> > > >  drivers/clk/uniphier/clk-uniphier-core.c |  2 +-
> > > >  65 files changed, 290 insertions(+), 290 deletions(-)
> > > > ---
> > > > base-commit: ecdc3872a767fb045be3296d4317ae978a14b022
> > > > change-id: 20251010-clk_ops-3b7cc9ccd070
> > > >
> > > > Best regards,
> > > > --
> > > > Andrew Goodbody <andrew.goodbody@linaro.org>
> > > >
> > >
> > > If you don't return an error, we cannot tell if the operation
> > > succeeded, or not. U-Boot needs to be deterministic and we need to be
> > > able to debug errors and detect them at runtime.
> > >
> > > We use ulong for the return value as a bit of a compromise, since it
> > > is inefficient to use 64-bit on a 32-bit machine. Ideally it would be
> > > long, but some clock rates are 3GHz and it would be confusing to cast
> > > to ulong before using the value.
> > >
> > > An alternative we discussed was to return an integer error with the
> > > clock rate returned in a parameter, but that seemed less efficient.
> > >
> > > With 64-bit machines, there really isn't a problem. Just checking for
> > > a negative value is good enough, since the clock rate isn't going to
> > > be 9 exahertz(?). Values between -CONFIG_ERR_PTR_OFFSET and 0 are
> > > errors and are defined to be so.
> > >
> > > If you want clk_get_rate() to work like Linux (suppress / ignore
> > > errors?), that's fine, but please create a clk_get_rate_err() (or
> > > similar) which actually returns the correct error, and keep the error
> > > return on the uclass interface. It is not uncommon to have the uclass
> > > do some processing on values passed to/from driver. This allows people
> > > who care to obtain the error.
> >
> > This is moving things in the right direction of having the error
> > reporting and handling done where it can be done correctly. If there's
> > further parts of the Linux kernel-like API we need, we can take those
> > next.
>
> Here is part of the patch:
>
> --- a/drivers/clk/meson/a1.c
> +++ b/drivers/clk/meson/a1.c
> @@ -359,7 +359,7 @@ static ulong meson_div_get_rate(struct clk *clk,
> unsigned long id)
>
>         info = meson_clk_get_info(clk, id, MESON_CLK_DIV);
>         if (IS_ERR(info))
> -               return PTR_ERR(info);
> +               return 0;
>
> I don't see anything in that fragment other than just ignoring errors.
>

I agree with Simon. This patchset may cause a lot of problems for all
boards it changes in case clk ops fail, since it silences all error
returns. Any clock error will be untrackable unless you know where and
what to look specifically.

> Please, put this handling in the uclass function.
>
> Regards,
> Simon

Re: [PATCH 00/24] clk: Remove passing of negative errors through unsigned return

[Tom Rini]

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On Sun, Oct 19, 2025 at 04:45:24PM +0300, Svyatoslav Ryhel wrote:
> нд, 19 жовт. 2025 р. о 16:05 Simon Glass <sjg@chromium.org> пише:
> >
> > Hi Tom, Andrew,
> >
> > On Sat, 18 Oct 2025 at 15:04, Tom Rini <trini@konsulko.com> wrote:
> > >
> > > On Sat, Oct 18, 2025 at 09:34:42AM +0100, Simon Glass wrote:
> > > > Hi Andrew,
> > > >
> > > > On Wed, 15 Oct 2025 at 15:32, Andrew Goodbody
> > > > <andrew.goodbody@linaro.org> wrote:
> > > > >
> > > > > This series removes the passing of negative errors through the .get_rate
> > > > > function in the clk_ops struct. This function returns an unsigned long.
> > > > > The only value guaranteed to not be a valid clock rate is 0. This will
> > > > > also bring the drivers more in sync with Linux to allow for easier code
> > > > > porting and other maintenance in the future.
> > > > > Another series will address the calling of clk_get_rate and associated
> > > > > error handling.
> > > >
> > > > Some indication of the problem you ran into would be useful here.
> > >
> > > The problem statement is in the paragraph you're quoting. The numerical
> > > value of -ENOENT is a valid clock rate.
> >
> > No, I mean a problem with a board, or something like that. We are
> > talking here about not being able to return a valid clock rate between
> > 4294967040 and 4294967295, which is only even a theoretical problem on
> > 32-bit machines. So I think it is reasonable to include a motivation.
> >
> >
> > >
> > > > > Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
> > > > > ---
> > > > > Andrew Goodbody (24):
> > > > >       clk: meson: Remove negative error returns from clk_get_rate
> > > > >       clk: sifive: Remove negative error returns from clk_get_rate
> > > > >       clk: armada-37xx: Remove negative error returns from clk_get_rate
> > > > >       clk: thead: th1520-ap: Remove negative error returns from clk_get_rate
> > > > >       clk: ccf: Remove negative error returns from clk_get_rate
> > > > >       clk: at91: Remove negative error returns from clk_get_rate
> > > > >       clk: renesas: Remove negative error returns from clk_get_rate
> > > > >       clk: rockchip: Remove negative error returns from clk_get_rate
> > > > >       clk: Remove negative error returns from clk_get_rate
> > > > >       clk: starfive: Remove negative error returns from clk_get_rate
> > > > >       clk: altera: Remove negative error returns from clk_get_rate
> > > > >       clk: uniphier: Remove negative error returns from clk_get_rate
> > > > >       clk: aspeed: Remove negative error returns from clk_get_rate
> > > > >       clk: nuvoton: Remove negative error returns from clk_get_rate
> > > > >       clk: exynos: Remove negative error returns from clk_get_rate
> > > > >       clk: imx: Remove negative error returns from clk_get_rate
> > > > >       clk: ti: Remove negative error returns from clk_get_rate
> > > > >       clk: mediatek: Remove negative error returns from clk_get_rate
> > > > >       clk: owl: Remove negative error returns from clk_get_rate
> > > > >       clk: tegra: Remove negative error returns from clk_get_rate
> > > > >       clk: adi: Remove negative error returns from clk_get_rate
> > > > >       clk: sophgo: Remove negative error returns from clk_get_rate
> > > > >       clk: stm32: Remove negative error returns from clk_get_rate
> > > > >       clk: x86: Remove negative error returns from clk_get_rate
> > > > >
> > > > >  drivers/clk/adi/clk-shared.c             |  2 +-
> > > > >  drivers/clk/altera/clk-agilex.c          |  2 +-
> > > > >  drivers/clk/altera/clk-agilex5.c         |  2 +-
> > > > >  drivers/clk/altera/clk-n5x.c             |  2 +-
> > > > >  drivers/clk/aspeed/clk_ast2500.c         |  2 +-
> > > > >  drivers/clk/aspeed/clk_ast2600.c         |  2 +-
> > > > >  drivers/clk/at91/compat.c                |  6 ++--
> > > > >  drivers/clk/clk-hsdk-cgu.c               |  2 +-
> > > > >  drivers/clk/clk-uclass.c                 |  4 +--
> > > > >  drivers/clk/clk.c                        |  2 +-
> > > > >  drivers/clk/clk_fixed_factor.c           |  4 +--
> > > > >  drivers/clk/clk_k210.c                   |  6 ++--
> > > > >  drivers/clk/clk_sandbox.c                |  4 +--
> > > > >  drivers/clk/clk_scmi.c                   |  4 +--
> > > > >  drivers/clk/clk_vexpress_osc.c           |  2 +-
> > > > >  drivers/clk/clk_zynq.c                   |  4 +--
> > > > >  drivers/clk/clk_zynqmp.c                 | 40 ++++++++++-----------
> > > > >  drivers/clk/exynos/clk-exynos7420.c      |  2 +-
> > > > >  drivers/clk/imx/clk-imx8qm.c             |  6 ++--
> > > > >  drivers/clk/imx/clk-imx8qxp.c            |  6 ++--
> > > > >  drivers/clk/imx/clk-imxrt1170.c          |  2 +-
> > > > >  drivers/clk/imx/clk-pllv3.c              |  2 +-
> > > > >  drivers/clk/intel/clk_intel.c            |  2 +-
> > > > >  drivers/clk/mediatek/clk-mtk.c           |  2 +-
> > > > >  drivers/clk/meson/a1.c                   | 10 +++---
> > > > >  drivers/clk/meson/axg.c                  | 10 +++---
> > > > >  drivers/clk/meson/g12a.c                 | 36 +++++++++----------
> > > > >  drivers/clk/meson/gxbb.c                 | 20 +++++------
> > > > >  drivers/clk/mvebu/armada-37xx-periph.c   |  2 +-
> > > > >  drivers/clk/mvebu/armada-37xx-tbg.c      |  2 +-
> > > > >  drivers/clk/nuvoton/clk_npcm.c           | 10 +++---
> > > > >  drivers/clk/owl/clk_owl.c                |  2 +-
> > > > >  drivers/clk/renesas/clk-rcar-gen2.c      |  8 ++---
> > > > >  drivers/clk/renesas/rzg2l-cpg.c          |  8 ++---
> > > > >  drivers/clk/rockchip/clk_px30.c          | 24 ++++++-------
> > > > >  drivers/clk/rockchip/clk_rk3036.c        |  2 +-
> > > > >  drivers/clk/rockchip/clk_rk3066.c        |  8 ++---
> > > > >  drivers/clk/rockchip/clk_rk3128.c        |  6 ++--
> > > > >  drivers/clk/rockchip/clk_rk3188.c        |  6 ++--
> > > > >  drivers/clk/rockchip/clk_rk322x.c        |  4 +--
> > > > >  drivers/clk/rockchip/clk_rk3288.c        |  6 ++--
> > > > >  drivers/clk/rockchip/clk_rk3308.c        | 26 +++++++-------
> > > > >  drivers/clk/rockchip/clk_rk3328.c        |  6 ++--
> > > > >  drivers/clk/rockchip/clk_rk3368.c        |  8 ++---
> > > > >  drivers/clk/rockchip/clk_rk3399.c        | 12 +++----
> > > > >  drivers/clk/rockchip/clk_rk3528.c        | 20 +++++------
> > > > >  drivers/clk/rockchip/clk_rk3568.c        | 62 ++++++++++++++++----------------
> > > > >  drivers/clk/rockchip/clk_rk3576.c        | 36 +++++++++----------
> > > > >  drivers/clk/rockchip/clk_rk3588.c        | 32 ++++++++---------
> > > > >  drivers/clk/rockchip/clk_rv1108.c        |  4 +--
> > > > >  drivers/clk/rockchip/clk_rv1126.c        | 52 +++++++++++++--------------
> > > > >  drivers/clk/sifive/sifive-prci.c         |  8 ++---
> > > > >  drivers/clk/sophgo/clk-cv1800b.c         |  2 +-
> > > > >  drivers/clk/starfive/clk-jh7110-pll.c    |  2 +-
> > > > >  drivers/clk/stm32/clk-stm32-core.c       |  4 +--
> > > > >  drivers/clk/stm32/clk-stm32f.c           |  6 ++--
> > > > >  drivers/clk/stm32/clk-stm32h7.c          |  4 +--
> > > > >  drivers/clk/tegra/tegra-car-clk.c        |  2 +-
> > > > >  drivers/clk/tegra/tegra186-clk.c         |  2 +-
> > > > >  drivers/clk/thead/clk-th1520-ap.c        |  2 +-
> > > > >  drivers/clk/ti/clk-am3-dpll-x2.c         |  4 +--
> > > > >  drivers/clk/ti/clk-divider.c             |  4 +--
> > > > >  drivers/clk/ti/clk-mux.c                 |  2 +-
> > > > >  drivers/clk/ti/clk-sci.c                 |  2 +-
> > > > >  drivers/clk/uniphier/clk-uniphier-core.c |  2 +-
> > > > >  65 files changed, 290 insertions(+), 290 deletions(-)
> > > > > ---
> > > > > base-commit: ecdc3872a767fb045be3296d4317ae978a14b022
> > > > > change-id: 20251010-clk_ops-3b7cc9ccd070
> > > > >
> > > > > Best regards,
> > > > > --
> > > > > Andrew Goodbody <andrew.goodbody@linaro.org>
> > > > >
> > > >
> > > > If you don't return an error, we cannot tell if the operation
> > > > succeeded, or not. U-Boot needs to be deterministic and we need to be
> > > > able to debug errors and detect them at runtime.
> > > >
> > > > We use ulong for the return value as a bit of a compromise, since it
> > > > is inefficient to use 64-bit on a 32-bit machine. Ideally it would be
> > > > long, but some clock rates are 3GHz and it would be confusing to cast
> > > > to ulong before using the value.
> > > >
> > > > An alternative we discussed was to return an integer error with the
> > > > clock rate returned in a parameter, but that seemed less efficient.
> > > >
> > > > With 64-bit machines, there really isn't a problem. Just checking for
> > > > a negative value is good enough, since the clock rate isn't going to
> > > > be 9 exahertz(?). Values between -CONFIG_ERR_PTR_OFFSET and 0 are
> > > > errors and are defined to be so.
> > > >
> > > > If you want clk_get_rate() to work like Linux (suppress / ignore
> > > > errors?), that's fine, but please create a clk_get_rate_err() (or
> > > > similar) which actually returns the correct error, and keep the error
> > > > return on the uclass interface. It is not uncommon to have the uclass
> > > > do some processing on values passed to/from driver. This allows people
> > > > who care to obtain the error.
> > >
> > > This is moving things in the right direction of having the error
> > > reporting and handling done where it can be done correctly. If there's
> > > further parts of the Linux kernel-like API we need, we can take those
> > > next.
> >
> > Here is part of the patch:
> >
> > --- a/drivers/clk/meson/a1.c
> > +++ b/drivers/clk/meson/a1.c
> > @@ -359,7 +359,7 @@ static ulong meson_div_get_rate(struct clk *clk,
> > unsigned long id)
> >
> >         info = meson_clk_get_info(clk, id, MESON_CLK_DIV);
> >         if (IS_ERR(info))
> > -               return PTR_ERR(info);
> > +               return 0;
> >
> > I don't see anything in that fragment other than just ignoring errors.
> >
> 
> I agree with Simon. This patchset may cause a lot of problems for all
> boards it changes in case clk ops fail, since it silences all error
> returns. Any clock error will be untrackable unless you know where and
> what to look specifically.

I think it's worth going back to the original thread:
https://lore.kernel.org/u-boot/f5c94319-8ef8-459d-88b2-836702779cfb@linaro.org/

As part of the problem is that what we have today does not work. This is
why I'm think it's OK to first return 0, always, as the invalid clock
rate and then re-introduce error checking that can work.

-- 
Tom

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Re: [PATCH 00/24] clk: Remove passing of negative errors through unsigned return

[Simon Glass]

Hi Tom,

On Sun, 19 Oct 2025 at 17:21, Tom Rini <trini@konsulko.com> wrote:
>
> On Sun, Oct 19, 2025 at 04:45:24PM +0300, Svyatoslav Ryhel wrote:
> > нд, 19 жовт. 2025 р. о 16:05 Simon Glass <sjg@chromium.org> пише:
> > >
> > > Hi Tom, Andrew,
> > >
> > > On Sat, 18 Oct 2025 at 15:04, Tom Rini <trini@konsulko.com> wrote:
> > > >
> > > > On Sat, Oct 18, 2025 at 09:34:42AM +0100, Simon Glass wrote:
> > > > > Hi Andrew,
> > > > >
> > > > > On Wed, 15 Oct 2025 at 15:32, Andrew Goodbody
> > > > > <andrew.goodbody@linaro.org> wrote:
> > > > > >
> > > > > > This series removes the passing of negative errors through the .get_rate
> > > > > > function in the clk_ops struct. This function returns an unsigned long.
> > > > > > The only value guaranteed to not be a valid clock rate is 0. This will
> > > > > > also bring the drivers more in sync with Linux to allow for easier code
> > > > > > porting and other maintenance in the future.
> > > > > > Another series will address the calling of clk_get_rate and associated
> > > > > > error handling.
> > > > >
> > > > > Some indication of the problem you ran into would be useful here.
> > > >
> > > > The problem statement is in the paragraph you're quoting. The numerical
> > > > value of -ENOENT is a valid clock rate.
> > >
> > > No, I mean a problem with a board, or something like that. We are
> > > talking here about not being able to return a valid clock rate between
> > > 4294967040 and 4294967295, which is only even a theoretical problem on
> > > 32-bit machines. So I think it is reasonable to include a motivation.
> > >
> > >
> > > >
> > > > > > Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
> > > > > > ---
> > > > > > Andrew Goodbody (24):
> > > > > >       clk: meson: Remove negative error returns from clk_get_rate
> > > > > >       clk: sifive: Remove negative error returns from clk_get_rate
> > > > > >       clk: armada-37xx: Remove negative error returns from clk_get_rate
> > > > > >       clk: thead: th1520-ap: Remove negative error returns from clk_get_rate
> > > > > >       clk: ccf: Remove negative error returns from clk_get_rate
> > > > > >       clk: at91: Remove negative error returns from clk_get_rate
> > > > > >       clk: renesas: Remove negative error returns from clk_get_rate
> > > > > >       clk: rockchip: Remove negative error returns from clk_get_rate
> > > > > >       clk: Remove negative error returns from clk_get_rate
> > > > > >       clk: starfive: Remove negative error returns from clk_get_rate
> > > > > >       clk: altera: Remove negative error returns from clk_get_rate
> > > > > >       clk: uniphier: Remove negative error returns from clk_get_rate
> > > > > >       clk: aspeed: Remove negative error returns from clk_get_rate
> > > > > >       clk: nuvoton: Remove negative error returns from clk_get_rate
> > > > > >       clk: exynos: Remove negative error returns from clk_get_rate
> > > > > >       clk: imx: Remove negative error returns from clk_get_rate
> > > > > >       clk: ti: Remove negative error returns from clk_get_rate
> > > > > >       clk: mediatek: Remove negative error returns from clk_get_rate
> > > > > >       clk: owl: Remove negative error returns from clk_get_rate
> > > > > >       clk: tegra: Remove negative error returns from clk_get_rate
> > > > > >       clk: adi: Remove negative error returns from clk_get_rate
> > > > > >       clk: sophgo: Remove negative error returns from clk_get_rate
> > > > > >       clk: stm32: Remove negative error returns from clk_get_rate
> > > > > >       clk: x86: Remove negative error returns from clk_get_rate
> > > > > >
> > > > > >  drivers/clk/adi/clk-shared.c             |  2 +-
> > > > > >  drivers/clk/altera/clk-agilex.c          |  2 +-
> > > > > >  drivers/clk/altera/clk-agilex5.c         |  2 +-
> > > > > >  drivers/clk/altera/clk-n5x.c             |  2 +-
> > > > > >  drivers/clk/aspeed/clk_ast2500.c         |  2 +-
> > > > > >  drivers/clk/aspeed/clk_ast2600.c         |  2 +-
> > > > > >  drivers/clk/at91/compat.c                |  6 ++--
> > > > > >  drivers/clk/clk-hsdk-cgu.c               |  2 +-
> > > > > >  drivers/clk/clk-uclass.c                 |  4 +--
> > > > > >  drivers/clk/clk.c                        |  2 +-
> > > > > >  drivers/clk/clk_fixed_factor.c           |  4 +--
> > > > > >  drivers/clk/clk_k210.c                   |  6 ++--
> > > > > >  drivers/clk/clk_sandbox.c                |  4 +--
> > > > > >  drivers/clk/clk_scmi.c                   |  4 +--
> > > > > >  drivers/clk/clk_vexpress_osc.c           |  2 +-
> > > > > >  drivers/clk/clk_zynq.c                   |  4 +--
> > > > > >  drivers/clk/clk_zynqmp.c                 | 40 ++++++++++-----------
> > > > > >  drivers/clk/exynos/clk-exynos7420.c      |  2 +-
> > > > > >  drivers/clk/imx/clk-imx8qm.c             |  6 ++--
> > > > > >  drivers/clk/imx/clk-imx8qxp.c            |  6 ++--
> > > > > >  drivers/clk/imx/clk-imxrt1170.c          |  2 +-
> > > > > >  drivers/clk/imx/clk-pllv3.c              |  2 +-
> > > > > >  drivers/clk/intel/clk_intel.c            |  2 +-
> > > > > >  drivers/clk/mediatek/clk-mtk.c           |  2 +-
> > > > > >  drivers/clk/meson/a1.c                   | 10 +++---
> > > > > >  drivers/clk/meson/axg.c                  | 10 +++---
> > > > > >  drivers/clk/meson/g12a.c                 | 36 +++++++++----------
> > > > > >  drivers/clk/meson/gxbb.c                 | 20 +++++------
> > > > > >  drivers/clk/mvebu/armada-37xx-periph.c   |  2 +-
> > > > > >  drivers/clk/mvebu/armada-37xx-tbg.c      |  2 +-
> > > > > >  drivers/clk/nuvoton/clk_npcm.c           | 10 +++---
> > > > > >  drivers/clk/owl/clk_owl.c                |  2 +-
> > > > > >  drivers/clk/renesas/clk-rcar-gen2.c      |  8 ++---
> > > > > >  drivers/clk/renesas/rzg2l-cpg.c          |  8 ++---
> > > > > >  drivers/clk/rockchip/clk_px30.c          | 24 ++++++-------
> > > > > >  drivers/clk/rockchip/clk_rk3036.c        |  2 +-
> > > > > >  drivers/clk/rockchip/clk_rk3066.c        |  8 ++---
> > > > > >  drivers/clk/rockchip/clk_rk3128.c        |  6 ++--
> > > > > >  drivers/clk/rockchip/clk_rk3188.c        |  6 ++--
> > > > > >  drivers/clk/rockchip/clk_rk322x.c        |  4 +--
> > > > > >  drivers/clk/rockchip/clk_rk3288.c        |  6 ++--
> > > > > >  drivers/clk/rockchip/clk_rk3308.c        | 26 +++++++-------
> > > > > >  drivers/clk/rockchip/clk_rk3328.c        |  6 ++--
> > > > > >  drivers/clk/rockchip/clk_rk3368.c        |  8 ++---
> > > > > >  drivers/clk/rockchip/clk_rk3399.c        | 12 +++----
> > > > > >  drivers/clk/rockchip/clk_rk3528.c        | 20 +++++------
> > > > > >  drivers/clk/rockchip/clk_rk3568.c        | 62 ++++++++++++++++----------------
> > > > > >  drivers/clk/rockchip/clk_rk3576.c        | 36 +++++++++----------
> > > > > >  drivers/clk/rockchip/clk_rk3588.c        | 32 ++++++++---------
> > > > > >  drivers/clk/rockchip/clk_rv1108.c        |  4 +--
> > > > > >  drivers/clk/rockchip/clk_rv1126.c        | 52 +++++++++++++--------------
> > > > > >  drivers/clk/sifive/sifive-prci.c         |  8 ++---
> > > > > >  drivers/clk/sophgo/clk-cv1800b.c         |  2 +-
> > > > > >  drivers/clk/starfive/clk-jh7110-pll.c    |  2 +-
> > > > > >  drivers/clk/stm32/clk-stm32-core.c       |  4 +--
> > > > > >  drivers/clk/stm32/clk-stm32f.c           |  6 ++--
> > > > > >  drivers/clk/stm32/clk-stm32h7.c          |  4 +--
> > > > > >  drivers/clk/tegra/tegra-car-clk.c        |  2 +-
> > > > > >  drivers/clk/tegra/tegra186-clk.c         |  2 +-
> > > > > >  drivers/clk/thead/clk-th1520-ap.c        |  2 +-
> > > > > >  drivers/clk/ti/clk-am3-dpll-x2.c         |  4 +--
> > > > > >  drivers/clk/ti/clk-divider.c             |  4 +--
> > > > > >  drivers/clk/ti/clk-mux.c                 |  2 +-
> > > > > >  drivers/clk/ti/clk-sci.c                 |  2 +-
> > > > > >  drivers/clk/uniphier/clk-uniphier-core.c |  2 +-
> > > > > >  65 files changed, 290 insertions(+), 290 deletions(-)
> > > > > > ---
> > > > > > base-commit: ecdc3872a767fb045be3296d4317ae978a14b022
> > > > > > change-id: 20251010-clk_ops-3b7cc9ccd070
> > > > > >
> > > > > > Best regards,
> > > > > > --
> > > > > > Andrew Goodbody <andrew.goodbody@linaro.org>
> > > > > >
> > > > >
> > > > > If you don't return an error, we cannot tell if the operation
> > > > > succeeded, or not. U-Boot needs to be deterministic and we need to be
> > > > > able to debug errors and detect them at runtime.
> > > > >
> > > > > We use ulong for the return value as a bit of a compromise, since it
> > > > > is inefficient to use 64-bit on a 32-bit machine. Ideally it would be
> > > > > long, but some clock rates are 3GHz and it would be confusing to cast
> > > > > to ulong before using the value.
> > > > >
> > > > > An alternative we discussed was to return an integer error with the
> > > > > clock rate returned in a parameter, but that seemed less efficient.
> > > > >
> > > > > With 64-bit machines, there really isn't a problem. Just checking for
> > > > > a negative value is good enough, since the clock rate isn't going to
> > > > > be 9 exahertz(?). Values between -CONFIG_ERR_PTR_OFFSET and 0 are
> > > > > errors and are defined to be so.
> > > > >
> > > > > If you want clk_get_rate() to work like Linux (suppress / ignore
> > > > > errors?), that's fine, but please create a clk_get_rate_err() (or
> > > > > similar) which actually returns the correct error, and keep the error
> > > > > return on the uclass interface. It is not uncommon to have the uclass
> > > > > do some processing on values passed to/from driver. This allows people
> > > > > who care to obtain the error.
> > > >
> > > > This is moving things in the right direction of having the error
> > > > reporting and handling done where it can be done correctly. If there's
> > > > further parts of the Linux kernel-like API we need, we can take those
> > > > next.
> > >
> > > Here is part of the patch:
> > >
> > > --- a/drivers/clk/meson/a1.c
> > > +++ b/drivers/clk/meson/a1.c
> > > @@ -359,7 +359,7 @@ static ulong meson_div_get_rate(struct clk *clk,
> > > unsigned long id)
> > >
> > >         info = meson_clk_get_info(clk, id, MESON_CLK_DIV);
> > >         if (IS_ERR(info))
> > > -               return PTR_ERR(info);
> > > +               return 0;
> > >
> > > I don't see anything in that fragment other than just ignoring errors.
> > >
> >
> > I agree with Simon. This patchset may cause a lot of problems for all
> > boards it changes in case clk ops fail, since it silences all error
> > returns. Any clock error will be untrackable unless you know where and
> > what to look specifically.
>
> I think it's worth going back to the original thread:
> https://lore.kernel.org/u-boot/f5c94319-8ef8-459d-88b2-836702779cfb@linaro.org/

Specifically Heinrich's response which seems to make sense to me -
i.e. IS_ERR_VALUE(). A series that introduced that everywhere would
get my vote :-)

>
> As part of the problem is that what we have today does not work. This is
> why I'm think it's OK to first return 0, always, as the invalid clock
> rate and then re-introduce error checking that can work.

OK, but actually what doesn't work today? Which board is broken? Is
the problem that no one checks the errors?

- Simon