[PATCH v2 0/2] rockchip: Add support for ROCK 5B+

[PATCH v2 0/2] rockchip: Add support for ROCK 5B+

[Jonas Karlman]

This series add support for the ROCK 5B+ variant to the existing
rock5b-rk3588 defconfig taget.

The ROCK 5B+ variant is detected based on DRAM type (LPDDR5) and SARADC
channel 5, the read out value is expected to be close to 4095 (1.8v) on
5B+ variants.

Features tested on a ROCK 5B+ v1.2:
- SD-card boot
- eMMC boot
- SPI flash boot
- PCIe/NVMe
- Ethernet
- USB/TCPM

Changes in v2:
- Add a DRAM type check to detected ROCK 5B+ variant
- Drop device tree patches merged with the v6.16-dts sync

Jonas Karlman (2):
  rockchip: sdram: Add rockchip_sdram_type() helper
  rockchip: rock5b-rk3588: Add support for ROCK 5B+

 arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi |  3 +
 arch/arm/dts/rk3588-rock-5b-u-boot.dtsi      |  5 ++
 arch/arm/include/asm/arch-rockchip/sdram.h   |  3 +
 arch/arm/mach-rockchip/sdram.c               | 15 +++++
 board/radxa/rock5b-rk3588/Kconfig            |  5 ++
 board/radxa/rock5b-rk3588/MAINTAINERS        |  3 +-
 board/radxa/rock5b-rk3588/rock5b-rk3588.c    | 63 ++++++++++++++++++++
 configs/rock5b-rk3588_defconfig              |  1 +
 doc/board/rockchip/rockchip.rst              |  2 +-
 9 files changed, 97 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi

-- 
2.50.1

[PATCH v2 1/2] rockchip: sdram: Add rockchip_sdram_type() helper

[Jonas Karlman]

Add a helper function based on rockchip_sdram_size() that return what
DRAM type is used on current running board.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
v2: New patch
---
 arch/arm/include/asm/arch-rockchip/sdram.h |  3 +++
 arch/arm/mach-rockchip/sdram.c             | 15 +++++++++++++++
 2 files changed, 18 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h b/arch/arm/include/asm/arch-rockchip/sdram.h
index 4fb45ac5c76e..476fc1c4ee33 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram.h
@@ -87,6 +87,9 @@ enum {
 #define SYS_REG_CS1_COL_SHIFT(ch)		(0 + (ch) * 2)
 #define SYS_REG_CS1_COL_MASK			3
 
+/* Get sdram type decode from reg */
+u8 rockchip_sdram_type(phys_addr_t reg);
+
 /* Get sdram size decode from reg */
 size_t rockchip_sdram_size(phys_addr_t reg);
 
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 3bc482331c7e..d560f90e873d 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -345,6 +345,21 @@ int dram_init_banksize(void)
 	return 0;
 }
 
+u8 rockchip_sdram_type(phys_addr_t reg)
+{
+	u32 dram_type, version;
+	u32 sys_reg2 = readl(reg);
+	u32 sys_reg3 = readl(reg + 4);
+
+	dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
+	version = (sys_reg3 >> SYS_REG_VERSION_SHIFT) & SYS_REG_VERSION_MASK;
+	if (version >= 3)
+		dram_type |= ((sys_reg3 >> SYS_REG_EXTEND_DDRTYPE_SHIFT) &
+			      SYS_REG_EXTEND_DDRTYPE_MASK) << 3;
+
+	return dram_type;
+}
+
 size_t rockchip_sdram_size(phys_addr_t reg)
 {
 	u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;
-- 
2.50.1

Re: [PATCH v2 1/2] rockchip: sdram: Add rockchip_sdram_type() helper

[Quentin Schulz]

Hi Jonas,

On 8/1/25 7:09 PM, Jonas Karlman wrote:
> Add a helper function based on rockchip_sdram_size() that return what
> DRAM type is used on current running board.
> 
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
> ---
> v2: New patch
> ---
>   arch/arm/include/asm/arch-rockchip/sdram.h |  3 +++
>   arch/arm/mach-rockchip/sdram.c             | 15 +++++++++++++++
>   2 files changed, 18 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h b/arch/arm/include/asm/arch-rockchip/sdram.h
> index 4fb45ac5c76e..476fc1c4ee33 100644
> --- a/arch/arm/include/asm/arch-rockchip/sdram.h
> +++ b/arch/arm/include/asm/arch-rockchip/sdram.h
> @@ -87,6 +87,9 @@ enum {
>   #define SYS_REG_CS1_COL_SHIFT(ch)		(0 + (ch) * 2)
>   #define SYS_REG_CS1_COL_MASK			3
>   
> +/* Get sdram type decode from reg */

s/decode/decoded/

Please define in the comment how to map the u8 to the actual SDRAM type? 
I guess ideally we should have the enum in 
arch/arm/include/asm/arch-rockchip/sdram.h typedef'ed or at least named 
and return that type instead of a u8?

Please also document which register we should be passing there and the 
assumptions made in the fucntion (that the version (of what?) will be 
read in the next register as well).

> +u8 rockchip_sdram_type(phys_addr_t reg);
> +
>   /* Get sdram size decode from reg */
>   size_t rockchip_sdram_size(phys_addr_t reg);
>   
> diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
> index 3bc482331c7e..d560f90e873d 100644
> --- a/arch/arm/mach-rockchip/sdram.c
> +++ b/arch/arm/mach-rockchip/sdram.c
> @@ -345,6 +345,21 @@ int dram_init_banksize(void)
>   	return 0;
>   }
>   
> +u8 rockchip_sdram_type(phys_addr_t reg)
> +{
> +	u32 dram_type, version;
> +	u32 sys_reg2 = readl(reg);
> +	u32 sys_reg3 = readl(reg + 4);
> +
> +	dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
> +	version = (sys_reg3 >> SYS_REG_VERSION_SHIFT) & SYS_REG_VERSION_MASK;
> +	if (version >= 3)
> +		dram_type |= ((sys_reg3 >> SYS_REG_EXTEND_DDRTYPE_SHIFT) &
> +			      SYS_REG_EXTEND_DDRTYPE_MASK) << 3;
> +
> +	return dram_type;
> +}

I would have preferred to use FIELD_GET here but I now see that this is 
extracted from rockchip_sdram_size where it's like that.

Can we make rockchip_sdram_size() a user of rockchip_sdram_type() to 
make sure it doesn't get outdated?

Cheers,
Quentin

Re: [PATCH v2 1/2] rockchip: sdram: Add rockchip_sdram_type() helper

[Kever Yang]

On 2025/8/2 01:09, Jonas Karlman wrote:
> Add a helper function based on rockchip_sdram_size() that return what
> DRAM type is used on current running board.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
> v2: New patch
> ---
>   arch/arm/include/asm/arch-rockchip/sdram.h |  3 +++
>   arch/arm/mach-rockchip/sdram.c             | 15 +++++++++++++++
>   2 files changed, 18 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h b/arch/arm/include/asm/arch-rockchip/sdram.h
> index 4fb45ac5c76e..476fc1c4ee33 100644
> --- a/arch/arm/include/asm/arch-rockchip/sdram.h
> +++ b/arch/arm/include/asm/arch-rockchip/sdram.h
> @@ -87,6 +87,9 @@ enum {
>   #define SYS_REG_CS1_COL_SHIFT(ch)		(0 + (ch) * 2)
>   #define SYS_REG_CS1_COL_MASK			3
>   
> +/* Get sdram type decode from reg */
> +u8 rockchip_sdram_type(phys_addr_t reg);
> +
>   /* Get sdram size decode from reg */
>   size_t rockchip_sdram_size(phys_addr_t reg);
>   
> diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
> index 3bc482331c7e..d560f90e873d 100644
> --- a/arch/arm/mach-rockchip/sdram.c
> +++ b/arch/arm/mach-rockchip/sdram.c
> @@ -345,6 +345,21 @@ int dram_init_banksize(void)
>   	return 0;
>   }
>   
> +u8 rockchip_sdram_type(phys_addr_t reg)
> +{
> +	u32 dram_type, version;
> +	u32 sys_reg2 = readl(reg);
> +	u32 sys_reg3 = readl(reg + 4);
> +
> +	dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
> +	version = (sys_reg3 >> SYS_REG_VERSION_SHIFT) & SYS_REG_VERSION_MASK;
> +	if (version >= 3)
> +		dram_type |= ((sys_reg3 >> SYS_REG_EXTEND_DDRTYPE_SHIFT) &
> +			      SYS_REG_EXTEND_DDRTYPE_MASK) << 3;
> +
> +	return dram_type;
> +}
> +
>   size_t rockchip_sdram_size(phys_addr_t reg)
>   {
>   	u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;

[PATCH v2 2/2] rockchip: rock5b-rk3588: Add support for ROCK 5B+

[Jonas Karlman]

Include FDTs for both ROCK 5B and 5B+ in the FIT and add board selection
code to load the 5B+ FDT when the DRAM type is LPDDR5 and ADC channel 5
value is close to 4095.

  U-Boot 2025.07 (Jul 14 2025 - 21:28:20 +0000)

  Model: Radxa ROCK 5B+
  SoC:   RK3588
  DRAM:  8 GiB

Features tested on a ROCK 5B+ v1.2:
- SD-card boot
- eMMC boot
- SPI flash boot
- PCIe/NVMe
- Ethernet
- USB/TCPM

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
Changes in v2:
- Add DRAM type check in addition to SARADC check
---
 arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi |  3 +
 arch/arm/dts/rk3588-rock-5b-u-boot.dtsi      |  5 ++
 board/radxa/rock5b-rk3588/Kconfig            |  5 ++
 board/radxa/rock5b-rk3588/MAINTAINERS        |  3 +-
 board/radxa/rock5b-rk3588/rock5b-rk3588.c    | 63 ++++++++++++++++++++
 configs/rock5b-rk3588_defconfig              |  1 +
 doc/board/rockchip/rockchip.rst              |  2 +-
 7 files changed, 79 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi

diff --git a/arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi
new file mode 100644
index 000000000000..c07696c83913
--- /dev/null
+++ b/arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588-rock-5b-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index d51fbf51cb88..e07b549c767f 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -46,6 +46,11 @@
 	};
 };
 
+&saradc {
+	bootph-pre-ram;
+	vdd-microvolts = <1800000>;
+};
+
 &sdhci {
 	cap-mmc-highspeed;
 	mmc-hs200-1_8v;
diff --git a/board/radxa/rock5b-rk3588/Kconfig b/board/radxa/rock5b-rk3588/Kconfig
index 41dfe2402b12..98d630117836 100644
--- a/board/radxa/rock5b-rk3588/Kconfig
+++ b/board/radxa/rock5b-rk3588/Kconfig
@@ -9,4 +9,9 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "rock5b-rk3588"
 
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ADC
+	select SPL_ADC
+
 endif
diff --git a/board/radxa/rock5b-rk3588/MAINTAINERS b/board/radxa/rock5b-rk3588/MAINTAINERS
index 4460c9971a96..c8a43769105e 100644
--- a/board/radxa/rock5b-rk3588/MAINTAINERS
+++ b/board/radxa/rock5b-rk3588/MAINTAINERS
@@ -5,5 +5,4 @@ S:	Maintained
 F:	board/radxa/rock5b-rk3588
 F:	include/configs/rock5b-rk3588.h
 F:	configs/rock5b-rk3588_defconfig
-F:	arch/arm/dts/rk3588-rock-5b.dts
-F:	arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+F:	arch/arm/dts/rk3588-rock-5b*
diff --git a/board/radxa/rock5b-rk3588/rock5b-rk3588.c b/board/radxa/rock5b-rk3588/rock5b-rk3588.c
index fc2f69db2241..6bf4497ce3ae 100644
--- a/board/radxa/rock5b-rk3588/rock5b-rk3588.c
+++ b/board/radxa/rock5b-rk3588/rock5b-rk3588.c
@@ -3,8 +3,71 @@
  * Copyright (c) 2023-2024 Collabora Ltd.
  */
 
+#include <adc.h>
+#include <env.h>
 #include <fdtdec.h>
 #include <fdt_support.h>
+#include <asm/arch-rockchip/sdram.h>
+#include <linux/errno.h>
+
+#define PMU1GRF_BASE		0xfd58a000
+#define OS_REG2_REG		0x208
+
+#define HW_ID_CHANNEL		5
+
+struct board_model {
+	unsigned int dram;
+	unsigned int low;
+	unsigned int high;
+	const char *fdtfile;
+};
+
+static const struct board_model board_models[] = {
+	{ LPDDR5, 4005, 4185, "rockchip/rk3588-rock-5b-plus.dtb" },
+};
+
+static const struct board_model *get_board_model(void)
+{
+	unsigned int val, dram_type;
+	int i, ret;
+
+	dram_type = rockchip_sdram_type(PMU1GRF_BASE + OS_REG2_REG);
+
+	ret = adc_channel_single_shot("adc@fec10000", HW_ID_CHANNEL, &val);
+	if (ret)
+		return NULL;
+
+	for (i = 0; i < ARRAY_SIZE(board_models); i++) {
+		unsigned int dram = board_models[i].dram;
+		unsigned int min = board_models[i].low;
+		unsigned int max = board_models[i].high;
+
+		if (dram == dram_type && min <= val && val <= max)
+			return &board_models[i];
+	}
+
+	return NULL;
+}
+
+int rk_board_late_init(void)
+{
+	const struct board_model *model = get_board_model();
+
+	if (model)
+		env_set("fdtfile", model->fdtfile);
+
+	return 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+	const struct board_model *model = get_board_model();
+
+	if (model && !strcmp(name, model->fdtfile))
+		return 0;
+
+	return -EINVAL;
+}
 
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, struct bd_info *bd)
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index 6349e8791456..967cebc2054f 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -47,6 +47,7 @@ CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
+CONFIG_OF_LIST="rockchip/rk3588-rock-5b rockchip/rk3588-rock-5b-plus"
 CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_REGMAP=y
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index b88299cbba23..7a1385789c20 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -152,7 +152,7 @@ List of mainline supported Rockchip boards:
      - Pine64 QuartzPro64 (quartzpro64-rk3588)
      - Radxa ROCK 5 ITX (rock-5-itx-rk3588)
      - Radxa ROCK 5A (rock5a-rk3588s)
-     - Radxa ROCK 5B (rock5b-rk3588)
+     - Radxa ROCK 5B/5B+ (rock5b-rk3588)
      - Radxa ROCK 5C (rock-5c-rk3588s)
      - Rockchip Toybrick TB-RK3588X (toybrick-rk3588)
      - Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588)
-- 
2.50.1

Re: [PATCH v2 2/2] rockchip: rock5b-rk3588: Add support for ROCK 5B+

[Quentin Schulz]

Hi Jonas,

On 8/1/25 7:09 PM, Jonas Karlman wrote:
> Include FDTs for both ROCK 5B and 5B+ in the FIT and add board selection
> code to load the 5B+ FDT when the DRAM type is LPDDR5 and ADC channel 5
> value is close to 4095.
> 
>    U-Boot 2025.07 (Jul 14 2025 - 21:28:20 +0000)
> 
>    Model: Radxa ROCK 5B+
>    SoC:   RK3588
>    DRAM:  8 GiB
> 
> Features tested on a ROCK 5B+ v1.2:
> - SD-card boot
> - eMMC boot
> - SPI flash boot
> - PCIe/NVMe
> - Ethernet
> - USB/TCPM
> 
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
> ---
> Changes in v2:
> - Add DRAM type check in addition to SARADC check
> ---
>   arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi |  3 +
>   arch/arm/dts/rk3588-rock-5b-u-boot.dtsi      |  5 ++
>   board/radxa/rock5b-rk3588/Kconfig            |  5 ++
>   board/radxa/rock5b-rk3588/MAINTAINERS        |  3 +-
>   board/radxa/rock5b-rk3588/rock5b-rk3588.c    | 63 ++++++++++++++++++++
>   configs/rock5b-rk3588_defconfig              |  1 +
>   doc/board/rockchip/rockchip.rst              |  2 +-
>   7 files changed, 79 insertions(+), 3 deletions(-)
>   create mode 100644 arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi
> 
> diff --git a/arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi
> new file mode 100644
> index 000000000000..c07696c83913
> --- /dev/null
> +++ b/arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi
> @@ -0,0 +1,3 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +
> +#include "rk3588-rock-5b-u-boot.dtsi"
> diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
> index d51fbf51cb88..e07b549c767f 100644
> --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
> +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
> @@ -46,6 +46,11 @@
>   	};
>   };
>   
> +&saradc {
> +	bootph-pre-ram;
> +	vdd-microvolts = <1800000>;
> +};
> +
>   &sdhci {
>   	cap-mmc-highspeed;
>   	mmc-hs200-1_8v;
> diff --git a/board/radxa/rock5b-rk3588/Kconfig b/board/radxa/rock5b-rk3588/Kconfig
> index 41dfe2402b12..98d630117836 100644
> --- a/board/radxa/rock5b-rk3588/Kconfig
> +++ b/board/radxa/rock5b-rk3588/Kconfig
> @@ -9,4 +9,9 @@ config SYS_VENDOR
>   config SYS_CONFIG_NAME
>   	default "rock5b-rk3588"
>   
> +config BOARD_SPECIFIC_OPTIONS # dummy
> +	def_bool y
> +	select ADC
> +	select SPL_ADC
> +
>   endif
> diff --git a/board/radxa/rock5b-rk3588/MAINTAINERS b/board/radxa/rock5b-rk3588/MAINTAINERS
> index 4460c9971a96..c8a43769105e 100644
> --- a/board/radxa/rock5b-rk3588/MAINTAINERS
> +++ b/board/radxa/rock5b-rk3588/MAINTAINERS
> @@ -5,5 +5,4 @@ S:	Maintained
>   F:	board/radxa/rock5b-rk3588
>   F:	include/configs/rock5b-rk3588.h
>   F:	configs/rock5b-rk3588_defconfig
> -F:	arch/arm/dts/rk3588-rock-5b.dts
> -F:	arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
> +F:	arch/arm/dts/rk3588-rock-5b*
> diff --git a/board/radxa/rock5b-rk3588/rock5b-rk3588.c b/board/radxa/rock5b-rk3588/rock5b-rk3588.c
> index fc2f69db2241..6bf4497ce3ae 100644
> --- a/board/radxa/rock5b-rk3588/rock5b-rk3588.c
> +++ b/board/radxa/rock5b-rk3588/rock5b-rk3588.c
> @@ -3,8 +3,71 @@
>    * Copyright (c) 2023-2024 Collabora Ltd.
>    */
>   
> +#include <adc.h>
> +#include <env.h>
>   #include <fdtdec.h>
>   #include <fdt_support.h>
> +#include <asm/arch-rockchip/sdram.h>
> +#include <linux/errno.h>
> +
> +#define PMU1GRF_BASE		0xfd58a000
> +#define OS_REG2_REG		0x208
> +

I assume the register address and meaning is stable across all RK3588, 
so maybe we should abstract that somewhere in the SoC file 
(arch/arm/mach-rockchip/rk3588) so that the caller doesn't need to 
specify them?

> +#define HW_ID_CHANNEL		5
> +
> +struct board_model {
> +	unsigned int dram;
> +	unsigned int low;
> +	unsigned int high;
> +	const char *fdtfile;
> +};
> +
> +static const struct board_model board_models[] = {
> +	{ LPDDR5, 4005, 4185, "rockchip/rk3588-rock-5b-plus.dtb" },
> +};
> +
> +static const struct board_model *get_board_model(void)
> +{
> +	unsigned int val, dram_type;
> +	int i, ret;

i could be an unsigned number type as well. (and it should since we're 
using it to access items in an array)

> +
> +	dram_type = rockchip_sdram_type(PMU1GRF_BASE + OS_REG2_REG);
> +
> +	ret = adc_channel_single_shot("adc@fec10000", HW_ID_CHANNEL, &val);
> +	if (ret)
> +		return NULL;
> +

While checking whether adc_channel_single_shot() is the right function 
to call, I stumbled upon the call in arch/arm/mach-rockchip/boot_mode.c 
which i believe wouldn't work for Rockchip SoCs whose DTSI uses adc@ as 
node name instead of saradc@. That would be rk3328, rk3588, rk3576, 
rk3528 and rv1126.

I guess there are different ways to fix this. We could have each SoC 
define a constant string with the node name of the SARADC or have an 
additional entry in /aliases for saradc in the DT? Maybe some other way 
could be used as well, just throwing ideas :)

Unrelated to this patch though, so feel free to ignore.

Cheers,
Quentin

Re: [PATCH v2 2/2] rockchip: rock5b-rk3588: Add support for ROCK 5B+

[Jonas Karlman]

Hi Quentin,

On 8/11/2025 11:24 AM, Quentin Schulz wrote:
> Hi Jonas,
> 
> On 8/1/25 7:09 PM, Jonas Karlman wrote:
>> Include FDTs for both ROCK 5B and 5B+ in the FIT and add board selection
>> code to load the 5B+ FDT when the DRAM type is LPDDR5 and ADC channel 5
>> value is close to 4095.
>>
>>    U-Boot 2025.07 (Jul 14 2025 - 21:28:20 +0000)
>>
>>    Model: Radxa ROCK 5B+
>>    SoC:   RK3588
>>    DRAM:  8 GiB
>>
>> Features tested on a ROCK 5B+ v1.2:
>> - SD-card boot
>> - eMMC boot
>> - SPI flash boot
>> - PCIe/NVMe
>> - Ethernet
>> - USB/TCPM
>>
>> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
>> ---
>> Changes in v2:
>> - Add DRAM type check in addition to SARADC check
>> ---
>>   arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi |  3 +
>>   arch/arm/dts/rk3588-rock-5b-u-boot.dtsi      |  5 ++
>>   board/radxa/rock5b-rk3588/Kconfig            |  5 ++
>>   board/radxa/rock5b-rk3588/MAINTAINERS        |  3 +-
>>   board/radxa/rock5b-rk3588/rock5b-rk3588.c    | 63 ++++++++++++++++++++
>>   configs/rock5b-rk3588_defconfig              |  1 +
>>   doc/board/rockchip/rockchip.rst              |  2 +-
>>   7 files changed, 79 insertions(+), 3 deletions(-)
>>   create mode 100644 arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi
>>
>> diff --git a/arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi
>> new file mode 100644
>> index 000000000000..c07696c83913
>> --- /dev/null
>> +++ b/arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi
>> @@ -0,0 +1,3 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +
>> +#include "rk3588-rock-5b-u-boot.dtsi"
>> diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
>> index d51fbf51cb88..e07b549c767f 100644
>> --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
>> +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
>> @@ -46,6 +46,11 @@
>>   	};
>>   };
>>   
>> +&saradc {
>> +	bootph-pre-ram;
>> +	vdd-microvolts = <1800000>;
>> +};
>> +
>>   &sdhci {
>>   	cap-mmc-highspeed;
>>   	mmc-hs200-1_8v;
>> diff --git a/board/radxa/rock5b-rk3588/Kconfig b/board/radxa/rock5b-rk3588/Kconfig
>> index 41dfe2402b12..98d630117836 100644
>> --- a/board/radxa/rock5b-rk3588/Kconfig
>> +++ b/board/radxa/rock5b-rk3588/Kconfig
>> @@ -9,4 +9,9 @@ config SYS_VENDOR
>>   config SYS_CONFIG_NAME
>>   	default "rock5b-rk3588"
>>   
>> +config BOARD_SPECIFIC_OPTIONS # dummy
>> +	def_bool y
>> +	select ADC
>> +	select SPL_ADC
>> +
>>   endif
>> diff --git a/board/radxa/rock5b-rk3588/MAINTAINERS b/board/radxa/rock5b-rk3588/MAINTAINERS
>> index 4460c9971a96..c8a43769105e 100644
>> --- a/board/radxa/rock5b-rk3588/MAINTAINERS
>> +++ b/board/radxa/rock5b-rk3588/MAINTAINERS
>> @@ -5,5 +5,4 @@ S:	Maintained
>>   F:	board/radxa/rock5b-rk3588
>>   F:	include/configs/rock5b-rk3588.h
>>   F:	configs/rock5b-rk3588_defconfig
>> -F:	arch/arm/dts/rk3588-rock-5b.dts
>> -F:	arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
>> +F:	arch/arm/dts/rk3588-rock-5b*
>> diff --git a/board/radxa/rock5b-rk3588/rock5b-rk3588.c b/board/radxa/rock5b-rk3588/rock5b-rk3588.c
>> index fc2f69db2241..6bf4497ce3ae 100644
>> --- a/board/radxa/rock5b-rk3588/rock5b-rk3588.c
>> +++ b/board/radxa/rock5b-rk3588/rock5b-rk3588.c
>> @@ -3,8 +3,71 @@
>>    * Copyright (c) 2023-2024 Collabora Ltd.
>>    */
>>   
>> +#include <adc.h>
>> +#include <env.h>
>>   #include <fdtdec.h>
>>   #include <fdt_support.h>
>> +#include <asm/arch-rockchip/sdram.h>
>> +#include <linux/errno.h>
>> +
>> +#define PMU1GRF_BASE		0xfd58a000
>> +#define OS_REG2_REG		0x208
>> +
> 
> I assume the register address and meaning is stable across all RK3588, 
> so maybe we should abstract that somewhere in the SoC file 
> (arch/arm/mach-rockchip/rk3588) so that the caller doesn't need to 
> specify them?

Correct, these are stable for the SoC and could be defined in soc
related header and is something I have very slowly been working on in my
optimize branch at [1] for a future series.

Right now we have some code using syscon_get_first_range() to get a base
addr from DT, and newer code that instead use a define. See e.g.
sdram_rk3588.c vs sdram_rk3576.c, getting the base from DT adds several
ms delay and something that seem pointless when we know the stable addr
at compile time.

So for now I just kept this here with the expectation that this should
be changed in a future series.

[1] https://source.denx.de/u-boot/contributors/kwiboo/u-boot/-/commit/3a11ab7fba8db133374e60edf8ab2b46195cf684

> 
>> +#define HW_ID_CHANNEL		5
>> +
>> +struct board_model {
>> +	unsigned int dram;
>> +	unsigned int low;
>> +	unsigned int high;
>> +	const char *fdtfile;
>> +};
>> +
>> +static const struct board_model board_models[] = {
>> +	{ LPDDR5, 4005, 4185, "rockchip/rk3588-rock-5b-plus.dtb" },
>> +};
>> +
>> +static const struct board_model *get_board_model(void)
>> +{
>> +	unsigned int val, dram_type;
>> +	int i, ret;
> 
> i could be an unsigned number type as well. (and it should since we're 
> using it to access items in an array)

Sure, will change in v3.

> 
>> +
>> +	dram_type = rockchip_sdram_type(PMU1GRF_BASE + OS_REG2_REG);
>> +
>> +	ret = adc_channel_single_shot("adc@fec10000", HW_ID_CHANNEL, &val);
>> +	if (ret)
>> +		return NULL;
>> +
> 
> While checking whether adc_channel_single_shot() is the right function 
> to call, I stumbled upon the call in arch/arm/mach-rockchip/boot_mode.c 
> which i believe wouldn't work for Rockchip SoCs whose DTSI uses adc@ as 
> node name instead of saradc@. That would be rk3328, rk3588, rk3576, 
> rk3528 and rv1126.

Correct, the saradc@ in boot_mode.c is typically used for "recovery" or
"maskrom" detection. However, this uses a hardcoded saradc channel that
may not necessarily be used for that purpose, especially on newer SoCs.

I suggest we do not try to change that to cover more SoCs without first
adding a way to define what channel to use for the button detection,
possible in a /config or a Kconfig option.

> 
> I guess there are different ways to fix this. We could have each SoC 
> define a constant string with the node name of the SARADC or have an 
> additional entry in /aliases for saradc in the DT? Maybe some other way 
> could be used as well, just throwing ideas :)
> 
> Unrelated to this patch though, so feel free to ignore.

As noted above, I think it is something to fix/consider but it may have
unintended consequences to blindly try and fix boot_mode.c for all RK
SoCs without having some sort of board option to specify when and how
the feature should be used.

Regards,
Jonas

> 
> Cheers,
> Quentin

Re: [PATCH v2 2/2] rockchip: rock5b-rk3588: Add support for ROCK 5B+

[Quentin Schulz]

Hi Jonas,

On 8/11/25 11:17 PM, Jonas Karlman wrote:
> Hi Quentin,
> 
> On 8/11/2025 11:24 AM, Quentin Schulz wrote:
>> Hi Jonas,
>>
>> On 8/1/25 7:09 PM, Jonas Karlman wrote:
[...]
>>> +#define PMU1GRF_BASE		0xfd58a000
>>> +#define OS_REG2_REG		0x208
>>> +
>>
>> I assume the register address and meaning is stable across all RK3588,
>> so maybe we should abstract that somewhere in the SoC file
>> (arch/arm/mach-rockchip/rk3588) so that the caller doesn't need to
>> specify them?
> 
> Correct, these are stable for the SoC and could be defined in soc
> related header and is something I have very slowly been working on in my
> optimize branch at [1] for a future series.
> 
> Right now we have some code using syscon_get_first_range() to get a base
> addr from DT, and newer code that instead use a define. See e.g.
> sdram_rk3588.c vs sdram_rk3576.c, getting the base from DT adds several
> ms delay and something that seem pointless when we know the stable addr
> at compile time.
> 

We could do something more akin to:

u8 _rockchip_sdram_type(phys_addr_t reg)
{
	u32 dram_type, version;
	u32 sys_reg2 = readl(reg);
	u32 sys_reg3 = readl(reg + 4);

	dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
	version = (sys_reg3 >> SYS_REG_VERSION_SHIFT) & SYS_REG_VERSION_MASK;
	if (version >= 3)
		dram_type |= ((sys_reg3 >> SYS_REG_EXTEND_DDRTYPE_SHIFT) &
			      SYS_REG_EXTEND_DDRTYPE_MASK) << 3;

	return dram_type;
}

u8 __weak rockchip_dram_type_reg(void)
{
     return 0;
}

u8 rockchip_sdram_type(void)
{
	phys_addr_t reg = rockchip_dram_type_reg();
	if (!reg)
		return UNUSED;

	return _rockchip_sdram_type(reg);
}

and define

u8 rockchip_dram_type_reg(void)
{
	return PMU1GRF_BASE + OS_REG2_REG;
}

in drivers/ram/rockchip/sdram_rk3588.c for example.

That's what I had in mind rather than going for a syscon.

> So for now I just kept this here with the expectation that this should
> be changed in a future series.
> 
> [1] https://source.denx.de/u-boot/contributors/kwiboo/u-boot/-/commit/3a11ab7fba8db133374e60edf8ab2b46195cf684
> 
>>
>>> +#define HW_ID_CHANNEL		5
>>> +
>>> +struct board_model {
>>> +	unsigned int dram;
>>> +	unsigned int low;
>>> +	unsigned int high;
>>> +	const char *fdtfile;
>>> +};
>>> +
>>> +static const struct board_model board_models[] = {
>>> +	{ LPDDR5, 4005, 4185, "rockchip/rk3588-rock-5b-plus.dtb" },
>>> +};
>>> +
>>> +static const struct board_model *get_board_model(void)
>>> +{
>>> +	unsigned int val, dram_type;
>>> +	int i, ret;
>>
>> i could be an unsigned number type as well. (and it should since we're
>> using it to access items in an array)
> 
> Sure, will change in v3.
> 
>>
>>> +
>>> +	dram_type = rockchip_sdram_type(PMU1GRF_BASE + OS_REG2_REG);
>>> +
>>> +	ret = adc_channel_single_shot("adc@fec10000", HW_ID_CHANNEL, &val);
>>> +	if (ret)
>>> +		return NULL;
>>> +
>>
>> While checking whether adc_channel_single_shot() is the right function
>> to call, I stumbled upon the call in arch/arm/mach-rockchip/boot_mode.c
>> which i believe wouldn't work for Rockchip SoCs whose DTSI uses adc@ as
>> node name instead of saradc@. That would be rk3328, rk3588, rk3576,
>> rk3528 and rv1126.
> 
> Correct, the saradc@ in boot_mode.c is typically used for "recovery" or
> "maskrom" detection. However, this uses a hardcoded saradc channel that
> may not necessarily be used for that purpose, especially on newer SoCs.
> 
> I suggest we do not try to change that to cover more SoCs without first
> adding a way to define what channel to use for the button detection,
> possible in a /config or a Kconfig option.
> 
>>
>> I guess there are different ways to fix this. We could have each SoC
>> define a constant string with the node name of the SARADC or have an
>> additional entry in /aliases for saradc in the DT? Maybe some other way
>> could be used as well, just throwing ideas :)
>>
>> Unrelated to this patch though, so feel free to ignore.
> 
> As noted above, I think it is something to fix/consider but it may have
> unintended consequences to blindly try and fix boot_mode.c for all RK
> SoCs without having some sort of board option to specify when and how
> the feature should be used.
> 

Agreed.

Cheers,
Quentin

Re: [PATCH v2 2/2] rockchip: rock5b-rk3588: Add support for ROCK 5B+

[Kever Yang]

On 2025/8/2 01:09, Jonas Karlman wrote:
> Include FDTs for both ROCK 5B and 5B+ in the FIT and add board selection
> code to load the 5B+ FDT when the DRAM type is LPDDR5 and ADC channel 5
> value is close to 4095.
>
>    U-Boot 2025.07 (Jul 14 2025 - 21:28:20 +0000)
>
>    Model: Radxa ROCK 5B+
>    SoC:   RK3588
>    DRAM:  8 GiB
>
> Features tested on a ROCK 5B+ v1.2:
> - SD-card boot
> - eMMC boot
> - SPI flash boot
> - PCIe/NVMe
> - Ethernet
> - USB/TCPM
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
> Changes in v2:
> - Add DRAM type check in addition to SARADC check
> ---
>   arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi |  3 +
>   arch/arm/dts/rk3588-rock-5b-u-boot.dtsi      |  5 ++
>   board/radxa/rock5b-rk3588/Kconfig            |  5 ++
>   board/radxa/rock5b-rk3588/MAINTAINERS        |  3 +-
>   board/radxa/rock5b-rk3588/rock5b-rk3588.c    | 63 ++++++++++++++++++++
>   configs/rock5b-rk3588_defconfig              |  1 +
>   doc/board/rockchip/rockchip.rst              |  2 +-
>   7 files changed, 79 insertions(+), 3 deletions(-)
>   create mode 100644 arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi
>
> diff --git a/arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi
> new file mode 100644
> index 000000000000..c07696c83913
> --- /dev/null
> +++ b/arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi
> @@ -0,0 +1,3 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +
> +#include "rk3588-rock-5b-u-boot.dtsi"
> diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
> index d51fbf51cb88..e07b549c767f 100644
> --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
> +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
> @@ -46,6 +46,11 @@
>   	};
>   };
>   
> +&saradc {
> +	bootph-pre-ram;
> +	vdd-microvolts = <1800000>;
> +};
> +
>   &sdhci {
>   	cap-mmc-highspeed;
>   	mmc-hs200-1_8v;
> diff --git a/board/radxa/rock5b-rk3588/Kconfig b/board/radxa/rock5b-rk3588/Kconfig
> index 41dfe2402b12..98d630117836 100644
> --- a/board/radxa/rock5b-rk3588/Kconfig
> +++ b/board/radxa/rock5b-rk3588/Kconfig
> @@ -9,4 +9,9 @@ config SYS_VENDOR
>   config SYS_CONFIG_NAME
>   	default "rock5b-rk3588"
>   
> +config BOARD_SPECIFIC_OPTIONS # dummy
> +	def_bool y
> +	select ADC
> +	select SPL_ADC
> +
>   endif
> diff --git a/board/radxa/rock5b-rk3588/MAINTAINERS b/board/radxa/rock5b-rk3588/MAINTAINERS
> index 4460c9971a96..c8a43769105e 100644
> --- a/board/radxa/rock5b-rk3588/MAINTAINERS
> +++ b/board/radxa/rock5b-rk3588/MAINTAINERS
> @@ -5,5 +5,4 @@ S:	Maintained
>   F:	board/radxa/rock5b-rk3588
>   F:	include/configs/rock5b-rk3588.h
>   F:	configs/rock5b-rk3588_defconfig
> -F:	arch/arm/dts/rk3588-rock-5b.dts
> -F:	arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
> +F:	arch/arm/dts/rk3588-rock-5b*
> diff --git a/board/radxa/rock5b-rk3588/rock5b-rk3588.c b/board/radxa/rock5b-rk3588/rock5b-rk3588.c
> index fc2f69db2241..6bf4497ce3ae 100644
> --- a/board/radxa/rock5b-rk3588/rock5b-rk3588.c
> +++ b/board/radxa/rock5b-rk3588/rock5b-rk3588.c
> @@ -3,8 +3,71 @@
>    * Copyright (c) 2023-2024 Collabora Ltd.
>    */
>   
> +#include <adc.h>
> +#include <env.h>
>   #include <fdtdec.h>
>   #include <fdt_support.h>
> +#include <asm/arch-rockchip/sdram.h>
> +#include <linux/errno.h>
> +
> +#define PMU1GRF_BASE		0xfd58a000
> +#define OS_REG2_REG		0x208
> +
> +#define HW_ID_CHANNEL		5
> +
> +struct board_model {
> +	unsigned int dram;
> +	unsigned int low;
> +	unsigned int high;
> +	const char *fdtfile;
> +};
> +
> +static const struct board_model board_models[] = {
> +	{ LPDDR5, 4005, 4185, "rockchip/rk3588-rock-5b-plus.dtb" },
> +};
> +
> +static const struct board_model *get_board_model(void)
> +{
> +	unsigned int val, dram_type;
> +	int i, ret;
> +
> +	dram_type = rockchip_sdram_type(PMU1GRF_BASE + OS_REG2_REG);
> +
> +	ret = adc_channel_single_shot("adc@fec10000", HW_ID_CHANNEL, &val);
> +	if (ret)
> +		return NULL;
> +
> +	for (i = 0; i < ARRAY_SIZE(board_models); i++) {
> +		unsigned int dram = board_models[i].dram;
> +		unsigned int min = board_models[i].low;
> +		unsigned int max = board_models[i].high;
> +
> +		if (dram == dram_type && min <= val && val <= max)
> +			return &board_models[i];
> +	}
> +
> +	return NULL;
> +}
> +
> +int rk_board_late_init(void)
> +{
> +	const struct board_model *model = get_board_model();
> +
> +	if (model)
> +		env_set("fdtfile", model->fdtfile);
> +
> +	return 0;
> +}
> +
> +int board_fit_config_name_match(const char *name)
> +{
> +	const struct board_model *model = get_board_model();
> +
> +	if (model && !strcmp(name, model->fdtfile))
> +		return 0;
> +
> +	return -EINVAL;
> +}
>   
>   #ifdef CONFIG_OF_BOARD_SETUP
>   int ft_board_setup(void *blob, struct bd_info *bd)
> diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
> index 6349e8791456..967cebc2054f 100644
> --- a/configs/rock5b-rk3588_defconfig
> +++ b/configs/rock5b-rk3588_defconfig
> @@ -47,6 +47,7 @@ CONFIG_CMD_REGULATOR=y
>   # CONFIG_SPL_DOS_PARTITION is not set
>   CONFIG_SPL_OF_CONTROL=y
>   CONFIG_OF_LIVE=y
> +CONFIG_OF_LIST="rockchip/rk3588-rock-5b rockchip/rk3588-rock-5b-plus"
>   CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
>   CONFIG_SPL_DM_SEQ_ALIAS=y
>   CONFIG_SPL_REGMAP=y
> diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
> index b88299cbba23..7a1385789c20 100644
> --- a/doc/board/rockchip/rockchip.rst
> +++ b/doc/board/rockchip/rockchip.rst
> @@ -152,7 +152,7 @@ List of mainline supported Rockchip boards:
>        - Pine64 QuartzPro64 (quartzpro64-rk3588)
>        - Radxa ROCK 5 ITX (rock-5-itx-rk3588)
>        - Radxa ROCK 5A (rock5a-rk3588s)
> -     - Radxa ROCK 5B (rock5b-rk3588)
> +     - Radxa ROCK 5B/5B+ (rock5b-rk3588)
>        - Radxa ROCK 5C (rock-5c-rk3588s)
>        - Rockchip Toybrick TB-RK3588X (toybrick-rk3588)
>        - Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588)

Re: [v2,0/2] rockchip: Add support for ROCK 5B+

[bryan]

Hi Jonas,

I tested your ROCK 5B+ patches and the results are below.

Hardware / build:
  - Board: Radxa ROCK 5B+ rev 1.2 (32 GB LPDDR5)
  - Toolchain: aarch64-linux-gnu-gcc 15.1.0
  - TPL: rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.19.bin
  - BL31: rk3588_bl31_v1.51.elf
  - Boot: microSD
  - U-Boot build: 2026.01-rc1-00252-g0afc36a2f4dc

Results:
  - Detected as “Radxa ROCK 5B+” (rk3588-rock-5b-plus.dtb)
  - SD and USB enumeration work correctly
  - Ethernet reports “No ethernet found” (GMAC node not yet enabled)

Full boot log attached below.

Tested-by: Bryan Hinton <bryan@bryanhinton.com>

Thanks,
Bryan

---
Boot log:

U-Boot 2026.01-rc1-00252-g0afc36a2f4dc (Nov 04 2025 - 15:52:02 -0600)

Model: Radxa ROCK 5B+
SoC:   RK3588
DRAM:  32 GiB (total 31.7 GiB)
Core:  380 devices, 34 uclasses, devicetree: separate
MMC:   mmc@fe2c0000: 1, mmc@fe2e0000: 0
Loading Environment from nowhere... OK
In:    serial@feb50000
Out:   serial@feb50000
Err:   serial@feb50000
Model: Radxa ROCK 5B+
SoC:   RK3588
Net:   No ethernet found.
Hit any key to stop autoboot: 0
=> env print fdtfile
fdtfile=rockchip/rk3588-rock-5b-plus.dtb
=> fdt print / model
No FDT memory address configured. Please configure
the FDT address via "fdt addr <address>" command.
Aborting!
=> fdt print / compatible
No FDT memory address configured. Please configure
the FDT address via "fdt addr <address>" command.
Aborting!
=> usb start
starting USB...
USB EHCI 1.00
USB OHCI 1.0
USB EHCI 1.00
USB OHCI 1.0
Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
Bus usb@fc800000: 1 USB Device(s) found
Bus usb@fc840000: 1 USB Device(s) found
Bus usb@fc880000: 1 USB Device(s) found
Bus usb@fc8c0000: 1 USB Device(s) found
Bus usb@fcd00000: 1 USB Device(s) found
Bus usb@fc400000: 1 USB Device(s) found
       scanning usb for storage devices... 0 Storage Device(s) found
=> mmc list
mmc@fe2c0000: 1
mmc@fe2e0000: 0
=> bdinfo
boot_params = 0x0000000000000000
DRAM bank   = 0x0000000000000000
-> start    = 0x0000000000200000
-> size     = 0x00000000efe00000
DRAM bank   = 0x0000000000000001
-> start    = 0x0000000100000000
-> size     = 0x00000002fc000000
DRAM bank   = 0x0000000000000002
-> start    = 0x00000003fc500000
-> size     = 0x0000000003a00000
DRAM bank   = 0x0000000000000003
-> start    = 0x0000000400000000
-> size     = 0x0000000400000000
flashstart  = 0x0000000000000000
flashsize   = 0x0000000000000000
flashoffset = 0x0000000000000000
baudrate    = 1500000 bps
relocaddr   = 0x00000000eff07000
reloc off   = 0x00000000ef507000
Build       = 64-bit
current eth = unknown
eth-1addr   = (not set)
IP addr     = <NULL>
fdt_blob    = 0x00000000edbe0a00
lmb_dump_all:
 memory.count = 0x4
 memory[0]	[0x200000-0xefffffff], 0xefe00000 bytes, flags: none
 memory[1]	[0x100000000-0x3fbffffff], 0x2fc000000 bytes, flags: none
 memory[2]	[0x3fc500000-0x3ffefffff], 0x3a00000 bytes, flags: none
 memory[3]	[0x400000000-0x7ffffffff], 0x400000000 bytes, flags: none
 reserved.count = 0x5
 reserved[0]	[0xecbdd000-0xecbdffff], 0x3000 bytes, flags: no-notify, no-overwrite
 reserved[1]	[0xecbe09f0-0xefffffff], 0x341f610 bytes, flags: no-overwrite
 reserved[2]	[0x100000000-0x3fbffffff], 0x2fc000000 bytes, flags: no-overwrite
 reserved[3]	[0x3fc500000-0x3ffefffff], 0x3a00000 bytes, flags: no-overwrite
 reserved[4]	[0x400000000-0x7ffffffff], 0x400000000 bytes, flags: no-overwrite
devicetree  = separate
serial addr = 0x00000000feb50000
 width      = 0x0000000000000004
 shift      = 0x0000000000000002
 offset     = 0x0000000000000000
 clock      = 0x00000000016e3600
arch_number = 0x0000000000000000
TLB addr    = 0x00000000efff0000
irq_sp      = 0x00000000edbe09f0
sp start    = 0x00000000edbe09f0
Early malloc usage: 2700 / 10000
=> fdt addr 0x00000000edbe0a00
Working FDT set to edbe0a00
=> fdt print / model
model = "Radxa ROCK 5B+"

Re: [PATCH v2 0/2] rockchip: Add support for ROCK 5B+

[FUKAUMI Naoki]

Hi Jonas,

On 8/2/25 02:09, Jonas Karlman wrote:
> This series add support for the ROCK 5B+ variant to the existing
> rock5b-rk3588 defconfig taget.
> 
> The ROCK 5B+ variant is detected based on DRAM type (LPDDR5) and SARADC
> channel 5, the read out value is expected to be close to 4095 (1.8v) on
> 5B+ variants.
> 
> Features tested on a ROCK 5B+ v1.2:
> - SD-card boot
> - eMMC boot
> - SPI flash boot
> - PCIe/NVMe
> - Ethernet
> - USB/TCPM

I also confirmed that the following things are working:
- uSD card (boot/mmc info)
- SPI flash (sf probe)
- PCIe (pci enum)
- NVMe (nvme scan)
- Ethernet (ping)
- USB (usb start)

Tested-by: FUKAUMI Naoki <naoki@radxa.com>

Best regards,

--
FUKAUMI Naoki
Radxa Computer (Shenzhen) Co., Ltd.

> Changes in v2:
> - Add a DRAM type check to detected ROCK 5B+ variant
> - Drop device tree patches merged with the v6.16-dts sync
> 
> Jonas Karlman (2):
>    rockchip: sdram: Add rockchip_sdram_type() helper
>    rockchip: rock5b-rk3588: Add support for ROCK 5B+
> 
>   arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi |  3 +
>   arch/arm/dts/rk3588-rock-5b-u-boot.dtsi      |  5 ++
>   arch/arm/include/asm/arch-rockchip/sdram.h   |  3 +
>   arch/arm/mach-rockchip/sdram.c               | 15 +++++
>   board/radxa/rock5b-rk3588/Kconfig            |  5 ++
>   board/radxa/rock5b-rk3588/MAINTAINERS        |  3 +-
>   board/radxa/rock5b-rk3588/rock5b-rk3588.c    | 63 ++++++++++++++++++++
>   configs/rock5b-rk3588_defconfig              |  1 +
>   doc/board/rockchip/rockchip.rst              |  2 +-
>   9 files changed, 97 insertions(+), 3 deletions(-)
>   create mode 100644 arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi
> Tested-by: Bryan Hinton <bryan@bryanhinton.com>