From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?iso-8859-1?Q?Robert_Deli=EBn?= Date: Mon, 11 Dec 2006 11:03:27 +0100 Subject: [U-Boot-Users] [PATCH] MIPS time.c fix Message-ID: <000001c71d0b$9a845cc0$dfdd9182@code1.emi.philips.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de > The above is not true for all MIPS. A lot (almost all) of older MIPS > parts run the cpu CP0 counter at half the core clock rate. Thanks for your feedback; I wasn't aware of this. I've encountered a couple of /2 constructions in some configurations, but I though that was just a quick fix that degrades the granularity of the timer by half in order to prevent overflows in net.c. > I would suggest changing CPU_CLOCK_RATE to CPU_CP0_COUNT_RATE since > they are not always the same. I have changed it to CFG_CP0_COUNT_RATE, if you don't mind. The IncaIP and Purple platform seem to have cores with half-speed COUNT registers so those have been fixed too. Behold the new patch ;-) -------------- next part -------------- A non-text attachment was scrubbed... Name: mips_timer2.diff Type: application/octet-stream Size: 6651 bytes Desc: not available Url : http://lists.denx.de/pipermail/u-boot/attachments/20061211/8d42666e/attachment.obj