From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Grab Date: Tue, 12 Jul 2005 17:25:15 +0200 Subject: AW: [U-Boot-Users] EMAC2 & EMAC3 operation on PPC 440GX In-Reply-To: <20050622125338.5577.qmail@web30302.mail.mud.yahoo.com> Message-ID: <000501c586f5$e7d4f550$f201a8c0@SN7606> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de >I'm also using the Marvel 88E1111 PHY with no >problems. Note that you must follow the reset >waveform exactly per the data sheet or the PHYs will >be in la la land. Hopefully the reset discrete is >connect to a GPIO pin. Since this PHY can not be >strapped for RGMII, you also must set register 20 to >0xce3 in your board specific initialization followed >by a soft reset. The Phy is strapped for RGMII to Copper mode HWCFG_MODE[3:0]=1011 with auto negotiation, all capabilities, prefer slave selected. The driver detects the PHY and read properly out the speed and duplex. I don?t see an issue with it?! I found an hardware issue on my board. The reference clock GMCRefClk was missing. So no TxClk could be generated from the EMAC. But now i have trouble with the ethernet driver. After setting ethernet device to ETH2 with "setenv ethact ppc_440x_eth2" and then ping a network device i got stuck. Debugging the code shows me that a external interrupt is coming with uic1msr=A0000000. This means that UIC_MS and UIC_MRDE is pending. But it can?t be handled in enetInt because the second if clause is not matching and the functions returns (see following code). This results in an endless loop of the interrupt handler. Do someone have a hint why UIC_MS and UIC_MRDE comes up and how i can solve my problem? Another strange thing is that i have the waveform of the GMC0TxClk on all GMC0TxData lines. Same behavior on second line. Is this normal for the PPC 440 GX EMAC? if (!(my_uic0msr & (UIC_MRE | UIC_MTE)) && !(my_uic1msr & (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE))) { /* not for us */ return (rc); } #if defined (CONFIG_440_GX) if (!(my_uic0msr & (UIC_MRE | UIC_MTE)) && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) { /* not for us */ return (rc); } #endif u-boot output: U-Boot relocated to 1ffc2000 Net: Install interrupt for vector 32 ==> 1ffc648c Install interrupt for vector 10 ==> 1ffc648c Install interrupt for vector 11 ==> 1ffc648c Install interrupt for vector 33 ==> 1ffc648c Install interrupt for vector 34 ==> 1ffc648c ppc_440x_eth0, ppc_440x_eth1, ppc_440x_eth2, ppc_440x_eth3 BEDBUG:ready => setenv ethact ppc_440x_eth2 => ping 192.168.0.121 Trying ppc_440x_eth2 About preceeding transfer (eth2): - Sent packet number 0 - Received packet number 0 - Handled packet number 0 Waiting for PHY auto negotiation to complete.. done Install interrupt for vector 65 ==> 1ffc648c Install interrupt for vector 64 ==> 1ffc648c Which settings did you made in u-boot to get your ethernet functioning with your board? Maybe it helps me to find my problem... Thx for your help, David --- "Travis B. Sawyer" wrote: > David Grab wrote: > > Hello, > > > > as mentioned before i?m using two Marvel 88E1111 > PHY on my PPC440GX Board. > > They are configured as a RGMII to copper interface > for use with EMAC 2 & 3. > > So now i?m in trouble with the configuration of > the network. After booting i > > set with "setenv ethact ppc_440x_eth2" EMAC2 for > networking. After that i > > try a "ping" to know if network is working. > Reading the speed and duplex > > from PHY works, but after that i got in an endless > loop. I figured out, that > > no interrupt is recognized and in 440gx_enet.c in > ppc_440x_eth_init the > > default configuration of the interrupt handler is > for ETH0: > > > > irq_install_handler (VECNUM_EWU0 + (hw_p->devnum > * 2), > > (interrupt_handler_t *) enetInt, dev); > > irq_install_handler (VECNUM_ETH0 + (hw_p->devnum > * 2), > > (interrupt_handler_t *) enetInt, dev); > > > > so i changed it as following... > > > > irq_install_handler (VECNUM_EWU2 + (hw_p->devnum > * 2), > > (interrupt_handler_t *) enetInt, dev); > > irq_install_handler (VECNUM_ETH2 + (hw_p->devnum > * 2), > > (interrupt_handler_t *) enetInt, dev); > > You shouldn't need to do this. I have 3 different > boards that work fine > with emac2 & emac3. > > > > > > and added in vecnum.h these lines: > > > > #define VECNUM_ETH2 (64 + 0) /* Ethernet > 0 interrupt status */ > > #define VECNUM_EWU2 (64 + 1) /* Ethernet > 0 wakeup */ > > > > But this didn?t solve the problem. Actually i also > couldn?t get the TxCLK > > work on my RGMII Bridge and i don?t know why. > > I saw the note yesterday about the etch length. The > hw guys didn't want > to route the 13" of extra etch so I whack a reg in > our phy to tell it > to skew the clock. > > -travis > > > ------------------------------------------------------- > SF.Net email is sponsored by: Discover Easy Linux > Migration Strategies > from IBM. Find simple to follow Roadmaps, > straightforward articles, > informative Webcasts and more! Get everything you > need to get up to > speed, fast. > http://ads.osdn.com/?ad_id=7477&alloc_id=16492&op=click > _______________________________________________ > U-Boot-Users mailing list > U-Boot-Users at lists.sourceforge.net >