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Thu, 11 Aug 2022 14:50:10 +0900 (KST) Received: from jh80chung01 (unknown [10.113.111.84]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20220811055010epsmtip1f2e5fbf4fc28f4c03626c6628e5426dc~KNGKaq5bM1703817038epsmtip1U; Thu, 11 Aug 2022 05:50:10 +0000 (GMT) From: To: "'Weijie Gao'" , Cc: "'GSS_MTK_Uboot_upstream'" , "'Peng Fan'" In-Reply-To: Subject: RE: [PATCH 05/31] mmc: mediatek: add support for MediaTek MT7891/MT7986 SoCs Date: Thu, 11 Aug 2022 14:50:10 +0900 Message-ID: <000701d8ad46$38041fe0$a80c5fa0$@samsung.com> X-Mailer: Microsoft Outlook 15.0 Content-Language: ko Thread-Index: AQHLHgvcCliuroO9T0fJFH3aqMQAlwImXx/xAn/cRAitnx4jwA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrGKsWRmVeSWpSXmKPExsWy7bCmru7kGV+SDDZ95rRYvaiB2eLHqi+s Fm/3drJbNLw4zezA4nH2zg5Gj5aT+1k8Nr7bwRTAHJVtk5GamJJapJCal5yfkpmXbqvkHRzv HG9qZmCoa2hpYa6kkJeYm2qr5OIToOuWmQO0TkmhLDGnFCgUkFhcrKRvZ1OUX1qSqpCRX1xi q5RakJJTYFqgV5yYW1yal66Xl1piZWhgYGQKVJiQnbH0t3LBRfWKs90eDYxzFboYOTkkBEwk vh5az9rFyMUhJLCDUWLH3CVQzidGiQWXLrBBOJ8ZJQ5sOscC0zJrBUzLLkaJnuaDUFUvgZzt 69hBqtgE5CRWXD8JZHNwiAi4SJy4FQgSZhZIl+h+MA1sEKdAnMSWCX1g5cIC4RKfPnYxgdgs AqoSEz+sYwaxeQUsJT5M6WSDWKwgsfvTUVaIOSISszvbwGpEBJwkFu19wA5yg4TAIXaJy1t7 wPZKAO1tfKEP0Sss8er4FnYIW0riZX8bVH0zo8TSJQdZIZweRol/DdehthlL7F86mQlkELOA psT6XVCDFCV2/p7LCHEEn8S7rz2sELt4JTrahCBKVCQuvX7JBLPr7pP/UCUeEqf2SkKC6hGj xOwpE9kmMCrMQvLOLIRlCxiZVjGKpRYU56anFhsWGMHjNDk/dxMjOMFpme1gnPT2g94hRiYO xkOMEhzMSiK8ZYs+JwnxpiRWVqUW5ccXleakFh9iNAUG6kRmKdHkfGCKzSuJNzSxNDAxMzI2 sTA0M1QS51017XSikEB6YklqdmpqQWoRTB8TB6dUA5N66S+534d2rFROyPtjpdurzvFgq8tD jwKtfye5lixy1XBLXO2191bqld6NoezprQeWlkS+35qsuaVut8z+i0vTcr/dmdex4OMz++D2 UzVKwt2l7ltmbnfb5Vt80SBUzVv1xyHDfa7PWxYK8r4ptM6awnpo6SppxWndT3c57/OSmr// pE76Vx9RGfGLsofZ17zMfh15cdWWpQXRYev1vmfO/cckMcP4wRKtJ+uPyzdMNjn7NkQi/9jC 77/LNsy7985zg6eyToqxy5wjk31D56apRnOEFzw6lqNaFXQml9tiiYPGo3kzA9ynmOiGFhhy PT8y92PG4s+LhAxXmB1PnrDz0tE/h5aFr/8aM/P7GpMoJZbijERDLeai4kQAwBgPiPkDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprPLMWRmVeSWpSXmKPExsWy7bCSnO6kGV+SDPY/N7ZYvaiB2eLHqi+s Fm/3drJbNLw4zezA4nH2zg5Gj5aT+1k8Nr7bwRTAHMVlk5Kak1mWWqRvl8CVsfS3csFF9Yqz 3R4NjHMVuhg5OSQETCRmrVjP2sXIxSEksINR4vGOPawQCSmJz0+nsnUxcgDZwhKHDxdD1Dxn lJjRtR6shk1AXmLzoQZ2EFtEwE1i95FvjCA2s0C6RPeFTWA1QgL3GCX+vPcCsTkF4iS2TOhj B5kpLBAq8fi8FEiYRUBVYuKHdcwgNq+ApcSHKZ1sECcoSOz+dJQVYqSIxOzONmaIVU4Si/Y+ YJ/AKDALSWoBI+MqRsnUguLc9NxiwwKjvNRyveLE3OLSvHS95PzcTYzgMNTS2sG4Z9UHvUOM TByMhxglOJiVRHjLFn1OEuJNSaysSi3Kjy8qzUktPsQozcGiJM57oetkvJBAemJJanZqakFq EUyWiYNTqoFpzR15nuorS85kH6854XGo5FrL9vPf5jC6lnZ4buNyn3uh0ZR7jsNGj891z/Wy pxqJt7RNrD7+8NfhP2e63VUa+iSyo9W43A5rfIo1T9HQ2p0QGvqolTnx7Af/5BLVDwff+mbP 4jo3dYLAkb0cWwP7eN5te/uUU1/4Vm+7oDH//Np903gOey64kzbtXGT0qROFjCEihtVrZv6U X/lOYCe73eE1dVylHxhXzPr42/KA7M3fTx6/sMzg+LZHluEf8+VandsV5z6urbDst7/cnMDn r/7s0dWY5VeTxIRDIvJff+PfzXX+hnthvHdVom+vxgsX3fMTmvty9df5rWh3/hqt3Nx+q+GI 0bs3b+RC5x9WYinOSDTUYi4qTgQA90k4C7ICAAA= X-CMS-MailID: 20220811055010epcas1p36582767bc3936feb378e9f6d3d8c9df9 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: SVC_REQ_APPROVE CMS-TYPE: 101P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220804033524epcas1p20e168b5d50b20b0bad5017d1590a6ebe References: X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean > -----Original Message----- > From: Weijie Gao [mailto:weijie.gao@mediatek.com] > Sent: Thursday, August 4, 2022 12:35 PM > To: u-boot@lists.denx.de > Cc: GSS_MTK_Uboot_upstream; Peng Fan; Jaehoon Chung; Weijie Gao > Subject: [PATCH 05/31] mmc: mediatek: add support for MediaTek MT7891/MT7986 SoCs > > This patch adds eMMC and SDXC support for MediaTek MT7981/MT7986 SoCs > > Signed-off-by: Weijie Gao Reviewed-by: Jaehoon Chung Best Regards, Jaehoon Chung > --- > drivers/mmc/mtk-sd.c | 68 ++++++++++++++++++++++++++++++++++---------- > 1 file changed, 53 insertions(+), 15 deletions(-) > > diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c > index e61e8cf4b9..b206b0a085 100644 > --- a/drivers/mmc/mtk-sd.c > +++ b/drivers/mmc/mtk-sd.c > @@ -1496,7 +1496,12 @@ static void msdc_init_hw(struct msdc_host *host) > /* Enable data & cmd interrupts */ > writel(DATA_INTS_MASK | CMD_INTS_MASK, &host->base->msdc_inten); > > - writel(0, tune_reg); > + if (host->top_base) { > + writel(0, &host->top_base->emmc_top_control); > + writel(0, &host->top_base->emmc_top_cmd); > + } else { > + writel(0, tune_reg); > + } > writel(0, &host->base->msdc_iocon); > > if (host->r_smpl) > @@ -1507,9 +1512,14 @@ static void msdc_init_hw(struct msdc_host *host) > writel(0x403c0046, &host->base->patch_bit0); > writel(0xffff4089, &host->base->patch_bit1); > > - if (host->dev_comp->stop_clk_fix) > + if (host->dev_comp->stop_clk_fix) { > clrsetbits_le32(&host->base->patch_bit1, MSDC_PB1_STOP_DLY_M, > 3 << MSDC_PB1_STOP_DLY_S); > + clrbits_le32(&host->base->sdc_fifo_cfg, > + SDC_FIFO_CFG_WRVALIDSEL); > + clrbits_le32(&host->base->sdc_fifo_cfg, > + SDC_FIFO_CFG_RDVALIDSEL); > + } > > if (host->dev_comp->busy_check) > clrbits_le32(&host->base->patch_bit1, (1 << 7)); > @@ -1544,15 +1554,28 @@ static void msdc_init_hw(struct msdc_host *host) > } > > if (host->dev_comp->data_tune) { > - setbits_le32(tune_reg, > - MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL); > - clrsetbits_le32(&host->base->patch_bit0, > - MSDC_INT_DAT_LATCH_CK_SEL_M, > - host->latch_ck << > - MSDC_INT_DAT_LATCH_CK_SEL_S); > + if (host->top_base) { > + setbits_le32(&host->top_base->emmc_top_control, > + PAD_DAT_RD_RXDLY_SEL); > + clrbits_le32(&host->top_base->emmc_top_control, > + DATA_K_VALUE_SEL); > + setbits_le32(&host->top_base->emmc_top_cmd, > + PAD_CMD_RD_RXDLY_SEL); > + } else { > + setbits_le32(tune_reg, > + MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL); > + clrsetbits_le32(&host->base->patch_bit0, > + MSDC_INT_DAT_LATCH_CK_SEL_M, > + host->latch_ck << > + MSDC_INT_DAT_LATCH_CK_SEL_S); > + } > } else { > /* choose clock tune */ > - setbits_le32(tune_reg, MSDC_PAD_TUNE_RXDLYSEL); > + if (host->top_base) > + setbits_le32(&host->top_base->emmc_top_control, > + PAD_RXDLY_SEL); > + else > + setbits_le32(tune_reg, MSDC_PAD_TUNE_RXDLYSEL); > } > > if (host->dev_comp->builtin_pad_ctrl) { > @@ -1604,12 +1627,6 @@ static void msdc_init_hw(struct msdc_host *host) > clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M, > 3 << SDC_CFG_DTOC_S); > > - if (host->dev_comp->stop_clk_fix) { > - clrbits_le32(&host->base->sdc_fifo_cfg, > - SDC_FIFO_CFG_WRVALIDSEL); > - clrbits_le32(&host->base->sdc_fifo_cfg, > - SDC_FIFO_CFG_RDVALIDSEL); > - } > > host->def_tune_para.iocon = readl(&host->base->msdc_iocon); > host->def_tune_para.pad_tune = readl(&host->base->pad_tune); > @@ -1792,6 +1809,25 @@ static const struct msdc_compatible mt7623_compat = { > .enhance_rx = false > }; > > +static const struct msdc_compatible mt7986_compat = { > + .clk_div_bits = 12, > + .pad_tune0 = true, > + .async_fifo = true, > + .data_tune = true, > + .busy_check = true, > + .stop_clk_fix = true, > + .enhance_rx = true, > +}; > + > +static const struct msdc_compatible mt7981_compat = { > + .clk_div_bits = 12, > + .pad_tune0 = true, > + .async_fifo = true, > + .data_tune = true, > + .busy_check = true, > + .stop_clk_fix = true, > +}; > + > static const struct msdc_compatible mt8512_compat = { > .clk_div_bits = 12, > .pad_tune0 = true, > @@ -1824,6 +1860,8 @@ static const struct udevice_id msdc_ids[] = { > { .compatible = "mediatek,mt7621-mmc", .data = (ulong)&mt7621_compat }, > { .compatible = "mediatek,mt7622-mmc", .data = (ulong)&mt7622_compat }, > { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat }, > + { .compatible = "mediatek,mt7986-mmc", .data = (ulong)&mt7986_compat }, > + { .compatible = "mediatek,mt7981-mmc", .data = (ulong)&mt7981_compat }, > { .compatible = "mediatek,mt8512-mmc", .data = (ulong)&mt8512_compat }, > { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat }, > { .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat }, > -- > 2.17.1