[U-Boot-Users] Debugging 85xx eTSEC's

[C Balakumar <c.balakumar@gdatech.co.in>]

Hi Robert,

Check the MDIO and MDC lines on your custom board.

It seems like you are not able to read the PHY ID.
And also check the phy address configuration in the u-boot board config 
file.

-Balakumar Chinnusamy

----- Original Message ----- 
From: "robert lazarski" <robertlazarski@gmail.com>
To: <u-boot-users@lists.sourceforge.net>
Sent: Friday, October 26, 2007 2:27 PM
Subject: [U-Boot-Users] Debugging 85xx eTSEC's


> Hi all,
>
> Using u-boot from the latest git, I'm trying to debug our phy's on our
> custom 8548 board. Our eTSEC0 / eTSEC1 are mavell 88E1121 and eTSEC2 /
> eTSEC3 are 88E1111 - I'm trying to debug eTSEC2 since the 88E1111
> seems to be supported by u-boot. I get this output from the serial
> port in debug mode:
>
> eTSEC1 is in sgmii mode.
> eTSEC2 is in sgmii mode.
> eTSEC3 is in sgmii mode.
> eTSEC4 is in sgmii mode.
>
> Net:   eTSEC0: PHY is Unknown/Generic PHY (ffffffff)
> eTSEC1: PHY is Unknown/Generic PHY (ffffffff)
> eTSEC2: PHY is Unknown/Generic PHY (ffffffff)
> eTSEC3: PHY is Unknown/Generic PHY (ffffffff)
> eTSEC0, eTSEC1, eTSEC2, eTSEC3
>
> Where 'is in sgmii mode' comes from standard 85xx stuff: I can't ping
> when setting ethact to be eTSEC2, and I get this when running 'mii
> info'  :
>
> => mii info
> PHY_PHYIDR2 @ 0x0 = 0xffff
> PHY_PHYIDR2 @ 0x1 = 0xffff
> PHY_PHYIDR2 @ 0x2 = 0xffff
> PHY_PHYIDR2 @ 0x3 = 0xffff
> Can't read PHY at address 4
> ...
>
> My defines are:
>
> #if defined(CONFIG_TSEC_ENET)
>
> #ifndef CONFIG_NET_MULTI
> #define CONFIG_NET_MULTI        1
> #endif
>
> #define CONFIG_MII              1       /* MII PHY management */
> #define CONFIG_TSEC1    1
> #define CONFIG_TSEC1_NAME       "eTSEC0"
> #define CONFIG_TSEC2    1
> #define CONFIG_TSEC2_NAME       "eTSEC1"
> #define CONFIG_TSEC3    1
> #define CONFIG_TSEC3_NAME       "eTSEC2"
> #define CONFIG_TSEC4    1
> #define CONFIG_TSEC4_NAME       "eTSEC3"
> #undef CONFIG_MPC85XX_FEC
>
> #define TSEC1_PHY_ADDR          0
> #define TSEC2_PHY_ADDR          1
> #define TSEC3_PHY_ADDR          2
> #define TSEC4_PHY_ADDR          3
>
> #define TSEC1_PHYIDX            0
> #define TSEC2_PHYIDX            0
> #define TSEC3_PHYIDX            0
> #define TSEC4_PHYIDX            0
> #define TSEC1_FLAGS             TSEC_GIGABIT
> #define TSEC2_FLAGS             TSEC_GIGABIT
> #define TSEC3_FLAGS             TSEC_GIGABIT
> #define TSEC4_FLAGS             TSEC_GIGABIT
>
> /* Options are: eTSEC[0-3] */
> #define CONFIG_ETHPRIME         "eTSEC0"
> #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex 
> detection */
> #endif  /* CONFIG_TSEC_ENET */
>
> Any ideas?
> Robert
>
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