[U-Boot] MPC8313 DDR2 configuration

[Scott Larson <slarson@a2etech.com>]

Hi Paul,
Thanks for the reply. I am very new to the 32bit world.

Currently I am using the files for the MPC8313ERDB as a basis.
I have altered srdam.c and my version of MPC8313ERDB.h to reflect my new
DDR2 layout. I have 4 ICs, 2 on each CS.

The settings you mentioned below are..
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
.. in my version of MPC8313ERDB.h file.
I believe these are referring to the eLocalBus base addresses for Local Bus
Chip Selects?

My DDR2 ram is using the MPC8313 DDR memory controller and I have added.....

#define CONFIG_SYS_DDR_CS1_CONFIG	(CSCONFIG_EN \
				| CSCONFIG_ODT_RD_ONLY_CURRENT \
				| CSCONFIG_ODT_WR_ONLY_CURRENT \
				| CSCONFIG_BANK_BIT_3 \
				| CSCONFIG_ROW_BIT_14 \
				| CSCONFIG_COL_BIT_10)
				/* 0x80114202 */
.... to my version of the MPC8313ERDB.h file.

And, I have altered sdram.c to look like this...

	/* Local address Window for DDR CS0 */
	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);

	/* Local address Window for DDR CS1 */
	im->sysconf.ddrlaw[1].bar = (CONFIG_SYS_DDR_SDRAM_BASE + msize) &
0xfffff000;
	im->sysconf.ddrlaw[1].ar = LBLAWAR_EN | (msize_log2 - 1);
	
	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;

	/*
	 * Erratum DDR3 requires a 50ms delay after clearing
DDRCDR[DDR_cfg],
	 * or the DDR2 controller may fail to initialize correctly.
	 */
	__udelay(50000);

#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
#warning Chip select bounds is only configurable in 16MB increments
#endif
	/* Set CS bounds for CS0 */
	im->ddr.csbnds[0].csbnds =
		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA)
|
		(((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >>
CSBNDS_EA_SHIFT) &
			CSBNDS_EA);
	
	/* Set CS bounds for CS1 */	
	im->ddr.csbnds[1].csbnds =
		(((CONFIG_SYS_DDR_SDRAM_BASE + msize) >> CSBNDS_SA_SHIFT) &
CSBNDS_SA) |
		(((CONFIG_SYS_DDR_SDRAM_BASE + (2*msize) - 1) >>
CSBNDS_EA_SHIFT) &
			CSBNDS_EA);
			
	/* Enable bank 0. */
	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;

	/* Enable bank 1. */
	im->ddr.cs_config[1] =  CONFIG_SYS_DDR_CS1_CONFIG;

My hardware has not been delivered yet so I can't test the modifications!

So I don't know if they might work?!

Best Regards,
Scott


-----Original Message-----
From: paul.gortmaker@gmail.com [mailto:paul.gortmaker at gmail.com] On Behalf
Of Paul Gortmaker
Sent: 08 February 2012 04:46
To: Scott Larson
Cc: u-boot at lists.denx.de
Subject: Re: [U-Boot] MPC8313 DDR2 configuration

On Tue, Feb 7, 2012 at 11:52 AM, Scott Larson <slarson@a2etech.com> wrote:
> Hi,
>
> Looking for help on DDR2 configuration in u-boot.
>
>
>
> I have the MPC8313ERDB from Freescale. It has 128Mbytes of DDR2 ram. 
> The existing 128MByte that uses only CS0.
>
>
>
> I have a new board design to bring up.
>
> The timing parameters are all ok but I need some guidance on changing 
> the settings to suit my memory configuration.
>
>
>
> My board has 512Mbytes on CS0 and 512Mbytes on CS1.
>
> Changes need to be made to files MPC8313ERDB.h and sdram.c

SODIMM with SPD?  Autoconfig with CONFIG_SPD_EEPROM is nice compared to hard
coding values, if you can use it.  I'm pretty sure it works fine on sbc8349
board.

>
>
>
> I have made all the row and column size and block address pin settings 
> ok. I have set DDR size to 512Mbytes (per Chip Select).
>
>
>
> I need some guidance on the setting for CS1 bank of ram.

Have you created the CONFIG_SYS_BR1_PRELIM and the CONFIG_SYS_OR1_PRELIM
defines in your board header?

If you copied these from a reference platform, they may still be populated
with settings appropriate for flash up at the top of memory instead of DDR2
settings for your 2nd bank...

P.

>
>
>
> thanks
>
> Scott
>
>
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