cache: l2x0: Fix incorrect behavior if the latency is 1 cycle

cache: l2x0: Fix incorrect behavior if the latency is 1 cycle

[haifeng.li]

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According to the PL310 TRM, 0 in the latency fields(setup/read/write)
indicates 1 cycle of latency for Tag and Data RAM latency control
registers. If we want to set 1 cycle of latency, we need to clear
the field actually. The TRM is as below:
https://developer.arm.com/documentation/ddi0246/h/programmers-model/register
-descriptions/tag-and-data-ram-latency-control-registers

Signed-off-by: Haifeng Li <haifeng.li@timesintelli.com>

drivers/cache/cache-l2x0.c | 6 ++++++
1 file changed, 6 insertions(+)

[-- Attachment #2: 0001-cache-l2x0-Fix-incorrect-behavior-if-the-latency-is-.patch --]
[-- Type: application/octet-stream, Size: 1878 bytes --]

From b1d3be4eb85bd38633c24f3363ea86730f667b2d Mon Sep 17 00:00:00 2001
From: Haifeng Li <haifeng.li@timesintelli.com>
Date: Fri, 18 Mar 2022 19:09:53 +0800
Subject: [PATCH 1/1] cache: l2x0: Fix incorrect behavior if the latency is 1
 cycle

According to the PL310 TRM, 0 in the latency fields(setup/read/write)
indicates 1 cycle of latency for Tag and Data RAM latency control
registers. If we want to set 1 cycle of latency, we need to clear
the field actually. The TRM is as below:
https://developer.arm.com/documentation/ddi0246/h/programmers-model/register-descriptions/tag-and-data-ram-latency-control-registers

Signed-off-by: Haifeng Li <haifeng.li@timesintelli.com>
---
 drivers/cache/cache-l2x0.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c
index a1556fbf17..49f16519ba 100644
--- a/drivers/cache/cache-l2x0.c
+++ b/drivers/cache/cache-l2x0.c
@@ -40,6 +40,9 @@ static void l2c310_of_parse_and_init(struct udevice *dev)
 
 	saved_reg = readl(&regs->pl310_tag_latency_ctrl);
 	if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3))
+		clrbits_le32(&saved_reg, L310_LATENCY_CTRL_WR(7) |
+				L310_LATENCY_CTRL_RD(7) |
+				L310_LATENCY_CTRL_SETUP(7));
 		saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
 			     L310_LATENCY_CTRL_WR(tag[1] - 1) |
 			     L310_LATENCY_CTRL_SETUP(tag[2] - 1);
@@ -47,6 +50,9 @@ static void l2c310_of_parse_and_init(struct udevice *dev)
 
 	saved_reg = readl(&regs->pl310_data_latency_ctrl);
 	if (!dev_read_u32_array(dev, "arm,data-latency", tag, 3))
+		clrbits_le32(&saved_reg, L310_LATENCY_CTRL_WR(7) |
+				L310_LATENCY_CTRL_RD(7) |
+				L310_LATENCY_CTRL_SETUP(7));
 		saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
 			     L310_LATENCY_CTRL_WR(tag[1] - 1) |
 			     L310_LATENCY_CTRL_SETUP(tag[2] - 1);
-- 
2.17.1

Re: cache: l2x0: Fix incorrect behavior if the latency is 1 cycle

[Haifeng Li]

please ignore this email. I will re-send it with patch inline.

Thanks,
Haifeng.
------------------------------------------------------------------
From:Haifeng Li <haifeng.li@timesintelli.com>
Sent At:2022 Mar. 18 (Fri.) 19:28
To:dinguyen <dinguyen@kernel.org>; u-boot <u-boot@lists.denx.de>
Cc:Haifeng Li <haifeng.li@timesintelli.com>
Subject:cache: l2x0: Fix incorrect behavior if the latency is 1 cycle

According to the PL310 TRM, 0 in the latency fields(setup/read/write)
indicates 1 cycle of latency for Tag and Data RAM latency control
registers. If we want to set 1 cycle of latency, we need to clear
the field actually. The TRM is as below:
https://developer.arm.com/documentation/ddi0246/h/programmers-model/register
-descriptions/tag-and-data-ram-latency-control-registers

Signed-off-by: Haifeng Li <haifeng.li@timesintelli.com>

drivers/cache/cache-l2x0.c | 6 ++++++
1 file changed, 6 insertions(+)