From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2322DC433F5 for ; Fri, 18 Mar 2022 12:41:37 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8E1F883CF7; Fri, 18 Mar 2022 13:41:30 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=timesintelli.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 7BD6281DD3; Fri, 18 Mar 2022 12:29:17 +0100 (CET) Received: from out29-197.mail.aliyun.com (out29-197.mail.aliyun.com [115.124.29.197]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id F286B80F92 for ; Fri, 18 Mar 2022 12:29:11 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=timesintelli.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=haifeng.li@timesintelli.com X-Alimail-AntiSpam: AC=CONTINUE; BC=0.3668395|-1; BR=01201311R941S13rulernew998_84748_2000303; CH=blue; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.428828-0.00185156-0.569321; FP=0|0|0|0|0|0|0|0; HT=ay29a033018047202; MF=haifeng.li@timesintelli.com; NM=1; PH=DS; RN=3; RT=3; SR=0; TI=SMTPD_---.N7PeWAA_1647602933; Received: from XTZJ20210422GJ(mailfrom:haifeng.li@timesintelli.com fp:SMTPD_---.N7PeWAA_1647602933) by smtp.aliyun-inc.com(33.37.75.176); Fri, 18 Mar 2022 19:28:53 +0800 From: To: , Cc: Subject: cache: l2x0: Fix incorrect behavior if the latency is 1 cycle Date: Fri, 18 Mar 2022 19:28:52 +0800 Message-ID: <003001d83abb$586fd8d0$094f8a70$@timesintelli.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_NextPart_000_0031_01D83AFE.66933FE0" X-Mailer: Microsoft Outlook 16.0 Thread-Index: Adg6utPBVcVMvxNBRxCgLJnDe1fVFQ== Content-Language: zh-cn X-Mailman-Approved-At: Fri, 18 Mar 2022 13:41:28 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean This is a multipart message in MIME format. ------=_NextPart_000_0031_01D83AFE.66933FE0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit According to the PL310 TRM, 0 in the latency fields(setup/read/write) indicates 1 cycle of latency for Tag and Data RAM latency control registers. If we want to set 1 cycle of latency, we need to clear the field actually. The TRM is as below: https://developer.arm.com/documentation/ddi0246/h/programmers-model/register -descriptions/tag-and-data-ram-latency-control-registers Signed-off-by: Haifeng Li drivers/cache/cache-l2x0.c | 6 ++++++ 1 file changed, 6 insertions(+) ------=_NextPart_000_0031_01D83AFE.66933FE0 Content-Type: application/octet-stream; name="0001-cache-l2x0-Fix-incorrect-behavior-if-the-latency-is-.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="0001-cache-l2x0-Fix-incorrect-behavior-if-the-latency-is-.patch" >From b1d3be4eb85bd38633c24f3363ea86730f667b2d Mon Sep 17 00:00:00 2001=0A= From: Haifeng Li =0A= Date: Fri, 18 Mar 2022 19:09:53 +0800=0A= Subject: [PATCH 1/1] cache: l2x0: Fix incorrect behavior if the latency = is 1=0A= cycle=0A= =0A= According to the PL310 TRM, 0 in the latency fields(setup/read/write)=0A= indicates 1 cycle of latency for Tag and Data RAM latency control=0A= registers. If we want to set 1 cycle of latency, we need to clear=0A= the field actually. The TRM is as below:=0A= https://developer.arm.com/documentation/ddi0246/h/programmers-model/regis= ter-descriptions/tag-and-data-ram-latency-control-registers=0A= =0A= Signed-off-by: Haifeng Li =0A= ---=0A= drivers/cache/cache-l2x0.c | 6 ++++++=0A= 1 file changed, 6 insertions(+)=0A= =0A= diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c=0A= index a1556fbf17..49f16519ba 100644=0A= --- a/drivers/cache/cache-l2x0.c=0A= +++ b/drivers/cache/cache-l2x0.c=0A= @@ -40,6 +40,9 @@ static void l2c310_of_parse_and_init(struct udevice = *dev)=0A= =0A= saved_reg =3D readl(®s->pl310_tag_latency_ctrl);=0A= if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3))=0A= + clrbits_le32(&saved_reg, L310_LATENCY_CTRL_WR(7) |=0A= + L310_LATENCY_CTRL_RD(7) |=0A= + L310_LATENCY_CTRL_SETUP(7));=0A= saved_reg |=3D L310_LATENCY_CTRL_RD(tag[0] - 1) |=0A= L310_LATENCY_CTRL_WR(tag[1] - 1) |=0A= L310_LATENCY_CTRL_SETUP(tag[2] - 1);=0A= @@ -47,6 +50,9 @@ static void l2c310_of_parse_and_init(struct udevice = *dev)=0A= =0A= saved_reg =3D readl(®s->pl310_data_latency_ctrl);=0A= if (!dev_read_u32_array(dev, "arm,data-latency", tag, 3))=0A= + clrbits_le32(&saved_reg, L310_LATENCY_CTRL_WR(7) |=0A= + L310_LATENCY_CTRL_RD(7) |=0A= + L310_LATENCY_CTRL_SETUP(7));=0A= saved_reg |=3D L310_LATENCY_CTRL_RD(tag[0] - 1) |=0A= L310_LATENCY_CTRL_WR(tag[1] - 1) |=0A= L310_LATENCY_CTRL_SETUP(tag[2] - 1);=0A= -- =0A= 2.17.1=0A= =0A= ------=_NextPart_000_0031_01D83AFE.66933FE0--