[PATCH 0/6] riscv: adds T-Head C9xx basic and GMAC support.

[PATCH 0/6] riscv: adds T-Head C9xx basic and GMAC support.

[wefu]

From: Wei Fu <wefu@redhat.com>

This patchset adds T-Head C9xx basic support in arch/riscv/,
updates TH1520 Soc/Lichee Pi4A dts files for GMAC support.
Also enable designware ethernet & realtek phy in default configs,
and some boot env option for booting linux from Ethernet. 

Signed-off-by: Wei Fu <wefu@redhat.com>
Co-authored-by: Yixun Lan <dlan@gentoo.org>

Wei Fu (6):
  cpu: add t-head's c9xx
  riscv/dts: add gmac node for th1520.
  riscv/dts: add gmac node for lichee-pi-4a
  net/designware: add compatible for "snps,dwmac"
  config/th1520_lpi4a_defconfig:enable designware ethernet & realtek phy
  config/th1520_lpi4a.h: add more env option for booting linux

 arch/riscv/Kconfig                     |  1 +
 arch/riscv/cpu/c9xx/Kconfig            | 12 ++++++
 arch/riscv/cpu/c9xx/Makefile           |  5 +++
 arch/riscv/cpu/c9xx/cpu.c              | 51 ++++++++++++++++++++++++++
 arch/riscv/cpu/c9xx/dram.c             | 36 ++++++++++++++++++
 arch/riscv/dts/th1520-lichee-pi-4a.dts |  5 +++
 arch/riscv/dts/th1520.dtsi             | 33 +++++++++++++++++
 arch/riscv/include/asm/csr.h           |  2 +
 board/thead/th1520_lpi4a/Kconfig       |  3 +-
 configs/th1520_lpi4a_defconfig         |  8 +++-
 drivers/net/designware.c               |  1 +
 include/configs/th1520_lpi4a.h         | 12 ++++++
 12 files changed, 166 insertions(+), 3 deletions(-)
 create mode 100644 arch/riscv/cpu/c9xx/Kconfig
 create mode 100644 arch/riscv/cpu/c9xx/Makefile
 create mode 100644 arch/riscv/cpu/c9xx/cpu.c
 create mode 100644 arch/riscv/cpu/c9xx/dram.c

-- 
2.44.0

[PATCH 1/6] cpu: add t-head's c9xx

[wefu]

From: Wei Fu <wefu@redhat.com>

Signed-off-by: Wei Fu <wefu@redhat.com>
Co-authored-by: Yixun Lan <dlan@gentoo.org>
---
 arch/riscv/Kconfig               |  1 +
 arch/riscv/cpu/c9xx/Kconfig      | 12 ++++++++
 arch/riscv/cpu/c9xx/Makefile     |  5 ++++
 arch/riscv/cpu/c9xx/cpu.c        | 51 ++++++++++++++++++++++++++++++++
 arch/riscv/cpu/c9xx/dram.c       | 36 ++++++++++++++++++++++
 arch/riscv/include/asm/csr.h     |  2 ++
 board/thead/th1520_lpi4a/Kconfig |  3 +-
 7 files changed, 109 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ac52c5e6da..ac3b802abe 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -97,6 +97,7 @@ source "arch/riscv/cpu/fu540/Kconfig"
 source "arch/riscv/cpu/fu740/Kconfig"
 source "arch/riscv/cpu/generic/Kconfig"
 source "arch/riscv/cpu/jh7110/Kconfig"
+source "arch/riscv/cpu/c9xx/Kconfig"
 
 # architecture-specific options below
 
diff --git a/arch/riscv/cpu/c9xx/Kconfig b/arch/riscv/cpu/c9xx/Kconfig
new file mode 100644
index 0000000000..5a84bcacd6
--- /dev/null
+++ b/arch/riscv/cpu/c9xx/Kconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2017-2020 Alibaba Group Holding Limited
+
+config RISCV_THEAD
+	bool
+	select ARCH_EARLY_INIT_R
+	imply CPU
+	imply CPU_RISCV
+	imply RISCV_TIMER
+	imply RISCV_RDTIME
+	imply CMD_CPU
diff --git a/arch/riscv/cpu/c9xx/Makefile b/arch/riscv/cpu/c9xx/Makefile
new file mode 100644
index 0000000000..e3f776cb41
--- /dev/null
+++ b/arch/riscv/cpu/c9xx/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2017-2020 Alibaba Group Holding Limited
+
+obj-y += cpu.o dram.o
diff --git a/arch/riscv/cpu/c9xx/cpu.c b/arch/riscv/cpu/c9xx/cpu.c
new file mode 100644
index 0000000000..4b21edd62b
--- /dev/null
+++ b/arch/riscv/cpu/c9xx/cpu.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017-2020 Alibaba Group Holding Limited
+ */
+
+#include <asm/cache.h>
+#include <asm/csr.h>
+#include <cpu_func.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+	cache_flush();
+
+	return 0;
+}
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+	register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+
+	for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
+		asm volatile(".long 0x0295000b");  /* dcache.cpa a0 */
+
+	sync_is();
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+	register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+
+	for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
+		asm volatile(".long 0x02b5000b");  /* dcache.cipa a0 */
+
+	sync_is();
+}
+
+void invalid_dcache_range(unsigned long start, unsigned long end)
+{
+	register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+
+	for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
+		asm volatile(".long 0x02a5000b");  /* dcache.ipa a0 */
+
+	sync_is();
+}
diff --git a/arch/riscv/cpu/c9xx/dram.c b/arch/riscv/cpu/c9xx/dram.c
new file mode 100644
index 0000000000..614d7bf1cc
--- /dev/null
+++ b/arch/riscv/cpu/c9xx/dram.c
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <fdtdec.h>
+#include <init.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+{
+	/*
+	 * Ensure that we run from first 4GB so that all
+	 * addresses used by U-Boot are 32bit addresses.
+	 *
+	 * This in-turn ensures that 32bit DMA capable
+	 * devices work fine because DMA mapping APIs will
+	 * provide 32bit DMA addresses only.
+	 */
+	if (gd->ram_top >= SZ_4G)
+		return SZ_4G - 1;
+
+	return gd->ram_top;
+}
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 986f951c31..3102de6cbb 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -145,6 +145,8 @@
 #define CSR_MARCHID		0xf12
 #define CSR_MHARTID		0xf14
 
+#define sync_is()   asm volatile (".long 0x01b0000b")
+
 #ifndef __ASSEMBLY__
 
 #define csr_swap(csr, val)					\
diff --git a/board/thead/th1520_lpi4a/Kconfig b/board/thead/th1520_lpi4a/Kconfig
index 622246127c..bef0638e80 100644
--- a/board/thead/th1520_lpi4a/Kconfig
+++ b/board/thead/th1520_lpi4a/Kconfig
@@ -11,7 +11,7 @@ config SYS_VENDOR
 	default "thead"
 
 config SYS_CPU
-	default "generic"
+	default "c9xx"
 
 config SYS_CONFIG_NAME
 	default "th1520_lpi4a"
@@ -30,6 +30,7 @@ config SPL_OPENSBI_LOAD_ADDR
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select ARCH_EARLY_INIT_R
+	select RISCV_THEAD
 	imply CPU
 	imply CPU_RISCV
 	imply RISCV_TIMER if RISCV_SMODE
-- 
2.44.0

Re: [PATCH 1/6] cpu: add t-head's c9xx

[Nils Le Roux]

Hi!

I tested this and it works fine. I also happen to have the glue layer ported
from the Linux somewhere on my machine. If you're interested, please 
reach out
to me and I'll arrange a patch. I have a few remarks on this patch:

On 3/27/24 9:07 AM, wefu@redhat.com wrote:
> From: Wei Fu <wefu@redhat.com>
>
> Signed-off-by: Wei Fu <wefu@redhat.com>
> Co-authored-by: Yixun Lan <dlan@gentoo.org>
> ---
>   arch/riscv/Kconfig               |  1 +
>   arch/riscv/cpu/c9xx/Kconfig      | 12 ++++++++
>   arch/riscv/cpu/c9xx/Makefile     |  5 ++++
>   arch/riscv/cpu/c9xx/cpu.c        | 51 ++++++++++++++++++++++++++++++++
>   arch/riscv/cpu/c9xx/dram.c       | 36 ++++++++++++++++++++++
>   arch/riscv/include/asm/csr.h     |  2 ++
>   board/thead/th1520_lpi4a/Kconfig |  3 +-
>   7 files changed, 109 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index ac52c5e6da..ac3b802abe 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -97,6 +97,7 @@ source "arch/riscv/cpu/fu540/Kconfig"
>   source "arch/riscv/cpu/fu740/Kconfig"
>   source "arch/riscv/cpu/generic/Kconfig"
>   source "arch/riscv/cpu/jh7110/Kconfig"
> +source "arch/riscv/cpu/c9xx/Kconfig"
>   
>   # architecture-specific options below
>   
> diff --git a/arch/riscv/cpu/c9xx/Kconfig b/arch/riscv/cpu/c9xx/Kconfig
> new file mode 100644
> index 0000000000..5a84bcacd6
> --- /dev/null
> +++ b/arch/riscv/cpu/c9xx/Kconfig
> @@ -0,0 +1,12 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (C) 2017-2020 Alibaba Group Holding Limited
> +
> +config RISCV_THEAD
> +	bool
> +	select ARCH_EARLY_INIT_R
> +	imply CPU
> +	imply CPU_RISCV
> +	imply RISCV_TIMER
> +	imply RISCV_RDTIME
> +	imply CMD_CPU
> diff --git a/arch/riscv/cpu/c9xx/Makefile b/arch/riscv/cpu/c9xx/Makefile
> new file mode 100644
> index 0000000000..e3f776cb41
> --- /dev/null
> +++ b/arch/riscv/cpu/c9xx/Makefile
> @@ -0,0 +1,5 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (C) 2017-2020 Alibaba Group Holding Limited
> +
> +obj-y += cpu.o dram.o
> diff --git a/arch/riscv/cpu/c9xx/cpu.c b/arch/riscv/cpu/c9xx/cpu.c
> new file mode 100644
> index 0000000000..4b21edd62b
> --- /dev/null
> +++ b/arch/riscv/cpu/c9xx/cpu.c
> @@ -0,0 +1,51 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2017-2020 Alibaba Group Holding Limited
> + */
> +
> +#include <asm/cache.h>
> +#include <asm/csr.h>
> +#include <cpu_func.h>
> +
> +/*
> + * cleanup_before_linux() is called just before we call linux
> + * it prepares the processor for linux
> + *
> + * we disable interrupt and caches.
> + */
> +int cleanup_before_linux(void)
> +{
> +	cache_flush();
> +
> +	return 0;
> +}
> +
> +void flush_dcache_range(unsigned long start, unsigned long end)
> +{
> +	register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
Isn't this just round_down/ALIGN_DOWN macro?
> +
> +	for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
> +		asm volatile(".long 0x0295000b");  /* dcache.cpa a0 */
> +
> +	sync_is();
> +}
> +
> +void invalidate_dcache_range(unsigned long start, unsigned long end)
> +{
> +	register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
> +
> +	for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
> +		asm volatile(".long 0x02b5000b");  /* dcache.cipa a0 */

`th.dcache.cipa` not only invalidates the dcache, but also flushes it 
which is
not expected here. In practice, this leads to a bug with the dwmac 
driver: when
U-Boot handles an ARP request, it overwrites the ARP request with the ARP
response in-place, directly in the ring buffer[^1]. When re-using the same
buffer later on, the driver will flush this data instead of invalidating
it[^2], and you'll read the ARP response you just sent instead of the packet
just written by the chip.

This can easily be reproduced by downloading a big file using TFTP. As 
soon as
you receive an ARP request, U-Boot hangs, timeouts and requests the packet
again. It also makes TCP completely unusable.

You can use `th.dcache.ipa` instead, as implemented in 
`invalid_dcache_range`.

[^1] 
https://github.com/u-boot/u-boot/blob/a5ec56aea1a56737a4e124d058a6920d16f5e686/net/arp.c#L154-L160
[^2] 
https://github.com/u-boot/u-boot/blob/a5ec56aea1a56737a4e124d058a6920d16f5e686/drivers/net/designware.c#L542

> +
> +	sync_is();
> +}
> +
> +void invalid_dcache_range(unsigned long start, unsigned long end)

I think this isn't used anywhere.

> +{
> +	register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
> +
> +	for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
> +		asm volatile(".long 0x02a5000b");  /* dcache.ipa a0 */
> +
> +	sync_is();
> +}
> diff --git a/arch/riscv/cpu/c9xx/dram.c b/arch/riscv/cpu/c9xx/dram.c
> new file mode 100644
> index 0000000000..614d7bf1cc
> --- /dev/null
> +++ b/arch/riscv/cpu/c9xx/dram.c
> @@ -0,0 +1,36 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
> + */
> +
> +#include <fdtdec.h>
> +#include <init.h>
> +#include <linux/sizes.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int dram_init(void)
> +{
> +	return fdtdec_setup_mem_size_base();
> +}
> +
> +int dram_init_banksize(void)
> +{
> +	return fdtdec_setup_memory_banksize();
> +}
> +
> +phys_size_t board_get_usable_ram_top(phys_size_t total_size)
> +{
> +	/*
> +	 * Ensure that we run from first 4GB so that all
> +	 * addresses used by U-Boot are 32bit addresses.
> +	 *
> +	 * This in-turn ensures that 32bit DMA capable
> +	 * devices work fine because DMA mapping APIs will
> +	 * provide 32bit DMA addresses only.
> +	 */
> +	if (gd->ram_top >= SZ_4G)
> +		return SZ_4G - 1;
> +
> +	return gd->ram_top;
> +}
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index 986f951c31..3102de6cbb 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -145,6 +145,8 @@
>   #define CSR_MARCHID		0xf12
>   #define CSR_MHARTID		0xf14
>   
> +#define sync_is()   asm volatile (".long 0x01b0000b")
> +

I believe this instruction is also T-Head specific (at least my disassembler
doesn't know it). I doubt it belongs here.

Best regards,
Nils

>   #ifndef __ASSEMBLY__
>   
>   #define csr_swap(csr, val)					\
> diff --git a/board/thead/th1520_lpi4a/Kconfig b/board/thead/th1520_lpi4a/Kconfig
> index 622246127c..bef0638e80 100644
> --- a/board/thead/th1520_lpi4a/Kconfig
> +++ b/board/thead/th1520_lpi4a/Kconfig
> @@ -11,7 +11,7 @@ config SYS_VENDOR
>   	default "thead"
>   
>   config SYS_CPU
> -	default "generic"
> +	default "c9xx"
>   
>   config SYS_CONFIG_NAME
>   	default "th1520_lpi4a"
> @@ -30,6 +30,7 @@ config SPL_OPENSBI_LOAD_ADDR
>   config BOARD_SPECIFIC_OPTIONS
>   	def_bool y
>   	select ARCH_EARLY_INIT_R
> +	select RISCV_THEAD
>   	imply CPU
>   	imply CPU_RISCV
>   	imply RISCV_TIMER if RISCV_SMODE

[PATCH 2/6] riscv/dts: add gmac node for th1520.

[wefu]

From: Wei Fu <wefu@redhat.com>

Signed-off-by: Wei Fu <wefu@redhat.com>
Co-authored-by: Yixun Lan <dlan@gentoo.org>
---
 arch/riscv/dts/th1520.dtsi | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi
index f7bfa42243..d68c446a6b 100644
--- a/arch/riscv/dts/th1520.dtsi
+++ b/arch/riscv/dts/th1520.dtsi
@@ -128,6 +128,13 @@
 		#clock-cells = <0>;
 	};
 
+	dummy_apb: apb-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <62500000>;
+		clock-output-names = "dummy_apb";
+		#clock-cells = <0>;
+	};
+
 	uart_sclk: uart-sclk-clock {
 		compatible = "fixed-clock";
 		clock-output-names = "uart_sclk";
@@ -163,6 +170,32 @@
 					      <&cpu3_intc 3>, <&cpu3_intc 7>;
 		};
 
+		gmac0: ethernet@ffe7070000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7070000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_a>;
+			status = "disabled";
+			mdio0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,dwmac-mdio";
+
+				phy_88E1111_a: ethernet-phy@1 {
+					reg = <0x1>;
+				};
+
+				phy_88E1111_b: ethernet-phy@2 {
+					reg = <0x2>;
+				};
+			};
+		};
+
 		uart0: serial@ffe7014000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0xff 0xe7014000 0x0 0x100>;
-- 
2.44.0

[PATCH 3/6] riscv/dts: add gmac node for lichee-pi-4a

[wefu]

From: Wei Fu <wefu@redhat.com>

Signed-off-by: Wei Fu <wefu@redhat.com>
Co-authored-by: Yixun Lan <dlan@gentoo.org>
---
 arch/riscv/dts/th1520-lichee-pi-4a.dts | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/riscv/dts/th1520-lichee-pi-4a.dts b/arch/riscv/dts/th1520-lichee-pi-4a.dts
index a1248b2ee3..29f990c7be 100644
--- a/arch/riscv/dts/th1520-lichee-pi-4a.dts
+++ b/arch/riscv/dts/th1520-lichee-pi-4a.dts
@@ -20,6 +20,7 @@
 		serial3 = &uart3;
 		serial4 = &uart4;
 		serial5 = &uart5;
+		ethernet0 = &gmac0;
 	};
 
 	chosen {
@@ -30,3 +31,7 @@
 &uart0 {
 	status = "okay";
 };
+
+&gmac0 {
+	status = "okay";
+};
-- 
2.44.0

[PATCH 4/6] net/designware: add compatible for "snps,dwmac"

[wefu]

From: Wei Fu <wefu@redhat.com>

Signed-off-by: Wei Fu <wefu@redhat.com>
Co-authored-by: Yixun Lan <dlan@gentoo.org>
---
 drivers/net/designware.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index c222197b11..bc2726485b 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -861,6 +861,7 @@ static const struct udevice_id designware_eth_ids[] = {
 	{ .compatible = "amlogic,meson6-dwmac" },
 	{ .compatible = "st,stm32-dwmac" },
 	{ .compatible = "snps,arc-dwmac-3.70a" },
+	{ .compatible = "snps,dwmac" },
 	{ }
 };
 
-- 
2.44.0

[PATCH 5/6] config/th1520_lpi4a_defconfig:enable designware ethernet & realtek phy

[wefu]

From: Wei Fu <wefu@redhat.com>

Signed-off-by: Wei Fu <wefu@redhat.com>
Co-authored-by: Yixun Lan <dlan@gentoo.org>
---
 configs/th1520_lpi4a_defconfig | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/configs/th1520_lpi4a_defconfig b/configs/th1520_lpi4a_defconfig
index 49ff92f6de..b7d049b9d2 100644
--- a/configs/th1520_lpi4a_defconfig
+++ b/configs/th1520_lpi4a_defconfig
@@ -58,16 +58,20 @@ CONFIG_CMD_BOOTMENU=y
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_VERSION_VARIABLE=y
-# CONFIG_NET is not set
 # CONFIG_BLOCK_CACHE is not set
 # CONFIG_GPIO is not set
 # CONFIG_I2C is not set
 # CONFIG_INPUT is not set
 # CONFIG_DM_MMC is not set
 # CONFIG_MTD is not set
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_DW_ALTDESCRIPTOR=y
 # CONFIG_POWER is not set
 CONFIG_SYS_NS16550=y
-CONFIG_RISCV_TIMER=y
+# CONFIG_REGEX is not set
 CONFIG_AES=y
 CONFIG_BLAKE2=y
 CONFIG_SHA512=y
-- 
2.44.0

[PATCH 6/6] config/th1520_lpi4a.h: add more env option for booting linux

[wefu]

From: Wei Fu <wefu@redhat.com>

Signed-off-by: Wei Fu <wefu@redhat.com>
Co-authored-by: Yixun Lan <dlan@gentoo.org>
---
 include/configs/th1520_lpi4a.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/include/configs/th1520_lpi4a.h b/include/configs/th1520_lpi4a.h
index 87496a52c4..6c0c4bc50d 100644
--- a/include/configs/th1520_lpi4a.h
+++ b/include/configs/th1520_lpi4a.h
@@ -17,6 +17,18 @@
 /* Environment options */
 
 #define CFG_EXTRA_ENV_SETTINGS \
+	"kernel_addr_r=0x82000000\0" \
+	"kernel_comp_addr_r=0x88000000\0" \
+	"kernel_comp_size=0x4000000\0" \
+	"ramdisk_addr_r=0x8d300000\0" \
+	"fdt_addr_r=0x8e000000\0" \
+	"fdt_addr_fixed=0x20000000\0" \
+	"scriptaddr=0x8e400000\0" \
+	"scriptfile=uEnv_light_lpi4a.txt\0" \
+	"devtype=mmc\0" \
+	"devnum=0\0" \
+	"bootpart=2\0" \
+	"bootcmd=ext4load mmc ${devnum}:${bootpart} ${scriptaddr} ${scriptfile}; env import -t ${scriptaddr} ${filesize};boot\0" \
 	"PS1=[LPi4A]# \0"
 
 #endif /* __TH1520_LPI4A_H */
-- 
2.44.0

Re: [PATCH 0/6] riscv: adds T-Head C9xx basic and GMAC support.

[Tom Rini]

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On Wed, Mar 27, 2024 at 04:07:21PM +0800, wefu@redhat.com wrote:

> From: Wei Fu <wefu@redhat.com>
> 
> This patchset adds T-Head C9xx basic support in arch/riscv/,
> updates TH1520 Soc/Lichee Pi4A dts files for GMAC support.
> Also enable designware ethernet & realtek phy in default configs,
> and some boot env option for booting linux from Ethernet. 
> 
> Signed-off-by: Wei Fu <wefu@redhat.com>
> Co-authored-by: Yixun Lan <dlan@gentoo.org>

It would be really good to see this moved over to using standard boot
and plain text environment instead of adding to the technical debt here,
thanks.

-- 
Tom

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