[U-Boot-Users] (no subject)

[Peter Wright <peter.wright@utstar.com>]

I have a custom MPC8560 Board that I?ve been told to get U-Boot working on.

I?ve added in board definition into it and modified the default MPC8560ADS
configuration for it.? I have been able to burn it into flash on the board,
and step through it.? U-Boot boots up and configures the TLB and then jumps
to the proper place in FLASH to continue the load.? But it seems to go off
into the middle of nowhere when it comes to the serial_puts command.? From
the JTAG and using the memory map that U-Boot compile makes it gets into the
serial_puts function and then jumps off into main memory for some reason.?
It then halts at where the debugger says is an invalid opcode.

Has anyone seen these sorts of problems before?

The board I?ve been given is very bare.? It has 256 MByte DDR Main RAM,? 32
MByte Flash (64k sectors), Ethernet on MII, and Serial on SCC1.? Nothing
else on it.

This board use to run VxWorks so I took most of the settings used for that
and modified U-boot as following (I hope someone can tell me if I did
something wrong)

Made a new directory for the board
Copied the MPC8560ADS board files to the new location
Copied include/configs/MPC8560ADS.h? to a file matching my new board.

Modified the .h file to meet the new board definitions.? Removed the SDRAM
on LBC, and the SPD_EEPROM

Modified the DDR as follows:

??? #define CFG_SDRAM_SIZE????? 256???????????? /* DDR is 256MB */
??? #define CFG_DDR_CS0_BNDS??? 0x0000000f????? /* 0-256MB */
??? #define CFG_DDR_CS0_CONFIG? 0x80000102
??? #define CFG_DDR_TIMING_1??? 0x37344321
??? #define CFG_DDR_TIMING_2??? 0x00000800????? /* P9-45,may need tuning */
??? #define CFG_DDR_CONTROL???? 0xc2000000????? /* unbuffered,no DYN_PWR */
??? #define CFG_DDR_MODE??????? 0x00000062????? /* DLL,normal,seq,4/2.5 */
??? #define CFG_DDR_INTERVAL??? 0x05100100????? /* autocharge,no open page
*/

Modified flash section as:

#define CFG_FLASH_BASE????????? 0xfe000000????? /* start of FLASH 32M */
#define CFG_BR0_PRELIM????????? 0xfe001001????? /* port size 16bit */

#define CFG_OR0_PRELIM????????? 0xfe000797????? /* 16MB Flash */
#define CFG_MAX_FLASH_BANKS???? 1?????????????? /* number of banks */
#define CFG_MAX_FLASH_SECT????? 512???????????? /* sectors per device */

Which match the settings that were used for VxWorks for this area

I left I2C alone even though the board has no I2C? when I tried to remove it
u-boot wouldn?t compile.

I then modified init.S in the board directory so the TLB looks like:

tlb1_entry:
??????? entry_start

??????? /*
???????? * Number of TLB0 and TLB1 entries in the following table
???????? */
??????? .long 12

#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
??? ????/*
???????? * TLB0???????? 4K????? Non-cacheable, guarded
???????? * 0xff700000?? 4K????? Initial CCSRBAR mapping
???????? *
???????? * This ends up at a TLB0 Index==0 entry, and must not collide
???????? * with other TLB0 Entries.
???????? */
??????? .long TLB1_MAS0(0, 0, 0)
??????? .long TLB1_MAS1(1, 0, 0, 0, 0)
??????? .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
??????? .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT),
0,0,0,0,0,1,0,1,0,1)
#else
#error("Update the number of table entries in tlb1_entry")
#endif

??????? /*
???????? * TLB0???????? 16K???? Cacheable, non-guarded
???????? * 0xd001_0000? 16K???? Temporary Global data for initialization
???????? *
???????? * Use four 4K TLB0 entries.? These entries must be cacheable
???????? * as they provide the bootstrap memory before the memory
???????? * controler and real memory have been configured.
???????? *
???????? * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
???????? * and must not collide with other TLB0 entries.
???????? */
??????? .long TLB1_MAS0(0, 0, 0)
??????? .long TLB1_MAS1(1, 0, 0, 0, 0)
??????? .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
??????????????????????? 0,0,0,0,0,0,0,0)
??????? .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
??????????????????????? 0,0,0,0,0,1,0,1,0,1)

??????? .long TLB1_MAS0(0, 0, 0)
??????? .long TLB1_MAS1(1, 0, 0, 0, 0)
??????? .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
??? ????????????????????0,0,0,0,0,0,0,0)
??????? .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
??????????????????????? 0,0,0,0,0,1,0,1,0,1)

??????? .long TLB1_MAS0(0, 0, 0)
??????? .long TLB1_MAS1(1, 0, 0, 0, 0)
??????? .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
??????????????????????? 0,0,0,0,0,0,0,0)
??????? .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
??????????????????????? 0,0,0,0,0,1,0,1,0,1)
??????? .long TLB1_MAS0(0, 0, 0)
??????? .long TLB1_MAS1(1, 0, 0, 0, 0)
??????? .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
??????????????????????? 0,0,0,0,0,0,0,0)
??????? .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
???? ???????????????????0,0,0,0,0,1,0,1,0,1)


??????? /*
???????? * TLB 0:?????? 16M???? Non-cacheable, guarded
???????? * 0xff000000?? 16M???? FLASH
???????? * Out of reset this entry is only 4K.
???????? */
??????? .long TLB1_MAS0(1, 0, 0)
??????? .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
??????? .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE + 0x01000000),
0,0,0,1,0,1,1,0)
??????? .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE + 0x01000000),
0,0,0,0,1,1,1,1,1,1)

??????? /*
???????? * TLB 1:?????? 256M??? Non-cacheable, guarded
???????? * 0x80000000?? 256M??? PCI1 MEM First half
???????? */
??????? .long TLB1_MAS0(1, 1, 0)
??????? .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
??????? .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
??????? .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE),
0,0,0,0,0,1,0,1,0,1)

??????? /*
???????? * TLB 2:?????? 256M??? Non-cacheable, guarded
???????? * 0x90000000?? 256M??? PCI1 MEM Second half
???????? */
??????? .long TLB1_MAS0(1, 2, 0)
??????? .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
??????? .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
??????????????????????? 0,0,0,0,1,0,1,0)
??????? .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
??????????????????? ????0,0,0,0,0,1,0,1,0,1)

??????? /*
???????? * TLB 3:?????? 16M???? Non-cacheable, guarded
???????? * 0xfe000000?? 16M???? FLASH
???????? */
??????? .long TLB1_MAS0(1, 3, 0)
??????? .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
??????? .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,1,0,1,1,0)
??????? .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,1,1,1,1,1,1)


??????? /*
???????? * TLB 5:?????? 64M???? Non-cacheable, guarded
???????? * 0xe000_0000? 1M????? CCSRBAR
???????? * 0xe200_0000? 16M? ???PCI1 IO
???????? */
??????? .long TLB1_MAS0(1, 5, 0)
??????? .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
??????? .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
??????? .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)

??????? /*
???????? * TLB 7:?????? 16K???? Non-cacheable, guarded
???????? * 0xf8000000?? 16K???? BCSR registers
???????? */
??????? .long TLB1_MAS0(1, 7, 0)
??????? .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
??????? .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0)
??????? .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1)

#if !defined(CONFIG_SPD_EEPROM)
??????? /*
???????? * TLB 8:?????? 256M??? DDR
???????? * 0x00000000?? 64M???? DDR System memory
???????? * 0x04000000?? 64M???? DDR System memory
???????? * Without SPD EEPROM configured DDR, this must be setup manually.
???????? * Make sure the TLB count at the top of this table is correct.
???????? * Likely it needs to be increased by two for these entries.
???????? */

??????? .long TLB1_MAS0(1, 8, 0)
??????? .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
??????? .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,1,0)
??????? .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE),
0,0,0,0,1,1,1,1,1,1)
#endif

??????? entry_end

Modified the Local Address window to:

#if !defined(CONFIG_SPD_EEPROM)
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
/*#define LAWAR0??????? (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE &
LAWAR_SIZE_256M))*/
#define LAWAR0 0x80f0001b
#else
#define LAWBAR0 0
#define LAWAR0? ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) &
~LAWAR_EN)
#endif

#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
#define LAWAR1? (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE &
LAWAR_SIZE_512M))

/*
?* This is not so much the FLASH map as it is the whole localbus map.
?*/
#define LAWBAR2 ((CFG_FLASH_BASE>>12) & 0xfffff)
#define LAWAR2? (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE &
LAWAR_SIZE_32M))

law_entry:
??????? entry_start
??????? .long 0x04
??????? .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
??????? entry_end


Anyone have any idea on what I?ve done wrong?? Are there any other board
definitions in U-Boot I could use that might meet what I have better?

Peter Wright
Senior Software Engineer
Base Station Development
CDMA Division
Main: 1-604-276-0055
Direct: 1-604-303-8599? ext 267