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From: Andy Pont <andy.pont@sdcsystems.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] Falcon mode boot support
Date: Thu, 18 Dec 2014 12:28:16 -0000	[thread overview]
Message-ID: <009e01d01abe$1f4a0f00$5dde2d00$@pont@sdcsystems.com> (raw)
In-Reply-To: <20141217210226.GP20704@bill-the-cat>

Hi Tom,

> I suspect that this might be related to the general problem on these
> part families where SPL isn't as fast as we expect it to be, perhaps
> cache related.

I did a bit of digging around following this line of thought and found an
old discussion on the mailing list
(http://lists.denx.de/pipermail/u-boot/2013-June/156949.html) regarding
someone who had a very similar problem with SPL/Falcon and NAND flash.

I have emailed Bas van den Berg to see if he is willing to share his final
implementation as adding the code that adds the SRAM to the MMU and enables
the caches to the end of am33xx_spl_board_init() hangs within the
enable_caches() function.

Unfortunately this getting well out of my comfort zone with the ARM cores
and so I'm not sure where to go next and how to debug it further.

Regards,

Andy.

  reply	other threads:[~2014-12-18 12:28 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <548f0a77.c768c20a.2e45.26a0SMTPIN_ADDED_BROKEN@mx.google.com>
2014-12-15 17:23 ` [U-Boot] Falcon mode boot support Tom Rini
2014-12-15 21:08   ` Andy Pont
     [not found]   ` <548f4dd3.0677c20a.5db4.14a9SMTPIN_ADDED_BROKEN@mx.google.com>
2014-12-15 22:08     ` Tom Rini
2014-12-16 12:58       ` Andy Pont
     [not found]       ` <54902c90.e44bc20a.557b.5c5bSMTPIN_ADDED_BROKEN@mx.google.com>
2014-12-16 14:30         ` Tom Rini
2014-12-16 14:48           ` Andy Pont
2014-12-17 16:27             ` Andy Pont
     [not found]             ` <5491af14.42fac20a.10ed.3bd4SMTPIN_ADDED_BROKEN@mx.google.com>
2014-12-17 21:02               ` Tom Rini
2014-12-18 12:28                 ` Andy Pont [this message]
2014-12-15 16:20 Andy Pont

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