From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6F319C636CC for ; Thu, 16 Feb 2023 07:39:44 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E2CF585AC4; Thu, 16 Feb 2023 08:39:41 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 263A085AC4; Thu, 16 Feb 2023 08:39:40 +0100 (CET) Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by phobos.denx.de (Postfix) with ESMTP id 0CEAE85AC0 for ; Thu, 16 Feb 2023 08:39:32 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=yanhong.wang@starfivetech.com Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 84C1024E2B1; Thu, 16 Feb 2023 15:39:28 +0800 (CST) Received: from EXMBX073.cuchost.com (172.16.6.83) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 16 Feb 2023 15:39:28 +0800 Received: from [192.168.120.49] (171.223.208.138) by EXMBX073.cuchost.com (172.16.6.83) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 16 Feb 2023 15:39:27 +0800 Message-ID: <0136274a-88d1-bf36-65f1-ab18081bdee6@starfivetech.com> Date: Thu, 16 Feb 2023 15:39:26 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v2 00/17] Basic StarFive JH7110 RISC-V SoC support Content-Language: en-US To: Sean Anderson , Conor Dooley CC: , Rick Chen , Leo , Lukasz Majewski , Lee Kuan Lim , Jianlong Huang , Emil Renner Berthing References: <20230118081132.31403-1-yanhong.wang@starfivetech.com> <6363344f-1448-ddf6-9459-94a1b44e27d3@gmail.com> From: yanhong wang In-Reply-To: <6363344f-1448-ddf6-9459-94a1b44e27d3@gmail.com> Content-Type: text/plain; charset="UTF-8" X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS061.cuchost.com (172.16.6.21) To EXMBX073.cuchost.com (172.16.6.83) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On 2023/1/22 5:56, Sean Anderson wrote: > On 1/21/23 16:36, Conor Dooley wrote: >> On Wed, Jan 18, 2023 at 04:11:15PM +0800, Yanhong Wang wrote: >>> This series of patches base on the latest branch/master, and add supp= ort >>> for the StarFive JH7110 RISC-V SoC and VisionFive V2 board. In order = for >>> this to be achieved, the respective DT nodes have been added,=C2=A0 a= nd the >>> required defconfigs have been added to the boards' defconfig. What is= more, >>> the basic required DM drivers have been added, such as reset, clock, = pinctrl, >>> uart, ram etc. >>> >>> Note that the register base address of reset controller is same with = the >>> clock controller. Therefore, there is no device tree node alone for r= eset >>> driver. It binds device node in the clock driver. >>> >>> The u-boot-spl and u-boot has been tested on the VisionFive V2 boards= which >>> equip with JH7110 SoC and works normally. >>> >>> For more information and support, you can visit RVspace wiki[1]. >>> >>> [1] https://wiki.rvspace.org/ >>> >>> Changes in v2: >>> - Renamed file 'jh7110-regs.h' to 'regs.h'. >>> - Reworded the clear L2 LIM memory code in C. >>> - Removed flash init call in 'spl_soc_init' function. >>> - Reworded the clock driver. >>> - Rename the macro 'SET_DIV' to 'ASSIGNED_CLOCK_PARENTS' in 'spl.c'. >>> - Moved the device tree node 'dmc@15700000' from 'jh7110-u-boot.dtsi'= to >>> =C2=A0=C2=A0 'starfive_visionfive2-u-boot.dtsi'. >>> >>> Previous versions: >>> v1 - https://patchwork.ozlabs.org/project/uboot/cover/20221212025020.= 23778-1-yanhong.wang@starfivetech.com/ >>> >>> Jianlong Huang (1): >>> =C2=A0=C2=A0 dt-bindings: pinctrl: Add StarFive JH7110 pinctrl defini= tions >>> >>> Kuan Lim Lee (1): >>> =C2=A0=C2=A0 pinctrl: starfive: Add StarFive JH7110 driver >>> >>> Yanhong Wang (15): >>> =C2=A0=C2=A0 riscv: cpu: jh7110: Add support for jh7110 SoC >>> =C2=A0=C2=A0 cache: starfive: Add StarFive JH7110 support >>> =C2=A0=C2=A0 dt-bindings: reset: Add StarFive JH7110 reset definition= s >>> =C2=A0=C2=A0 reset: starfive: jh7110: Add reset driver for StarFive J= H7110 SoC >>> =C2=A0=C2=A0 dt-bindings: clock: Add StarFive JH7110 clock definition= s >>> =C2=A0=C2=A0 clk: starfive: Add StarFive JH7110 clock driver >>> =C2=A0=C2=A0 ram: starfive: add ddr driver >>> =C2=A0=C2=A0 board: starfive: add StarFive VisionFive v2 board suppor= t >>> =C2=A0=C2=A0 riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC >>> =C2=A0=C2=A0 board: starfive: Add Kconfig for StarFive VisionFive v2 = Board >>> =C2=A0=C2=A0 board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kcon= fig >>> =C2=A0=C2=A0 riscv: dts: jh7110: Add initial StarFive JH7110 device t= ree >>> =C2=A0=C2=A0 riscv: dts: jh7110: Add initial u-boot device tree >>> =C2=A0=C2=A0 riscv: dts: jh7110: Add initial StarFive VisionFive v2 b= oard device >>> =C2=A0=C2=A0=C2=A0=C2=A0 tree >>> =C2=A0=C2=A0 configs: starfive: add starfive_visionfive2_defconfig >> >> Apologies if I have missed it somewhere - but where is patch 12? >> I don't see it on lore.kernel.org nor in my inbox :( >> >> Thanks, >> Conor. >> >=20 > https://lore.kernel.org/all/20230118082907.31629-1-yanhong.wang@starfiv= etech.com/ >=20 > Not sure why it isn't with the rest of the series. >=20 It was reported send fail when sending patch 12, so it was sent separatel= y later > --Sean