From mboxrd@z Thu Jan  1 00:00:00 1970
From: DeLaGarza, Robert <robdlg@att.net>
Date: Tue, 15 Apr 2003 01:42:13 -0700
Subject: [U-Boot-Users] mpc8245 timer
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The following code appears in u-boot-0.3.0/cpu/mpc824x/cpu.c

/*
 * Get timebase clock frequency (like cpu_clk in Hz)
 * This is the sys_logic_clk (memory bus) divided by 4
 */
unsigned long get_tbclk (void)
{
	return ((get_bus_freq (0) + 2L) / 4L);
}


However, in Table 11-11 of the _MPC8245 Integrated Processor User's Manual_,
there is the statement "The timers operate at 1/8 the speed of the SDRAM_CLK signal."

Should the divisor in get_tbclk( ) be 8L for the MPC8245?

(I know there are several '8245 and '8241 boards using PPCBoot and/or U-Boot, so my
guess is that the manual is wrong, but I didn't see anything in the errata about this.)