From: mchitale@ventanamicro.com
To: Michal Simek <michal.simek@amd.com>,
Jagan Teki <jagan@amarulasolutions.com>
Cc: u-boot@lists.denx.de, Simon Glass <sjg@chromium.org>,
Tom Rini <trini@konsulko.com>
Subject: Re: [PATCH v1 3/3] drivers: xilinx_spi: Probe fifo_depth at runtime
Date: Thu, 16 Nov 2023 18:47:40 +0530 [thread overview]
Message-ID: <01a7967a2ad7c06c9658e5d7aa6fee20cf23d155.camel@ventanamicro.com> (raw)
In-Reply-To: <4594325a-f240-4a6f-927f-6aec53cfa830@amd.com>
On Mon, 2023-11-13 at 10:06 +0100, Michal Simek wrote:
>
> On 11/11/23 18:31, Mayuresh Chitale wrote:
> > If the fifo-size DT parameter is not provided then probe the
> > controller's fifo depth at runtime. This is ported from a patch
> > in the Linux Xilinx SPI driver.
> >
> > Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> > Link:
> > https://lore.kernel.org/r/1422029330-10971-5-git-send-email-ricardo.ribalda@gmail.com
> > ---
> > drivers/spi/xilinx_spi.c | 23 +++++++++++++++++++++++
> > 1 file changed, 23 insertions(+)
> >
> > diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
> > index b63cda2091..99ae5be291 100644
> > --- a/drivers/spi/xilinx_spi.c
> > +++ b/drivers/spi/xilinx_spi.c
> > @@ -109,6 +109,27 @@ struct xilinx_spi_priv {
> > u8 startup;
> > };
> >
> > +static int xilinx_spi_find_buffer_size(struct xilinx_spi_regs
> > *regs)
> > +{
> > + u8 sr;
> > + int n_words = 0;
> > +
> > + /*
> > + * Before the buffer_size detection we reset the core
> > + * to make sure we start with a clean state.
>
> nit: can you please remove "we" above? It should be written in
> imperative mood.
Ok.
>
>
> > + */
> > + writel(SPISSR_RESET_VALUE, ®s->srr);
> > +
> > + /* Fill the Tx FIFO with as many words as possible */
> > + do {
> > + writel(0, ®s->spidtr);
> > + sr = readl(®s->spisr);
> > + n_words++;
> > + } while (!(sr & SPISR_TX_FULL));
> > +
> > + return n_words;
> > +}
> > +
> > static int xilinx_spi_probe(struct udevice *bus)
> > {
> > struct xilinx_spi_priv *priv = dev_get_priv(bus);
> > @@ -116,6 +137,8 @@ static int xilinx_spi_probe(struct udevice
> > *bus)
> >
> > regs = priv->regs = dev_read_addr_ptr(bus);
> > priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0);
> > + if (!priv->fifo_depth)
> > + priv->fifo_depth = xilinx_spi_find_buffer_size(regs);
> >
> > writel(SPISSR_RESET_VALUE, ®s->srr);
> >
>
> When above fixed feel free to add
> Reviewed-by: Michal Simek <michal.simek@amd.com>
Ok.
>
> Thanks,
> Michal
prev parent reply other threads:[~2023-11-16 13:17 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-11 17:31 [PATCH v1 0/3] Xilinx SPI driver enhancements Mayuresh Chitale
2023-11-11 17:31 ` [PATCH v1 1/3] drivers: xilinx_spi: Use udevice in start_tranfer Mayuresh Chitale
2023-11-11 17:31 ` [PATCH v1 2/3] drivers: xilinx_spi: Add xfer callback Mayuresh Chitale
2023-11-11 17:31 ` [PATCH v1 3/3] drivers: xilinx_spi: Probe fifo_depth at runtime Mayuresh Chitale
2023-11-13 9:06 ` Michal Simek
2023-11-16 13:17 ` mchitale [this message]
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