From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rene Straub Date: Tue, 25 Apr 2017 05:43:31 +0000 Subject: [U-Boot] [EXT] Armada 385: PEX detection pulse width In-Reply-To: <1160bc3ef5fc46419d338bce5d87e7d9@IL-EXCH01.marvell.com> References: <20170421085105.GA6180@gruene.netmodule.intranet> <1160bc3ef5fc46419d338bce5d87e7d9@IL-EXCH01.marvell.com> Message-ID: <02ca36371d7f43688e9fc3882c02a131@ebro.netmodule.intranet> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable To: u-boot@lists.denx.de Hello Adam, first of all thanks the quick reply. First trials with reduced pulse length= , showed promising results. To better understand the root cause of the prob= lem, it would be helpful if you explained us briefly what the register chan= ge actually performs. I/we understand that the problem is related to the pr= ocess of Rx Detection (measuring voltage change on PCIe link after a common= mode step). Maybe we can implement a board change (PCIe lane coupling capa= citors) to improve the detection, even with the default pulse length of the= A385. Best regards -Rene -----Original Message----- From: Adam Shobash [mailto:adams at marvell.com]=20 Sent: Sonntag, 23. April 2017 19:29 To: Stefan Eichenberger Cc: Assaf Hoffman ; Rene Straub ; sr at denx.de; u-boot at lists.denx.de Subject: RE: [EXT] Armada 385: PEX detection pulse width Hi Stefan, In A385, the register to change the pulse width is 0xa0120 bits[7:6]. Default value is 0x1(pulse width=3D2us) , you can try and change it to 0x0 = to see if it solves the issue. But, please note that we tested our platforms with the value 0x1 only and w= e cannot guarantee that after you change this value that it will work for a= ll the devices/add in cards other than Atheros . Thanks, Adam -----Original Message----- From: Stefan Eichenberger [mailto:stefan.eichenberger at netmodule.com]=20 Sent: Friday, April 21, 2017 11:51 AM To: Adam Shobash Cc: Assaf Hoffman; Ren=C3=A9 Straub; sr at denx.de; u-boot at lists.denx.de Subject: [EXT] Armada 385: PEX detection pulse width External Email ---------------------------------------------------------------------- Dear Adam, On the mainline u-boot we found a commit which helps to fix a problem regar= ding PCIe and the Armada 370: http://git.denx.de/?p=3Du-boot.git;a=3Dcommit;h=3D6bbe0924a799d33c1a8c9de38= b60a5e0251f2aea We currently facing a similar problem with the Armada 385 and PCIe. The pro= blem also appears with two different Atheros chipsets one (AR9280) gets nev= er detected and the other one gets detected most of the time but not always= (QCA9882). With Intel modules on the other hand, we can't reproduce the is= sue. It's the same behaviour as described in the commit above, the link tra= ining fails and therefore the link is signalized as down. If a link is succ= essfully established (QCA9882) we don't see any errors during communication. Do you know if we have the same possibility on the Armada 385 to tune the P= CI Express pulse width as you proposed it for the Armada 370? Unfortunately the PCIe Phy seems to be quite different to the one from the = Armada 370. Best regards Stefan