[U-Boot-Users] need help for LAN91C111 driver

[U-Boot-Users] need help for LAN91C111 driver

[Stephan Linz]

Hi,

I've found unexpected code inside of smc_phy_configure() in file 
drivers/smc91111.c:

	/* Enable PHY Interrupts (for register 18) */
	/* Interrupts listed here are disabled */
	smc_write_phy_register (PHY_INT_REG, 0xffff);

PHY_INT_REG is an read only register (all bits). So I don't understand the 
write access -- Why? Can anybody explain this step?

I think the corregt register have to be PHY_MASK_REG (register 19), which 
correspond to PHY_INT_REG (register 18) as interrupt mask.


Thanks, and best regards
-- 
Mit freundlichen Gruessen
Stephan Linz



======================================================================
Stephan Linz
Softwareentwicklung

MAZeT GmbH                   Email: mailto:linz at mazet.de
G?schwitzer Str. 32          Tel. : (3641) 2809-55
D-07745 Jena                 Fax  : (3641) 2809-12

Besuchen Sie bitte unsere Web-Seiten: http://www.MAZeT.de
======================================================================

[U-Boot-Users] need help for LAN91C111 driver

[Robert Schwebel]

On Tue, Oct 28, 2003 at 02:03:42PM +0100, Stephan Linz wrote:
> PHY_INT_REG is an read only register (all bits). So I don't understand the 
> write access -- Why? Can anybody explain this step?
> 
> I think the corregt register have to be PHY_MASK_REG (register 19), which 
> correspond to PHY_INT_REG (register 18) as interrupt mask.

I assume you are right - at least that is how we have fixed it in our
-ptx patch. Unfortunately I didn't find the time to push everything
upstream yet :-( 

Robert
-- 
 Dipl.-Ing. Robert Schwebel | http://www.pengutronix.de
 Pengutronix - Linux Solutions for Science and Industry
   Handelsregister:  Amtsgericht Hildesheim, HRA 2686
     Hornemannstra?e 12,  31137 Hildesheim, Germany
    Phone: +49-5121-28619-0 |  Fax: +49-5121-28619-4

[U-Boot-Users] need help for LAN91C111 driver

[Stephan Linz]

Am Dienstag, 28. Oktober 2003 14:28 schrieb Robert Schwebel:
> On Tue, Oct 28, 2003 at 02:03:42PM +0100, Stephan Linz wrote:
> > PHY_INT_REG is an read only register (all bits). So I don't understand
> > the write access -- Why? Can anybody explain this step?
> >
> > I think the corregt register have to be PHY_MASK_REG (register 19), which
> > correspond to PHY_INT_REG (register 18) as interrupt mask.
>
> I assume you are right - at least that is how we have fixed it in our
> -ptx patch. Unfortunately I didn't find the time to push everything
> upstream yet :-(

I'll post a patch in near future, because that isn't the only problem I have 
with this LAN adapter (driver).

Bye,
-- 
Mit freundlichen Gruessen
Stephan Linz



======================================================================
Stephan Linz
Softwareentwicklung

MAZeT GmbH                   Email: mailto:linz at mazet.de
G?schwitzer Str. 32          Tel. : (3641) 2809-55
D-07745 Jena                 Fax  : (3641) 2809-12

Besuchen Sie bitte unsere Web-Seiten: http://www.MAZeT.de
======================================================================