From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9A59EC7EE29 for ; Mon, 5 Jun 2023 01:40:44 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E559D846BF; Mon, 5 Jun 2023 03:40:41 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=etri.re.kr Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=dooray.com header.i=@dooray.com header.b="cN2gbiok"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 534C1847D6; Mon, 5 Jun 2023 03:40:39 +0200 (CEST) Received: from mscreen.etri.re.kr (mscreen.etri.re.kr [129.254.9.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7C98D846BE for ; Mon, 5 Jun 2023 03:40:31 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=etri.re.kr Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ckim@etri.re.kr Received: from unknown (HELO send001-relay.gov-dooray.com) (211.180.235.152) by 129.254.9.16 with ESMTP; 5 Jun 2023 10:40:28 +0900 X-Original-SENDERIP: 211.180.235.152 X-Original-MAILFROM: ckim@etri.re.kr X-Original-RCPTTO: u-boot@lists.denx.de Received: from [10.162.225.106] (HELO smtp001-imp.gov-dooray.com) ([10.162.225.106]) by send001-relay.gov-dooray.com with SMTP id 40b1d150647d3d0c; Mon, 05 Jun 2023 10:40:28 +0900 DKIM-Signature: a=rsa-sha256; b=cN2gbiok9ZhUUZ2CVTDT5rp3mblyNParp+kXga3dNmym5IG+YPYDZAZuIk7MekY8h71r44/1qv KfD2uzefSQzEFGaDeB/saKFq6jZaC7uyFQ5TorEu4tWz/vupadVjE2GqtzWJM6i/L2Svgbt2Ki3H IWXtXo/rs86ROgrhQ5dOLWkG9/lSHHTc3E/3lS01JaatUEmR8xHs2R/qXE1LHoSw2xL3tBVBWA/2 lSfUTSv2FxHamllvF0Pqg617urSo5uDyIf/oCbwqsMy29qvodD3aPc5riizDH+zgIO3ypLtXJ6Wy bBxqroUZ04uf21mJXFn5IZmk+ltsKkjIeTAnLsEg==; c=relaxed/relaxed; s=selector; d=dooray.com; v=1; bh=Kn+is+vgkZpDYt68Vdj7JJJjUsaBS0q9yGSKCtfRWAI=; h=From:To:Subject:Message-ID; Received: from [129.254.132.39] (HELO CHANKIMPC) ([129.254.132.39]) by smtp001-imp.gov-dooray.com with SMTP id 6778583b647d3d0b; Mon, 05 Jun 2023 10:40:28 +0900 From: "Chan Kim" To: "U-Boot Mailing List" Subject: [PATCH] Add CONFIG_GICV3 for ARCH_QEMU Date: Mon, 5 Jun 2023 10:40:26 +0900 Message-ID: <038c01d9974e$b450fcb0$1cf2f610$@etri.re.kr> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdmXTqnkGA7Zr+YERCOQk8wYOnrChA== Content-Language: ko X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean I'm trying sending a patch for the first time. I found when running u-boot qemu_arm64_defconfig on qemu-6.2.0's arm64 virt machine, we need CONFIG_GICV3. And for the GICV3 related to be compiled, we need to add GICD_BASE, GICR_BASE defined by the qemu arm64 virt machine. Signed-off-by : Chan Kim diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 99264a6478..437857b188 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1044,6 +1044,7 @@ config ARCH_QEMU select DM_SERIAL select OF_CONTROL select PL01X_SERIAL + select GICV3 imply CMD_DM imply DM_RNG imply DM_RTC diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h index e296f39879..979ae1815d 100644 --- a/include/configs/qemu-arm.h +++ b/include/configs/qemu-arm.h @@ -11,4 +11,6 @@ /* For timer, QEMU emulates an ARMv7/ARMv8 architected timer */ +#define GICD_BASE 0x8000000 /* 24MHz, FPGA runs at 5MHz */ +#define GICR_BASE 0x80a0000 /* 24MHz, FPGA runs at 5MHz */ #endif /* __CONFIG_H */ Thanks! Chan Kim