[U-Boot-Users] PPC4xx: SDRAM detection (bug?)

[Stefan Roese <stefan.roese@esd-electronics.com>]

Hi Llandre,

Sorry if I jump into this thread this late!

> I have a question about SDRAM detection code (cpu/ppc4xx/sdram.c).
> I tested it with the following configurations:
> Configuration #1: 32 MB (2 chips), SDRAM clk = 133 MHz
> Configuration #2: 32 MB (2 chips), SDRAM clk = 111 MHz
> and everything worked fine.
> 
> Then I tried the following:
> Configuration #3: 64 MB (2 chips), SDRAM clk = 111 MHz
> and the SDRAM does not work. U-Boot executes fine until it 
> jumps to SDRAM
> after relocation.
> In this case, two chips K4S561632E-TI75 have been used.
> In my understanding the default value (0x07f00000) for the 
> RTR register
> is wrong because these chips have a 64 ms/8k cycle refresh.
> Thus this register should be 0x03780000. I tried to change it
> but SDRAM did not work anyway. I suspect it is necessary to fix
> the TR register too or that the value for RTR is wrong.
> Any suggestions/remarks?

Yes, you are right: There seems to be a problem with the refresh counter
intialization in the sdram.c code (I am not referencing the spd_sdram.c
code here!). But I am not sure that this explains why U-Boot is not
running on your board with the 256mbit chips. We are running this code
on our board with all kind of sdram's (64mbit, 128mbit, 256mbit and even
512mbit) without any known problems. The 256mbit chips we use right now
are the Micron MT48LC16M16A2-7E.

But again there seems to be a problem which needs to be fixed. I can put
this on my list or you could send a patch! ;-)

Best regards,
Stefan