* [U-Boot-Users] main clock calculation invalid
@ 2007-04-19 15:42 Junior
2007-04-19 15:54 ` Wolfgang Denk
0 siblings, 1 reply; 8+ messages in thread
From: Junior @ 2007-04-19 15:42 UTC (permalink / raw)
To: u-boot
Hi all,
I'm trying to figure out why the below calculation of my main frequencey clock is not correct.
In the below equation:
maindiv2 = 28
maindiv1 = 13
prediv = 23
ps = 0
and CONFIG_SYS_CLK_FREQ is 14745600.
but I get 93622108 instead of 265420800. How is this possible?
here is the equation which is what get_FCLK returns:
return (((maindiv2 + 2) * (maindiv1 + 2) * CONFIG_SYS_CLK_FREQ) /
((prediv + 2) * (1 << ps)));
much thanks.
--Jr.
____________________________________________________________
GET FREE 5GB ONLINE STORAGE - Safely store your documents, photos and music online!
Visit http://www.inbox.com/storage to find out more!
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot-Users] main clock calculation invalid
2007-04-19 15:42 [U-Boot-Users] main clock calculation invalid Junior
@ 2007-04-19 15:54 ` Wolfgang Denk
2007-04-19 16:16 ` Junior
0 siblings, 1 reply; 8+ messages in thread
From: Wolfgang Denk @ 2007-04-19 15:54 UTC (permalink / raw)
To: u-boot
In message <06D6E1270E8.0000028Aejr@inbox.com> you wrote:
>
> I'm trying to figure out why the below calculation of my main frequencey clock is not correct.
>
> In the below equation:
> maindiv2 = 28
> maindiv1 = 13
> prediv = 23
> ps = 0
> and CONFIG_SYS_CLK_FREQ is 14745600.
I'm sorry, but the user's manual for my Z80 processor does not contain
any part which matches your description.
What might be missing?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, HRB 165235 Munich, CEO: Wolfgang Denk
Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Memories of you remind me of you. - Karl Lehenbauer
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot-Users] main clock calculation invalid
2007-04-19 15:54 ` Wolfgang Denk
@ 2007-04-19 16:16 ` Junior
2007-04-19 18:14 ` Wolfgang Denk
2007-04-19 18:51 ` Junior
0 siblings, 2 replies; 8+ messages in thread
From: Junior @ 2007-04-19 16:16 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: wd at denx.de
> Sent: Thu, 19 Apr 2007 17:54:59 +0200
> To: ejr at inbox.com
> Subject: Re: [U-Boot-Users] main clock calculation invalid
>
> In message <06D6E1270E8.0000028Aejr@inbox.com> you wrote:
>>
>> I'm trying to figure out why the below calculation of my main frequencey
>> clock is not correct.
>>
>> In the below equation:
>> maindiv2 = 28
>> maindiv1 = 13
>> prediv = 23
>> ps = 0
>> and CONFIG_SYS_CLK_FREQ is 14745600.
>
> I'm sorry, but the user's manual for my Z80 processor does not contain
> any part which matches your description.
>
> What might be missing?
I'm not sure what you're missing but my emphasis was on the calculation.
This is on an ARM9 LH7A404 chip. Now I might be missing something but even on a 16 bit CPU
the calculation result shouldn't change, no?
This is the function, all my printed values are correct before the calculation.
/* return FCLK frequency */
ulong get_FCLK (void)
{
lh7a40x_csc_t* csc = LH7A404_CSC_PTR;
ulong maindiv1, maindiv2, prediv, ps;
/*
* FCLK = ((MAINDIV1 +2) * (MAINDIV2 +2) * 14.7456MHz) /
* ((PREDIV+2) * (2^PS))
*/
maindiv2 = (csc->clkset & CLKSET_MAINDIV2) >> 11;
maindiv1 = (csc->clkset & CLKSET_MAINDIV1) >> 7;
prediv = (csc->clkset & CLKSET_PREDIV) >> 2;
ps = (csc->clkset & CLKSET_PS) >> 16;
printf("maindiv2: %d, maindiv1 %d, prediv %d, ps %d\n",maindiv2,maindiv1,prediv,ps);
printf("CONFIG_SYS_CLK_FREQ: %d \n",CONFIG_SYS_CLK_FREQ);
return ( ((maindiv2 + 2) * (maindiv1 + 2) * CONFIG_SYS_CLK_FREQ) / ((prediv + 2) * (1 << ps)));
}
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot-Users] main clock calculation invalid
2007-04-19 16:16 ` Junior
@ 2007-04-19 18:14 ` Wolfgang Denk
2007-04-19 18:51 ` Junior
1 sibling, 0 replies; 8+ messages in thread
From: Wolfgang Denk @ 2007-04-19 18:14 UTC (permalink / raw)
To: u-boot
In message <0721A2B6C14.000002EAejr@inbox.com> you wrote:
>
> > I'm sorry, but the user's manual for my Z80 processor does not contain
...
> I'm not sure what you're missing but my emphasis was on the calculation.
> This is on an ARM9 LH7A404 chip. Now I might be missing something but even
> on a 16 bit CPU
You did not understand my little joke about the old Z80 CPU - what I
wanted to pointout was that you completely left out all relevant
information, like which architecture and CPU and board you were
talking about.
> the calculation result shouldn't change, no?
You might have overflows here and there...
> and CONFIG_SYS_CLK_FREQ is 14745600.
It should probably be 14745600L or "UL".
> ulong maindiv1, maindiv2, prediv, ps;
^^^^^
> printf("maindiv2: %d, maindiv1 %d, prediv %d, ps %d\n",maindiv2,maindiv1,prediv,ps);
^^ ^^ ^^ ^^
%d is for int, not for ulong.
> printf("CONFIG_SYS_CLK_FREQ: %d \n",CONFIG_SYS_CLK_FREQ);
Same here.
> return ( ((maindiv2 + 2) * (maindiv1 + 2) * CONFIG_SYS_CLK_FREQ) /
> ((prediv + 2) * (1 << ps)));
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, HRB 165235 Munich, CEO: Wolfgang Denk
Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
What was sliced bread the greatest thing since?
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot-Users] main clock calculation invalid
2007-04-19 16:16 ` Junior
2007-04-19 18:14 ` Wolfgang Denk
@ 2007-04-19 18:51 ` Junior
2007-04-20 7:17 ` Martin Krause
1 sibling, 1 reply; 8+ messages in thread
From: Junior @ 2007-04-19 18:51 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: ejr at inbox.com
> Sent: Thu, 19 Apr 2007 08:16:01 -0800
> To: wd at denx.de
> Subject: Re: [U-Boot-Users] main clock calculation invalid
>
>> -----Original Message-----
>> From: wd at denx.de
>> Sent: Thu, 19 Apr 2007 17:54:59 +0200
>> To: ejr at inbox.com
>> Subject: Re: [U-Boot-Users] main clock calculation invalid
>>
>> In message <06D6E1270E8.0000028Aejr@inbox.com> you wrote:
>>>
>>> I'm trying to figure out why the below calculation of my main
>>> frequencey
>>> clock is not correct.
>>>
>>> In the below equation:
>>> maindiv2 = 28
>>> maindiv1 = 13
>>> prediv = 23
>>> ps = 0
>>> and CONFIG_SYS_CLK_FREQ is 14745600.
>>
>> I'm sorry, but the user's manual for my Z80 processor does not contain
>> any part which matches your description.
>>
>> What might be missing?
>
> I'm not sure what you're missing but my emphasis was on the calculation.
> This is on an ARM9 LH7A404 chip. Now I might be missing something but
> even on a 16 bit CPU
> the calculation result shouldn't change, no?
>
> This is the function, all my printed values are correct before the
> calculation.
>
> /* return FCLK frequency */
> ulong get_FCLK (void)
> {
> lh7a40x_csc_t* csc = LH7A404_CSC_PTR;
> ulong maindiv1, maindiv2, prediv, ps;
>
> /*
> * FCLK = ((MAINDIV1 +2) * (MAINDIV2 +2) * 14.7456MHz) /
> * ((PREDIV+2) * (2^PS))
> */
> maindiv2 = (csc->clkset & CLKSET_MAINDIV2) >> 11;
> maindiv1 = (csc->clkset & CLKSET_MAINDIV1) >> 7;
> prediv = (csc->clkset & CLKSET_PREDIV) >> 2;
> ps = (csc->clkset & CLKSET_PS) >> 16;
> printf("maindiv2: %d, maindiv1 %d, prediv %d, ps
> %d\n",maindiv2,maindiv1,prediv,ps);
> printf("CONFIG_SYS_CLK_FREQ: %d \n",CONFIG_SYS_CLK_FREQ);
> return ( ((maindiv2 + 2) * (maindiv1 + 2) * CONFIG_SYS_CLK_FREQ) /
> ((prediv + 2) * (1 << ps)));
> }
>
I think I see what the problem is but I'm not sure how to fix it in uboot.
When I multiply 450 and 14745600, I get a number greater than 32 bits and the MSB is missed.
I could do an alternative calculation to achive the correct result but unless there is a good trick out
there I'll do that.
Thanks,
--Jr.
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot-Users] main clock calculation invalid
2007-04-19 18:51 ` Junior
@ 2007-04-20 7:17 ` Martin Krause
2007-04-20 8:18 ` Wolfgang Denk
0 siblings, 1 reply; 8+ messages in thread
From: Martin Krause @ 2007-04-20 7:17 UTC (permalink / raw)
To: u-boot
Hi Junior,
u-boot-users-bounces at lists.sourceforge.net wrote on Thursday, April 19,
2007 8:52 PM:
> > return ( ((maindiv2 + 2) * (maindiv1 + 2) *
> > CONFIG_SYS_CLK_FREQ) / ((prediv + 2) * (1 << ps))); }
> >
>
>
> I think I see what the problem is but I'm not sure how to fix it in
> uboot.
> When I multiply 450 and 14745600, I get a number greater than 32 bits
> and the MSB is missed.
You could rearrange your formula:
CONFIG_SYS_CLK_FREQ / ((prediv + 2) * (1 << ps)) * (maindiv2 + 2) *
(maindiv1 + 2)
The compiler should do the calculation from left to right.
Regards,
Martin
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot-Users] main clock calculation invalid
2007-04-20 7:17 ` Martin Krause
@ 2007-04-20 8:18 ` Wolfgang Denk
2007-04-20 9:18 ` Martin Krause
0 siblings, 1 reply; 8+ messages in thread
From: Wolfgang Denk @ 2007-04-20 8:18 UTC (permalink / raw)
To: u-boot
In message <47F3F98010FF784EBEE6526EAAB078D1024F8528@tq-mailsrv.tq-net.de> you wrote:
>
> You could rearrange your formula:
>
> CONFIG_SYS_CLK_FREQ / ((prediv + 2) * (1 << ps)) * (maindiv2 + 2) *
> (maindiv1 + 2)
>
> The compiler should do the calculation from left to right.
And if in doubt, use parens to define the order of evaluation.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, HRB 165235 Munich, CEO: Wolfgang Denk
Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
A man either lives life as it happens to him, meets it head-on and
licks it, or he turns his back on it and starts to wither away.
-- Dr. Boyce, "The Menagerie" ("The Cage"), stardate unknown
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot-Users] main clock calculation invalid
2007-04-20 8:18 ` Wolfgang Denk
@ 2007-04-20 9:18 ` Martin Krause
0 siblings, 0 replies; 8+ messages in thread
From: Martin Krause @ 2007-04-20 9:18 UTC (permalink / raw)
To: u-boot
wd at denx.de wrote on Friday, April 20, 2007 10:18 AM:
> In message
> <47F3F98010FF784EBEE6526EAAB078D1024F8528@tq-mailsrv.tq-net.de> you
> wrote:
> >
> > You could rearrange your formula:
> >
> > CONFIG_SYS_CLK_FREQ / ((prediv + 2) * (1 << ps)) * (maindiv2 + 2) *
> > (maindiv1 + 2)
> >
> > The compiler should do the calculation from left to right.
>
> And if in doubt, use parens to define the order of evaluation.
Ahhh, I always had a strong feeling, that theses parenthesis things
would be good for something ... ;-)
Ragards,
Martin
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2007-04-20 9:18 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2007-04-19 15:42 [U-Boot-Users] main clock calculation invalid Junior
2007-04-19 15:54 ` Wolfgang Denk
2007-04-19 16:16 ` Junior
2007-04-19 18:14 ` Wolfgang Denk
2007-04-19 18:51 ` Junior
2007-04-20 7:17 ` Martin Krause
2007-04-20 8:18 ` Wolfgang Denk
2007-04-20 9:18 ` Martin Krause
[not found] <06d6e1270e8.0000028aejr@inbox.com>
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox