From mboxrd@z Thu Jan  1 00:00:00 1970
From: Stefan Roese <sr@denx.de>
Date: Tue, 7 Jan 2020 14:10:47 +0100
Subject: [PATCH v2 1/2] Add GigaDevice gd25q128 128Mbit chip to spi-nor id
 table.
In-Reply-To: <20191227132515.15869-1-mc5686@mclink.it>
References: <20191227132515.15869-1-mc5686@mclink.it>
Message-ID: <08a17bda-9fe9-36b1-ca3e-cea159c7735e@denx.de>
List-Id: <u-boot.lists.denx.de>
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To: u-boot@lists.denx.de

Hi Mauro,

On 27.12.19 14:25, Mauro Condarelli wrote:
> From: MCon <mc5686@mclink.it>
> 
> Tested on VoCore2
> 
> Signed-off-by: MCon <mc5686@mclink.it>
> Signed-off-by: Mauro Condarelli <mc5686@mclink.it>
> ---
> 
> Changes in v2: None
> 
>   drivers/mtd/spi/spi-nor-ids.c | 5 +++++
>   1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index d3b84574ac..973b6f86c9 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -107,6 +107,11 @@ const struct flash_info spi_nor_ids[] = {
>   			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>   			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>   	},
> +	{
> +		INFO("gd25q128", 0xc84018, 0, 64 * 1024, 256,
> +			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> +			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> +	},
>   	{
>   		INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
>   			SECT_4K | SPI_NOR_DUAL_READ |
> 

You can drop this patch. The support for this SPI NOR is now included
in mainline.

Thanks,
Stefan