[U-Boot] [PATCH 00/10] mx5: Fix clocks

[U-Boot] [PATCH 00/10] mx5: Fix clocks

[Benoît Thébaudeau]

Hi all,

This series fixes the mx5 clocks. The previous code was full of bugs and missing
parts. There is nothing special to say for each patch. Everything comes from the
reference manuals.

Best regards,
Beno?t

[U-Boot] [PATCH 01/10] mx5: Undeclare imx_decode_pll()

[Benoît Thébaudeau]

The imx_decode_pll() function does not exist for mx5, so remove its declaration.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 .../arch/arm/include/asm/arch-mx5/clock.h          |    2 --
 1 file changed, 2 deletions(-)

diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/clock.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/clock.h
index 36ea030..8d8fa18 100644
--- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/clock.h
+++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/clock.h
@@ -38,8 +38,6 @@ enum mxc_clock {
 	MXC_PERIPH_CLK,
 };
 
-unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
-
 u32 imx_get_uartclk(void);
 u32 imx_get_fecclk(void);
 unsigned int mxc_get_clock(enum mxc_clock clk);

[U-Boot] [PATCH 02/10] mx5: Use explicit clock gate names

[Benoît Thébaudeau]

Use clock gate definitions having names showing clearly the gated clock instead
of names giving only a register field index.

This change reveals that the USB PHY clock functions were broken on i.MX51, so
this patch fixes those too.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
---
 .../arch/arm/cpu/armv7/mx5/clock.c                 |   39 ++++-
 .../arch/arm/include/asm/arch-mx5/clock.h          |    7 +
 .../arch/arm/include/asm/arch-mx5/crm_regs.h       |  158 +++++++++++++++++++-
 .../drivers/usb/host/ehci-mx5.c                    |    5 +
 .../drivers/video/ipu_common.c                     |    2 +-
 5 files changed, 200 insertions(+), 11 deletions(-)

diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
index c67c3cf..9b083c0 100644
--- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
@@ -110,10 +110,11 @@ void enable_usboh3_clk(unsigned char enable)
 	unsigned int reg;
 
 	reg = readl(&mxc_ccm->CCGR2);
+	reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR2_USBOH3_60M_OFFSET);
 	if (enable)
-		reg |= 1 << MXC_CCM_CCGR2_CG14_OFFSET;
+		reg |= MXC_CCM_CCGR_CG_ON << MXC_CCM_CCGR2_USBOH3_60M_OFFSET;
 	else
-		reg &= ~(1 << MXC_CCM_CCGR2_CG14_OFFSET);
+		reg |= MXC_CCM_CCGR_CG_OFF << MXC_CCM_CCGR2_USBOH3_60M_OFFSET;
 	writel(reg, &mxc_ccm->CCGR2);
 }
 
@@ -137,6 +138,29 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 }
 #endif
 
+#if defined(CONFIG_MX51)
+void set_usb_phy_clk(void)
+{
+	unsigned int reg;
+
+	reg = readl(&mxc_ccm->cscmr1);
+	reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
+	writel(reg, &mxc_ccm->cscmr1);
+}
+
+void enable_usb_phy_clk(unsigned char enable)
+{
+	unsigned int reg;
+
+	reg = readl(&mxc_ccm->CCGR2);
+	reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR2_USB_PHY_OFFSET);
+	if (enable)
+		reg |= MXC_CCM_CCGR_CG_ON << MXC_CCM_CCGR2_USB_PHY_OFFSET;
+	else
+		reg |= MXC_CCM_CCGR_CG_OFF << MXC_CCM_CCGR2_USB_PHY_OFFSET;
+	writel(reg, &mxc_ccm->CCGR2);
+}
+#elif defined(CONFIG_MX53)
 void set_usb_phy1_clk(void)
 {
 	unsigned int reg;
@@ -151,10 +175,11 @@ void enable_usb_phy1_clk(unsigned char enable)
 	unsigned int reg;
 
 	reg = readl(&mxc_ccm->CCGR4);
+	reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR4_USB_PHY1_OFFSET);
 	if (enable)
-		reg |= 1 << MXC_CCM_CCGR4_CG5_OFFSET;
+		reg |= MXC_CCM_CCGR_CG_ON << MXC_CCM_CCGR4_USB_PHY1_OFFSET;
 	else
-		reg &= ~(1 << MXC_CCM_CCGR4_CG5_OFFSET);
+		reg |= MXC_CCM_CCGR_CG_OFF << MXC_CCM_CCGR4_USB_PHY1_OFFSET;
 	writel(reg, &mxc_ccm->CCGR4);
 }
 
@@ -172,12 +197,14 @@ void enable_usb_phy2_clk(unsigned char enable)
 	unsigned int reg;
 
 	reg = readl(&mxc_ccm->CCGR4);
+	reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR4_USB_PHY2_OFFSET);
 	if (enable)
-		reg |= 1 << MXC_CCM_CCGR4_CG6_OFFSET;
+		reg |= MXC_CCM_CCGR_CG_ON << MXC_CCM_CCGR4_USB_PHY2_OFFSET;
 	else
-		reg &= ~(1 << MXC_CCM_CCGR4_CG6_OFFSET);
+		reg |= MXC_CCM_CCGR_CG_OFF << MXC_CCM_CCGR4_USB_PHY2_OFFSET;
 	writel(reg, &mxc_ccm->CCGR4);
 }
+#endif
 
 /*
  * Calculate the frequency of PLLn.
diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/clock.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/clock.h
index 8d8fa18..a03e61a 100644
--- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/clock.h
+++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/clock.h
@@ -42,8 +42,15 @@ u32 imx_get_uartclk(void);
 u32 imx_get_fecclk(void);
 unsigned int mxc_get_clock(enum mxc_clock clk);
 int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
+#if defined(CONFIG_MX51)
+void set_usb_phy_clk(void);
+void enable_usb_phy_clk(unsigned char enable);
+#elif defined(CONFIG_MX53)
+void set_usb_phy1_clk(void);
+void enable_usb_phy1_clk(unsigned char enable);
 void set_usb_phy2_clk(void);
 void enable_usb_phy2_clk(unsigned char enable);
+#endif
 void set_usboh3_clk(void);
 void enable_usboh3_clk(unsigned char enable);
 void mxc_set_sata_internal_clock(void);
diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/crm_regs.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/crm_regs.h
index 4e0fc1b..4fd8dba 100644
--- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -200,11 +200,161 @@ struct mxc_ccm_reg {
 
 /* Define the bits in register CCGRx */
 #define MXC_CCM_CCGR_CG_MASK				0x3
+#define MXC_CCM_CCGR_CG_OFF				0x0
+#define MXC_CCM_CCGR_CG_RUN_ON				0x1
+#define MXC_CCM_CCGR_CG_ON				0x3
 
-#define MXC_CCM_CCGR4_CG5_OFFSET			10
-#define MXC_CCM_CCGR4_CG6_OFFSET			12
-#define MXC_CCM_CCGR5_CG5_OFFSET			10
-#define MXC_CCM_CCGR2_CG14_OFFSET			28
+#define MXC_CCM_CCGR0_ARM_BUS_OFFSET			0
+#define MXC_CCM_CCGR0_ARM_AXI_OFFSET			2
+#define MXC_CCM_CCGR0_ARM_DEBUG_OFFSET			4
+#define MXC_CCM_CCGR0_TZIC_OFFSET			6
+#define MXC_CCM_CCGR0_DAP_OFFSET			8
+#define MXC_CCM_CCGR0_TPIU_OFFSET			10
+#define MXC_CCM_CCGR0_CTI2_OFFSET			12
+#define MXC_CCM_CCGR0_CTI3_OFFSET			14
+#define MXC_CCM_CCGR0_AHBMUX1_OFFSET			16
+#define MXC_CCM_CCGR0_AHBMUX2_OFFSET			18
+#define MXC_CCM_CCGR0_ROMCP_OFFSET			20
+#define MXC_CCM_CCGR0_ROM_OFFSET			22
+#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET			24
+#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET			26
+#define MXC_CCM_CCGR0_AHB_MAX_OFFSET			28
+#define MXC_CCM_CCGR0_IIM_OFFSET			30
+
+#define MXC_CCM_CCGR1_TMAX1_OFFSET			0
+#define MXC_CCM_CCGR1_TMAX2_OFFSET			2
+#define MXC_CCM_CCGR1_TMAX3_OFFSET			4
+#define MXC_CCM_CCGR1_UART1_IPG_OFFSET			6
+#define MXC_CCM_CCGR1_UART1_PER_OFFSET			8
+#define MXC_CCM_CCGR1_UART2_IPG_OFFSET			10
+#define MXC_CCM_CCGR1_UART2_PER_OFFSET			12
+#define MXC_CCM_CCGR1_UART3_IPG_OFFSET			14
+#define MXC_CCM_CCGR1_UART3_PER_OFFSET			16
+#define MXC_CCM_CCGR1_I2C1_OFFSET			18
+#define MXC_CCM_CCGR1_I2C2_OFFSET			20
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET			22
+#define MXC_CCM_CCGR1_HSI2C_SERIAL_OFFSET		24
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR1_I2C3_OFFSET			22
+#endif
+#define MXC_CCM_CCGR1_FIRI_IPG_OFFSET			26
+#define MXC_CCM_CCGR1_FIRI_SERIAL_OFFSET		28
+#define MXC_CCM_CCGR1_SCC_OFFSET			30
+
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR2_USB_PHY_OFFSET			0
+#endif
+#define MXC_CCM_CCGR2_EPIT1_IPG_OFFSET			2
+#define MXC_CCM_CCGR2_EPIT1_HF_OFFSET			4
+#define MXC_CCM_CCGR2_EPIT2_IPG_OFFSET			6
+#define MXC_CCM_CCGR2_EPIT2_HF_OFFSET			8
+#define MXC_CCM_CCGR2_PWM1_IPG_OFFSET			10
+#define MXC_CCM_CCGR2_PWM1_HF_OFFSET			12
+#define MXC_CCM_CCGR2_PWM2_IPG_OFFSET			14
+#define MXC_CCM_CCGR2_PWM2_HF_OFFSET			16
+#define MXC_CCM_CCGR2_GPT_IPG_OFFSET			18
+#define MXC_CCM_CCGR2_GPT_HF_OFFSET			20
+#define MXC_CCM_CCGR2_OWIRE_OFFSET			22
+#define MXC_CCM_CCGR2_FEC_OFFSET			24
+#define MXC_CCM_CCGR2_USBOH3_IPG_AHB_OFFSET		26
+#define MXC_CCM_CCGR2_USBOH3_60M_OFFSET			28
+#define MXC_CCM_CCGR2_TVE_OFFSET			30
+
+#define MXC_CCM_CCGR3_ESDHC1_IPG_OFFSET			0
+#define MXC_CCM_CCGR3_ESDHC1_PER_OFFSET			2
+#define MXC_CCM_CCGR3_ESDHC2_IPG_OFFSET			4
+#define MXC_CCM_CCGR3_ESDHC2_PER_OFFSET			6
+#define MXC_CCM_CCGR3_ESDHC3_IPG_OFFSET			8
+#define MXC_CCM_CCGR3_ESDHC3_PER_OFFSET			10
+#define MXC_CCM_CCGR3_ESDHC4_IPG_OFFSET			12
+#define MXC_CCM_CCGR3_ESDHC4_PER_OFFSET			14
+#define MXC_CCM_CCGR3_SSI1_IPG_OFFSET			16
+#define MXC_CCM_CCGR3_SSI1_SSI_OFFSET			18
+#define MXC_CCM_CCGR3_SSI2_IPG_OFFSET			20
+#define MXC_CCM_CCGR3_SSI2_SSI_OFFSET			22
+#define MXC_CCM_CCGR3_SSI3_IPG_OFFSET			24
+#define MXC_CCM_CCGR3_SSI3_SSI_OFFSET			26
+#define MXC_CCM_CCGR3_SSI_EXT1_OFFSET			28
+#define MXC_CCM_CCGR3_SSI_EXT2_OFFSET			30
+
+#define MXC_CCM_CCGR4_PATA_OFFSET			0
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR4_SIM_IPG_OFFSET			2
+#define MXC_CCM_CCGR4_SIM_SERIAL_OFFSET			4
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR4_SATA_OFFSET			2
+#define MXC_CCM_CCGR4_CAN2_IPG_OFFSET			6
+#define MXC_CCM_CCGR4_CAN2_SERIAL_OFFSET		8
+#define MXC_CCM_CCGR4_USB_PHY1_OFFSET			10
+#define MXC_CCM_CCGR4_USB_PHY2_OFFSET			12
+#endif
+#define MXC_CCM_CCGR4_SAHARA_OFFSET			14
+#define MXC_CCM_CCGR4_RTIC_OFFSET			16
+#define MXC_CCM_CCGR4_ECSPI1_IPG_OFFSET			18
+#define MXC_CCM_CCGR4_ECSPI1_PER_OFFSET			20
+#define MXC_CCM_CCGR4_ECSPI2_IPG_OFFSET			22
+#define MXC_CCM_CCGR4_ECSPI2_PER_OFFSET			24
+#define MXC_CCM_CCGR4_CSPI_IPG_OFFSET			26
+#define MXC_CCM_CCGR4_SRTC_OFFSET			28
+#define MXC_CCM_CCGR4_SDMA_OFFSET			30
+
+#define MXC_CCM_CCGR5_SPBA_OFFSET			0
+#define MXC_CCM_CCGR5_GPU_OFFSET			2
+#define MXC_CCM_CCGR5_GARB_OFFSET			4
+#define MXC_CCM_CCGR5_VPU_OFFSET			6
+#define MXC_CCM_CCGR5_VPU_REF_OFFSET			8
+#define MXC_CCM_CCGR5_IPU_OFFSET			10
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR5_IPUMUX12_OFFSET			12
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR5_IPUMUX1_OFFSET			12
+#endif
+#define MXC_CCM_CCGR5_EMI_FAST_OFFSET			14
+#define MXC_CCM_CCGR5_EMI_SLOW_OFFSET			16
+#define MXC_CCM_CCGR5_EMI_INT1_OFFSET			18
+#define MXC_CCM_CCGR5_EMI_ENFC_OFFSET			20
+#define MXC_CCM_CCGR5_EMI_WRCK_OFFSET			22
+#define MXC_CCM_CCGR5_GPC_IPG_OFFSET			24
+#define MXC_CCM_CCGR5_SPDIF0_OFFSET			26
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR5_SPDIF1_OFFSET			28
+#endif
+#define MXC_CCM_CCGR5_SPDIF_IPG_OFFSET			30
+
+#if defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_IPUMUX2_OFFSET			0
+#define MXC_CCM_CCGR6_OCRAM_OFFSET			2
+#endif
+#define MXC_CCM_CCGR6_CSI_MCLK1_OFFSET			4
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR6_CSI_MCLK2_OFFSET			6
+#define MXC_CCM_CCGR6_EMI_GARB_OFFSET			8
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_EMI_INT2_OFFSET			8
+#endif
+#define MXC_CCM_CCGR6_IPU_DI0_OFFSET			10
+#define MXC_CCM_CCGR6_IPU_DI1_OFFSET			12
+#define MXC_CCM_CCGR6_GPU2D_OFFSET			14
+#if defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_ESAI_IPG_OFFSET			16
+#define MXC_CCM_CCGR6_ESAI_ROOT_OFFSET			18
+#define MXC_CCM_CCGR6_CAN1_IPG_OFFSET			20
+#define MXC_CCM_CCGR6_CAN1_SERIAL_OFFSET		22
+#define MXC_CCM_CCGR6_PL301_4X1_OFFSET			24
+#define MXC_CCM_CCGR6_PL301_2X2_OFFSET			26
+#define MXC_CCM_CCGR6_LDB_DI0_OFFSET			28
+#define MXC_CCM_CCGR6_LDB_DI1_OFFSET			30
+
+#define MXC_CCM_CCGR7_ASRC_IPG_OFFSET			0
+#define MXC_CCM_CCGR7_ASRC_ASRCK_OFFSET			2
+#define MXC_CCM_CCGR7_MLB_OFFSET			4
+#define MXC_CCM_CCGR7_IEEE1588_OFFSET			6
+#define MXC_CCM_CCGR7_UART4_IPG_OFFSET			8
+#define MXC_CCM_CCGR7_UART4_PER_OFFSET			10
+#define MXC_CCM_CCGR7_UART5_IPG_OFFSET			12
+#define MXC_CCM_CCGR7_UART5_PER_OFFSET			14
+#endif
 
 /* Define the bits in register CLPCR */
 #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS                 (0x1 << 18)
diff --git u-boot-4d3c95f.orig/drivers/usb/host/ehci-mx5.c u-boot-4d3c95f/drivers/usb/host/ehci-mx5.c
index 58cdcbe..079c567 100644
--- u-boot-4d3c95f.orig/drivers/usb/host/ehci-mx5.c
+++ u-boot-4d3c95f/drivers/usb/host/ehci-mx5.c
@@ -221,8 +221,13 @@ int ehci_hcd_init(void)
 
 	set_usboh3_clk();
 	enable_usboh3_clk(1);
+#if defined(CONFIG_MX51) && CONFIG_MXC_USB_PORT == 0
+	set_usb_phy_clk();
+	enable_usb_phy_clk(1);
+#elif defined(CONFIG_MX53)
 	set_usb_phy2_clk();
 	enable_usb_phy2_clk(1);
+#endif
 	mdelay(1);
 
 	/* Do board specific initialization */
diff --git u-boot-4d3c95f.orig/drivers/video/ipu_common.c u-boot-4d3c95f/drivers/video/ipu_common.c
index 2020da9..7869d65 100644
--- u-boot-4d3c95f.orig/drivers/video/ipu_common.c
+++ u-boot-4d3c95f/drivers/video/ipu_common.c
@@ -213,7 +213,7 @@ static struct clk ipu_clk = {
 	.rate = CONFIG_IPUV3_CLK,
 	.enable_reg = (u32 *)(CCM_BASE_ADDR +
 		offsetof(struct mxc_ccm_reg, CCGR5)),
-	.enable_shift = MXC_CCM_CCGR5_CG5_OFFSET,
+	.enable_shift = MXC_CCM_CCGR5_IPU_OFFSET,
 	.enable = clk_ipu_enable,
 	.disable = clk_ipu_disable,
 	.usecount = 0,

[U-Boot] [PATCH 03/10] mx5 clocks: Add and use CCSR definitions

[Benoît Thébaudeau]

This fixes config_pll_clk(), which used 0x20 instead of 0x200 for PLL4_CLOCK. 

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 .../arch/arm/cpu/armv7/mx5/clock.c                 |   34 +++++++++++++-------
 .../arch/arm/include/asm/arch-mx5/crm_regs.h       |   17 ++++++++++
 2 files changed, 40 insertions(+), 11 deletions(-)

diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
index 9b083c0..10843a4 100644
--- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
@@ -36,7 +36,9 @@ enum pll_clocks {
 	PLL1_CLOCK = 0,
 	PLL2_CLOCK,
 	PLL3_CLOCK,
+#ifdef CONFIG_MX53
 	PLL4_CLOCK,
+#endif
 	PLL_CLOCKS,
 };
 
@@ -379,10 +381,10 @@ static u32 get_lp_apm(void)
 	u32 ret_val = 0;
 	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
 
-	if (((ccsr >> 9) & 1) == 0)
-		ret_val = CONFIG_SYS_MX5_HCLK;
+	if (ccsr & MXC_CCM_CCSR_LP_APM)
+		ret_val = 32768 * 1024;
 	else
-		ret_val = ((32768 * 1024));
+		ret_val = CONFIG_SYS_MX5_HCLK;
 
 	return ret_val;
 }
@@ -660,40 +662,50 @@ static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
 	switch (index) {
 	case PLL1_CLOCK:
 		/* Switch ARM to PLL2 clock */
-		__raw_writel(ccsr | 0x4, &mxc_ccm->ccsr);
+		__raw_writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
+				&mxc_ccm->ccsr);
 		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
 					pll_param->mfi, pll_param->mfn,
 					pll_param->mfd);
 		/* Switch back */
-		__raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr);
+		__raw_writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
+				&mxc_ccm->ccsr);
 		break;
 	case PLL2_CLOCK:
 		/* Switch to pll2 bypass clock */
-		__raw_writel(ccsr | 0x2, &mxc_ccm->ccsr);
+		__raw_writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
+				&mxc_ccm->ccsr);
 		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
 					pll_param->mfi, pll_param->mfn,
 					pll_param->mfd);
 		/* Switch back */
-		__raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr);
+		__raw_writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
+				&mxc_ccm->ccsr);
 		break;
 	case PLL3_CLOCK:
 		/* Switch to pll3 bypass clock */
-		__raw_writel(ccsr | 0x1, &mxc_ccm->ccsr);
+		__raw_writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
+				&mxc_ccm->ccsr);
 		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
 					pll_param->mfi, pll_param->mfn,
 					pll_param->mfd);
 		/* Switch back */
-		__raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr);
+		__raw_writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
+				&mxc_ccm->ccsr);
 		break;
+#ifdef CONFIG_MX53
 	case PLL4_CLOCK:
 		/* Switch to pll4 bypass clock */
-		__raw_writel(ccsr | 0x20, &mxc_ccm->ccsr);
+		__raw_writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
+				&mxc_ccm->ccsr);
 		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
 					pll_param->mfi, pll_param->mfn,
 					pll_param->mfd);
 		/* Switch back */
-		__raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr);
+		__raw_writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
+				&mxc_ccm->ccsr);
 		break;
+#endif
 	default:
 		return -EINVAL;
 	}
diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/crm_regs.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/crm_regs.h
index 4fd8dba..7c21351 100644
--- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -82,6 +82,23 @@ struct mxc_ccm_reg {
 	u32 cmeor;
 };
 
+/* Define the bits in register CCSR */
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCSR_LP_APM			(0x1 << 9)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCSR_LP_APM			(0x1 << 10)
+#define MXC_CCM_CCSR_PLL4_SW_CLK_SEL		(0x1 << 9)
+#endif
+#define MXC_CCM_CCSR_STEP_SEL_OFFSET		7
+#define MXC_CCM_CCSR_STEP_SEL_MASK		(0x3 << 7)
+#define MXC_CCM_CCSR_PLL2_DIV_PODF_OFFSET	5
+#define MXC_CCM_CCSR_PLL2_DIV_PODF_MASK		(0x3 << 5)
+#define MXC_CCM_CCSR_PLL3_DIV_PODF_OFFSET	3
+#define MXC_CCM_CCSR_PLL3_DIV_PODF_MASK		(0x3 << 3)
+#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL		(0x1 << 2)
+#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL		(0x1 << 1)
+#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL		0x1
+
 /* Define the bits in register CACRR */
 #define MXC_CCM_CACRR_ARM_PODF_OFFSET		0
 #define MXC_CCM_CACRR_ARM_PODF_MASK		0x7

[U-Boot] [PATCH 04/10] mx5 clocks: Fix get_lp_apm()

[Benoît Thébaudeau]

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 .../arch/arm/cpu/armv7/mx5/clock.c                 |   24 +++++++++++++++++++-
 .../arch/arm/include/asm/arch-mx5/crm_regs.h       |   13 +++++++++++
 2 files changed, 36 insertions(+), 1 deletion(-)

diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
index 10843a4..408fb54 100644
--- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
@@ -262,6 +262,24 @@ static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
 	return ret;
 }
 
+#ifdef CONFIG_MX51
+/*
+ * This function returns the Frequency Pre-Multiplier clock.
+ */
+static u32 get_fpm(void)
+{
+	u32 mult;
+	u32 ccr = __raw_readl(&mxc_ccm->ccr);
+
+	if (ccr & MXC_CCM_CCR_FPM_MULT)
+		mult = 1024;
+	else
+		mult = 512;
+
+	return CONFIG_SYS_MX5_CLK32 * mult;
+}
+#endif
+
 /*
  * Get mcu main rate
  */
@@ -382,7 +400,11 @@ static u32 get_lp_apm(void)
 	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
 
 	if (ccsr & MXC_CCM_CCSR_LP_APM)
-		ret_val = 32768 * 1024;
+#if defined(CONFIG_MX51)
+		ret_val = get_fpm();
+#elif defined(CONFIG_MX53)
+		ret_val = decode_pll(mxc_plls[PLL4_CLOCK], CONFIG_SYS_MX5_HCLK);
+#endif
 	else
 		ret_val = CONFIG_SYS_MX5_HCLK;
 
diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/crm_regs.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/crm_regs.h
index 7c21351..c208de9 100644
--- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -82,6 +82,19 @@ struct mxc_ccm_reg {
 	u32 cmeor;
 };
 
+/* Define the bits in register CCR */
+#define MXC_CCM_CCR_COSC_EN			(0x1 << 12)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCR_FPM_MULT			(0x1 << 11)
+#endif
+#define MXC_CCM_CCR_CAMP2_EN			(0x1 << 10)
+#define MXC_CCM_CCR_CAMP1_EN			(0x1 << 9)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCR_FPM_EN			(0x1 << 8)
+#endif
+#define MXC_CCM_CCR_OSCNT_OFFSET		0
+#define MXC_CCM_CCR_OSCNT_MASK			0xFF
+
 /* Define the bits in register CCSR */
 #if defined(CONFIG_MX51)
 #define MXC_CCM_CCSR_LP_APM			(0x1 << 9)

[U-Boot] [PATCH 05/10] mx5 clocks: Fix get_periph_clk()

[Benoît Thébaudeau]

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 .../arch/arm/cpu/armv7/mx5/clock.c                 |   42 ++++++++++----------
 1 file changed, 22 insertions(+), 20 deletions(-)

diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
index 408fb54..b92ac49 100644
--- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
@@ -281,6 +281,26 @@ static u32 get_fpm(void)
 #endif
 
 /*
+ * This function returns the low power audio clock.
+ */
+static u32 get_lp_apm(void)
+{
+	u32 ret_val = 0;
+	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
+
+	if (ccsr & MXC_CCM_CCSR_LP_APM)
+#if defined(CONFIG_MX51)
+		ret_val = get_fpm();
+#elif defined(CONFIG_MX53)
+		ret_val = decode_pll(mxc_plls[PLL4_CLOCK], CONFIG_SYS_MX5_HCLK);
+#endif
+	else
+		ret_val = CONFIG_SYS_MX5_HCLK;
+
+	return ret_val;
+}
+
+/*
  * Get mcu main rate
  */
 u32 get_mcu_main_clk(void)
@@ -310,6 +330,8 @@ u32 get_periph_clk(void)
 		return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
 	case 1:
 		return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
+	case 2:
+		return get_lp_apm();
 	default:
 		return 0;
 	}
@@ -392,26 +414,6 @@ static u32 get_uart_clk(void)
 }
 
 /*
- * This function returns the low power audio clock.
- */
-static u32 get_lp_apm(void)
-{
-	u32 ret_val = 0;
-	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
-
-	if (ccsr & MXC_CCM_CCSR_LP_APM)
-#if defined(CONFIG_MX51)
-		ret_val = get_fpm();
-#elif defined(CONFIG_MX53)
-		ret_val = decode_pll(mxc_plls[PLL4_CLOCK], CONFIG_SYS_MX5_HCLK);
-#endif
-	else
-		ret_val = CONFIG_SYS_MX5_HCLK;
-
-	return ret_val;
-}
-
-/*
  * get cspi clock rate.
  */
 static u32 imx_get_cspiclk(void)

[U-Boot] [PATCH 06/10] mx5 clocks: Fix get_ipg_per_clk()

[Benoît Thébaudeau]

This fixes the "IPG PERCLK" frequency printed by the clocks command.

It also fixes i2c support.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 .../arch/arm/cpu/armv7/mx5/clock.c                 |   11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
index b92ac49..b13c55a 100644
--- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
@@ -359,11 +359,15 @@ static u32 get_ipg_clk(void)
  */
 static u32 get_ipg_per_clk(void)
 {
-	u32 pred1, pred2, podf;
+	u32 freq, pred1, pred2, podf;
 
 	if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
 		return get_ipg_clk();
-	/* Fixme: not handle what about lpm*/
+
+	if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL)
+		freq = get_lp_apm();
+	else
+		freq = get_periph_clk();
 	podf = __raw_readl(&mxc_ccm->cbcdr);
 	pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
 		MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
@@ -371,8 +375,7 @@ static u32 get_ipg_per_clk(void)
 		MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
 	podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
 		MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
-
-	return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
+	return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
 }
 
 /*

[U-Boot] [PATCH 07/10] mx5 clocks: Fix get_uart_clk()

[Benoît Thébaudeau]

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 .../arch/arm/cpu/armv7/mx5/clock.c                 |   45 ++++++++++++--------
 1 file changed, 27 insertions(+), 18 deletions(-)

diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
index b13c55a..75a6eae 100644
--- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
@@ -378,31 +378,40 @@ static u32 get_ipg_per_clk(void)
 	return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
 }
 
+/* Get the output clock rate of a standard PLL MUX for peripherals. */
+static u32 get_standard_pll_sel_clk(u32 clk_sel)
+{
+	u32 freq;
+
+	switch (clk_sel & 0x3) {
+	case 0:
+		freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
+		break;
+	case 1:
+		freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
+		break;
+	case 2:
+		freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
+		break;
+	case 3:
+		freq = get_lp_apm();
+		break;
+	}
+
+	return freq;
+}
+
 /*
  * Get the rate of uart clk.
  */
 static u32 get_uart_clk(void)
 {
-	unsigned int freq, reg, pred, podf;
+	unsigned int clk_sel, freq, reg, pred, podf;
 
 	reg = __raw_readl(&mxc_ccm->cscmr1);
-	switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
-		MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
-	case 0x0:
-		freq = decode_pll(mxc_plls[PLL1_CLOCK],
-				    CONFIG_SYS_MX5_HCLK);
-		break;
-	case 0x1:
-		freq = decode_pll(mxc_plls[PLL2_CLOCK],
-				    CONFIG_SYS_MX5_HCLK);
-		break;
-	case 0x2:
-		freq = decode_pll(mxc_plls[PLL3_CLOCK],
-				    CONFIG_SYS_MX5_HCLK);
-		break;
-	default:
-		return 66500000;
-	}
+	clk_sel = (reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
+			MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET;
+	freq = get_standard_pll_sel_clk(clk_sel);
 
 	reg = __raw_readl(&mxc_ccm->cscdr1);
 

[U-Boot] [PATCH 08/10] mx5 clocks: Simplify imx_get_cspiclk()

[Benoît Thébaudeau]

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 .../arch/arm/cpu/armv7/mx5/clock.c                 |   26 +++-----------------
 1 file changed, 3 insertions(+), 23 deletions(-)

diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
index 75a6eae..0801e4f 100644
--- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
@@ -430,7 +430,7 @@ static u32 get_uart_clk(void)
  */
 static u32 imx_get_cspiclk(void)
 {
-	u32 ret_val = 0, pdf, pre_pdf, clk_sel;
+	u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq;
 	u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
 	u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2);
 
@@ -440,28 +440,8 @@ static u32 imx_get_cspiclk(void)
 			>> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
 	clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
 			>> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
-
-	switch (clk_sel) {
-	case 0:
-		ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
-					CONFIG_SYS_MX5_HCLK) /
-					((pre_pdf + 1) * (pdf + 1));
-		break;
-	case 1:
-		ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
-					CONFIG_SYS_MX5_HCLK) /
-					((pre_pdf + 1) * (pdf + 1));
-		break;
-	case 2:
-		ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
-					CONFIG_SYS_MX5_HCLK) /
-					((pre_pdf + 1) * (pdf + 1));
-		break;
-	default:
-		ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
-		break;
-	}
-
+	freq = get_standard_pll_sel_clk(clk_sel);
+	ret_val = freq / ((pre_pdf + 1) * (pdf + 1));
 	return ret_val;
 }
 

[U-Boot] [PATCH 09/10] mx5 clocks: Fix eSDHC clock

[Benoît Thébaudeau]

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 .../arch/arm/cpu/armv7/imx-common/speed.c          |    6 ---
 .../arch/arm/cpu/armv7/mx5/clock.c                 |   52 ++++++++++++++++++++
 .../arch/arm/include/asm/arch-mx5/clock.h          |    4 ++
 3 files changed, 56 insertions(+), 6 deletions(-)

diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/imx-common/speed.c u-boot-4d3c95f/arch/arm/cpu/armv7/imx-common/speed.c
index 80989c4..d9cb7bc 100644
--- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/imx-common/speed.c
+++ u-boot-4d3c95f/arch/arm/cpu/armv7/imx-common/speed.c
@@ -34,12 +34,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int get_clocks(void)
 {
-#ifdef CONFIG_FSL_ESDHC
-#ifdef CONFIG_FSL_USDHC
 	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-#else
-	gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK);
-#endif
-#endif
 	return 0;
 }
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
index 0801e4f..a0339f6 100644
--- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
@@ -445,6 +445,50 @@ static u32 imx_get_cspiclk(void)
 	return ret_val;
 }
 
+/*
+ * get esdhc clock rate.
+ */
+static u32 get_esdhc_clk(u32 port)
+{
+	u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;
+	u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
+	u32 cscdr1 = __raw_readl(&mxc_ccm->cscdr1);
+
+	switch (port) {
+	case 0:
+		clk_sel = (cscmr1 & MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK) >>
+				MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET;
+		pred = (cscdr1 & MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) >>
+				MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET;
+		podf = (cscdr1 & MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) >>
+				MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET;
+		break;
+	case 1:
+		clk_sel = (cscmr1 & MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK) >>
+				MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET;
+		pred = (cscdr1 & MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK) >>
+				MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET;
+		podf = (cscdr1 & MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK) >>
+				MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET;
+		break;
+	case 2:
+		if (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_CLK_SEL)
+			return get_esdhc_clk(1);
+		else
+			return get_esdhc_clk(0);
+	case 3:
+		if (cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL)
+			return get_esdhc_clk(1);
+		else
+			return get_esdhc_clk(0);
+	default:
+		break;
+	}
+
+	freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));
+	return freq;
+}
+
 static u32 get_axi_a_clk(void)
 {
 	u32 cbcdr =  __raw_readl(&mxc_ccm->cbcdr);
@@ -532,6 +576,14 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 		return get_uart_clk();
 	case MXC_CSPI_CLK:
 		return imx_get_cspiclk();
+	case MXC_ESDHC_CLK:
+		return get_esdhc_clk(0);
+	case MXC_ESDHC2_CLK:
+		return get_esdhc_clk(1);
+	case MXC_ESDHC3_CLK:
+		return get_esdhc_clk(2);
+	case MXC_ESDHC4_CLK:
+		return get_esdhc_clk(3);
 	case MXC_FEC_CLK:
 		return decode_pll(mxc_plls[PLL1_CLOCK],
 				    CONFIG_SYS_MX5_HCLK);
diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/clock.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/clock.h
index a03e61a..5eeca2a 100644
--- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/clock.h
+++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/clock.h
@@ -31,6 +31,10 @@ enum mxc_clock {
 	MXC_IPG_PERCLK,
 	MXC_UART_CLK,
 	MXC_CSPI_CLK,
+	MXC_ESDHC_CLK,
+	MXC_ESDHC2_CLK,
+	MXC_ESDHC3_CLK,
+	MXC_ESDHC4_CLK,
 	MXC_FEC_CLK,
 	MXC_SATA_CLK,
 	MXC_DDR_CLK,

[U-Boot] [PATCH 10/10] mx5 clocks: Fix MXC_FEC_CLK

[Benoît Thébaudeau]

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 .../arch/arm/cpu/armv7/mx5/clock.c                 |    6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
index a0339f6..dff8229 100644
--- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
@@ -585,8 +585,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 	case MXC_ESDHC4_CLK:
 		return get_esdhc_clk(3);
 	case MXC_FEC_CLK:
-		return decode_pll(mxc_plls[PLL1_CLOCK],
-				    CONFIG_SYS_MX5_HCLK);
+		return get_ipg_clk();
 	case MXC_SATA_CLK:
 		return get_ahb_clk();
 	case MXC_DDR_CLK:
@@ -602,10 +601,9 @@ u32 imx_get_uartclk(void)
 	return get_uart_clk();
 }
 
-
 u32 imx_get_fecclk(void)
 {
-	return mxc_get_clock(MXC_IPG_CLK);
+	return get_ipg_clk();
 }
 
 static int gcd(int m, int n)

[U-Boot] [PATCH 02/10] mx5: Use explicit clock gate names

[Marek Vasut]

Dear Beno?t Th?baudeau,

> Use clock gate definitions having names showing clearly the gated clock
> instead of names giving only a register field index.
> 
> This change reveals that the USB PHY clock functions were broken on i.MX51,
> so this patch fixes those too.

Expanding CC /wrt this mx51 usb biz.

> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> ---
>  .../arch/arm/cpu/armv7/mx5/clock.c                 |   39 ++++-
>  .../arch/arm/include/asm/arch-mx5/clock.h          |    7 +
>  .../arch/arm/include/asm/arch-mx5/crm_regs.h       |  158
> +++++++++++++++++++- .../drivers/usb/host/ehci-mx5.c                    | 
>   5 +
>  .../drivers/video/ipu_common.c                     |    2 +-
>  5 files changed, 200 insertions(+), 11 deletions(-)
> 
> diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
> u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c index c67c3cf..9b083c0
> 100644
> --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
> +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
> @@ -110,10 +110,11 @@ void enable_usboh3_clk(unsigned char enable)
>  	unsigned int reg;
> 
>  	reg = readl(&mxc_ccm->CCGR2);
> +	reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR2_USBOH3_60M_OFFSET);

What's this addition?

>  	if (enable)
> -		reg |= 1 << MXC_CCM_CCGR2_CG14_OFFSET;
> +		reg |= MXC_CCM_CCGR_CG_ON << MXC_CCM_CCGR2_USBOH3_60M_OFFSET;

Can't you make it like ... MXC_CCM_CCGR2_USBOH3_60M(<on/off>) ... which would 
emit the correct bit? So you'd wrap the bitshift into it as well ... also, using 
clrsetbits_le32() won't hurt here.

>  	else
> -		reg &= ~(1 << MXC_CCM_CCGR2_CG14_OFFSET);
> +		reg |= MXC_CCM_CCGR_CG_OFF << MXC_CCM_CCGR2_USBOH3_60M_OFFSET;
>  	writel(reg, &mxc_ccm->CCGR2);
>  }
> 
> @@ -137,6 +138,29 @@ int enable_i2c_clk(unsigned char enable, unsigned
> i2c_num) }
>  #endif
> 
> +#if defined(CONFIG_MX51)
> +void set_usb_phy_clk(void)
> +{
> +	unsigned int reg;
> +
> +	reg = readl(&mxc_ccm->cscmr1);
> +	reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
> +	writel(reg, &mxc_ccm->cscmr1);

clrbits_le32() etc., please fix globally.

This doesn't even fit into this patch, so please split away.
[...]

[U-Boot] [PATCH 03/10] mx5 clocks: Add and use CCSR definitions

[Marek Vasut]

Dear Beno?t Th?baudeau,

> This fixes config_pll_clk(), which used 0x20 instead of 0x200 for
> PLL4_CLOCK.
> 
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
>  .../arch/arm/cpu/armv7/mx5/clock.c                 |   34
> +++++++++++++------- .../arch/arm/include/asm/arch-mx5/crm_regs.h       | 
>  17 ++++++++++ 2 files changed, 40 insertions(+), 11 deletions(-)
> 
> diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
> u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c index 9b083c0..10843a4
> 100644
> --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
> +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
> @@ -36,7 +36,9 @@ enum pll_clocks {
>  	PLL1_CLOCK = 0,
>  	PLL2_CLOCK,
>  	PLL3_CLOCK,
> +#ifdef CONFIG_MX53
>  	PLL4_CLOCK,
> +#endif
>  	PLL_CLOCKS,
>  };
> 
> @@ -379,10 +381,10 @@ static u32 get_lp_apm(void)
>  	u32 ret_val = 0;
>  	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
> 
> -	if (((ccsr >> 9) & 1) == 0)
> -		ret_val = CONFIG_SYS_MX5_HCLK;
> +	if (ccsr & MXC_CCM_CCSR_LP_APM)
> +		ret_val = 32768 * 1024;
>  	else
> -		ret_val = ((32768 * 1024));
> +		ret_val = CONFIG_SYS_MX5_HCLK;
> 
>  	return ret_val;
>  }
> @@ -660,40 +662,50 @@ static int config_pll_clk(enum pll_clocks index,
> struct pll_param *pll_param) switch (index) {
>  	case PLL1_CLOCK:
>  		/* Switch ARM to PLL2 clock */
> -		__raw_writel(ccsr | 0x4, &mxc_ccm->ccsr);
> +		__raw_writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
> +				&mxc_ccm->ccsr);
>  		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
>  					pll_param->mfi, pll_param->mfn,
>  					pll_param->mfd);
>  		/* Switch back */
> -		__raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr);
> +		__raw_writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
> +				&mxc_ccm->ccsr);

Why use __raw_writel() instead of writel() ? Besides ... again, 
clrsetbits_le32() is a better bet.

>  		break;
>  	case PLL2_CLOCK:
>  		/* Switch to pll2 bypass clock */
> -		__raw_writel(ccsr | 0x2, &mxc_ccm->ccsr);
> +		__raw_writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
> +				&mxc_ccm->ccsr);
>  		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
>  					pll_param->mfi, pll_param->mfn,
>  					pll_param->mfd);
>  		/* Switch back */
> -		__raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr);
> +		__raw_writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
> +				&mxc_ccm->ccsr);
>  		break;
>  	case PLL3_CLOCK:
>  		/* Switch to pll3 bypass clock */
> -		__raw_writel(ccsr | 0x1, &mxc_ccm->ccsr);
> +		__raw_writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
> +				&mxc_ccm->ccsr);
>  		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
>  					pll_param->mfi, pll_param->mfn,
>  					pll_param->mfd);
>  		/* Switch back */
> -		__raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr);
> +		__raw_writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
> +				&mxc_ccm->ccsr);
>  		break;
> +#ifdef CONFIG_MX53
>  	case PLL4_CLOCK:
>  		/* Switch to pll4 bypass clock */
> -		__raw_writel(ccsr | 0x20, &mxc_ccm->ccsr);
> +		__raw_writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
> +				&mxc_ccm->ccsr);
>  		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
>  					pll_param->mfi, pll_param->mfn,
>  					pll_param->mfd);
>  		/* Switch back */
> -		__raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr);
> +		__raw_writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
> +				&mxc_ccm->ccsr);
>  		break;
> +#endif
>  	default:
>  		return -EINVAL;
>  	}
> diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/crm_regs.h
> u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/crm_regs.h index
> 4fd8dba..7c21351 100644
> --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/crm_regs.h
> +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/crm_regs.h
> @@ -82,6 +82,23 @@ struct mxc_ccm_reg {
>  	u32 cmeor;
>  };
> 
> +/* Define the bits in register CCSR */
> +#if defined(CONFIG_MX51)
> +#define MXC_CCM_CCSR_LP_APM			(0x1 << 9)
> +#elif defined(CONFIG_MX53)
> +#define MXC_CCM_CCSR_LP_APM			(0x1 << 10)
> +#define MXC_CCM_CCSR_PLL4_SW_CLK_SEL		(0x1 << 9)
> +#endif
> +#define MXC_CCM_CCSR_STEP_SEL_OFFSET		7
> +#define MXC_CCM_CCSR_STEP_SEL_MASK		(0x3 << 7)
> +#define MXC_CCM_CCSR_PLL2_DIV_PODF_OFFSET	5
> +#define MXC_CCM_CCSR_PLL2_DIV_PODF_MASK		(0x3 << 5)
> +#define MXC_CCM_CCSR_PLL3_DIV_PODF_OFFSET	3
> +#define MXC_CCM_CCSR_PLL3_DIV_PODF_MASK		(0x3 << 3)
> +#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL		(0x1 << 2)
> +#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL		(0x1 << 1)
> +#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL		0x1
> +
>  /* Define the bits in register CACRR */
>  #define MXC_CCM_CACRR_ARM_PODF_OFFSET		0
>  #define MXC_CCM_CACRR_ARM_PODF_MASK		0x7

[U-Boot] [PATCH 03/10] mx5 clocks: Add and use CCSR definitions

[Marek Vasut]

Dear Beno?t Th?baudeau,

> Dear Marek Vasut,
> 
> > Dear Beno?t Th?baudeau,
> > 
> > > This fixes config_pll_clk(), which used 0x20 instead of 0x200 for
> > > PLL4_CLOCK.
> > > 
> > > Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> > > Cc: Stefano Babic <sbabic@denx.de>
> > > ---
> > > 
> > >  .../arch/arm/cpu/armv7/mx5/clock.c                 |   34
> > > 
> > > +++++++++++++------- .../arch/arm/include/asm/arch-mx5/crm_regs.h
> > > 
> > >  17 ++++++++++ 2 files changed, 40 insertions(+), 11 deletions(-)
> > > 
> > > diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
> > > u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c index
> > > 9b083c0..10843a4
> > > 100644
> > > --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
> > > +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
> > > @@ -36,7 +36,9 @@ enum pll_clocks {
> > > 
> > >  	PLL1_CLOCK = 0,
> > >  	PLL2_CLOCK,
> > >  	PLL3_CLOCK,
> > > 
> > > +#ifdef CONFIG_MX53
> > > 
> > >  	PLL4_CLOCK,
> > > 
> > > +#endif
> > > 
> > >  	PLL_CLOCKS,
> > >  
> > >  };
> > > 
> > > @@ -379,10 +381,10 @@ static u32 get_lp_apm(void)
> > > 
> > >  	u32 ret_val = 0;
> > >  	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
> > > 
> > > -	if (((ccsr >> 9) & 1) == 0)
> > > -		ret_val = CONFIG_SYS_MX5_HCLK;
> > > +	if (ccsr & MXC_CCM_CCSR_LP_APM)
> > > +		ret_val = 32768 * 1024;
> > > 
> > >  	else
> > > 
> > > -		ret_val = ((32768 * 1024));
> > > +		ret_val = CONFIG_SYS_MX5_HCLK;
> > > 
> > >  	return ret_val;
> > >  
> > >  }
> > > 
> > > @@ -660,40 +662,50 @@ static int config_pll_clk(enum pll_clocks
> > > index,
> > > struct pll_param *pll_param) switch (index) {
> > > 
> > >  	case PLL1_CLOCK:
> > >  		/* Switch ARM to PLL2 clock */
> > > 
> > > -		__raw_writel(ccsr | 0x4, &mxc_ccm->ccsr);
> > > +		__raw_writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
> > > +				&mxc_ccm->ccsr);
> > > 
> > >  		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
> > >  		
> > >  					pll_param->mfi, pll_param->mfn,
> > >  					pll_param->mfd);
> > >  		
> > >  		/* Switch back */
> > > 
> > > -		__raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr);
> > > +		__raw_writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
> > > +				&mxc_ccm->ccsr);
> > 
> > Why use __raw_writel() instead of writel() ? Besides ... again,
> > clrsetbits_le32() is a better bet.
> 
> Sure, but it's again for consistency with the existing code.

Existing code looks crappy, any reason to not fix it ;-)
[...]

[U-Boot] [PATCH 02/10] mx5: Use explicit clock gate names

[Benoît Thébaudeau]

Dear Marek Vasut,

> Dear Beno?t Th?baudeau,
> 
> > Use clock gate definitions having names showing clearly the gated
> > clock
> > instead of names giving only a register field index.
> > 
> > This change reveals that the USB PHY clock functions were broken on
> > i.MX51,
> > so this patch fixes those too.
> 
> Expanding CC /wrt this mx51 usb biz.
> 
> > Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> > Cc: Stefano Babic <sbabic@denx.de>
> > Cc: Marek Vasut <marex@denx.de>
> > ---
> >  .../arch/arm/cpu/armv7/mx5/clock.c                 |   39 ++++-
> >  .../arch/arm/include/asm/arch-mx5/clock.h          |    7 +
> >  .../arch/arm/include/asm/arch-mx5/crm_regs.h       |  158
> > +++++++++++++++++++- .../drivers/usb/host/ehci-mx5.c
> >                    |
> >   5 +
> >  .../drivers/video/ipu_common.c                     |    2 +-
> >  5 files changed, 200 insertions(+), 11 deletions(-)
> > 
> > diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
> > u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c index
> > c67c3cf..9b083c0
> > 100644
> > --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
> > +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
> > @@ -110,10 +110,11 @@ void enable_usboh3_clk(unsigned char enable)
> >  	unsigned int reg;
> > 
> >  	reg = readl(&mxc_ccm->CCGR2);
> > +	reg &= ~(MXC_CCM_CCGR_CG_MASK <<
> > MXC_CCM_CCGR2_USBOH3_60M_OFFSET);
> 
> What's this addition?

It's to clear this 2-bit bit-field before setting it.

> >  	if (enable)
> > -		reg |= 1 << MXC_CCM_CCGR2_CG14_OFFSET;
> > +		reg |= MXC_CCM_CCGR_CG_ON << MXC_CCM_CCGR2_USBOH3_60M_OFFSET;
> 
> Can't you make it like ... MXC_CCM_CCGR2_USBOH3_60M(<on/off>) ...
> which would
> emit the correct bit? So you'd wrap the bitshift into it as well ...
> also, using
> clrsetbits_le32() won't hurt here.

It's only to be consistent with the existing code. A cosmetic patch could be
applied after that for the whole file.

> >  	else
> > -		reg &= ~(1 << MXC_CCM_CCGR2_CG14_OFFSET);
> > +		reg |= MXC_CCM_CCGR_CG_OFF << MXC_CCM_CCGR2_USBOH3_60M_OFFSET;
> >  	writel(reg, &mxc_ccm->CCGR2);
> >  }
> > 
> > @@ -137,6 +138,29 @@ int enable_i2c_clk(unsigned char enable,
> > unsigned
> > i2c_num) }
> >  #endif
> > 
> > +#if defined(CONFIG_MX51)
> > +void set_usb_phy_clk(void)
> > +{
> > +	unsigned int reg;
> > +
> > +	reg = readl(&mxc_ccm->cscmr1);
> > +	reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
> > +	writel(reg, &mxc_ccm->cscmr1);
> 
> clrbits_le32() etc., please fix globally.

Ditto.

> This doesn't even fit into this patch, so please split away.
> [...]

These cosmetic changes are off topic for my series. I don't have much time to
work on that. Perhaps this can be done by someone else later.

Best regards,
Beno?t

[U-Boot] [PATCH 03/10] mx5 clocks: Add and use CCSR definitions

[Benoît Thébaudeau]

Dear Marek Vasut,

> Dear Beno?t Th?baudeau,
> 
> > This fixes config_pll_clk(), which used 0x20 instead of 0x200 for
> > PLL4_CLOCK.
> > 
> > Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> > Cc: Stefano Babic <sbabic@denx.de>
> > ---
> >  .../arch/arm/cpu/armv7/mx5/clock.c                 |   34
> > +++++++++++++------- .../arch/arm/include/asm/arch-mx5/crm_regs.h
> >       |
> >  17 ++++++++++ 2 files changed, 40 insertions(+), 11 deletions(-)
> > 
> > diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
> > u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c index
> > 9b083c0..10843a4
> > 100644
> > --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
> > +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
> > @@ -36,7 +36,9 @@ enum pll_clocks {
> >  	PLL1_CLOCK = 0,
> >  	PLL2_CLOCK,
> >  	PLL3_CLOCK,
> > +#ifdef CONFIG_MX53
> >  	PLL4_CLOCK,
> > +#endif
> >  	PLL_CLOCKS,
> >  };
> > 
> > @@ -379,10 +381,10 @@ static u32 get_lp_apm(void)
> >  	u32 ret_val = 0;
> >  	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
> > 
> > -	if (((ccsr >> 9) & 1) == 0)
> > -		ret_val = CONFIG_SYS_MX5_HCLK;
> > +	if (ccsr & MXC_CCM_CCSR_LP_APM)
> > +		ret_val = 32768 * 1024;
> >  	else
> > -		ret_val = ((32768 * 1024));
> > +		ret_val = CONFIG_SYS_MX5_HCLK;
> > 
> >  	return ret_val;
> >  }
> > @@ -660,40 +662,50 @@ static int config_pll_clk(enum pll_clocks
> > index,
> > struct pll_param *pll_param) switch (index) {
> >  	case PLL1_CLOCK:
> >  		/* Switch ARM to PLL2 clock */
> > -		__raw_writel(ccsr | 0x4, &mxc_ccm->ccsr);
> > +		__raw_writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
> > +				&mxc_ccm->ccsr);
> >  		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
> >  					pll_param->mfi, pll_param->mfn,
> >  					pll_param->mfd);
> >  		/* Switch back */
> > -		__raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr);
> > +		__raw_writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
> > +				&mxc_ccm->ccsr);
> 
> Why use __raw_writel() instead of writel() ? Besides ... again,
> clrsetbits_le32() is a better bet.

Sure, but it's again for consistency with the existing code.

> >  		break;
> >  	case PLL2_CLOCK:
> >  		/* Switch to pll2 bypass clock */
> > -		__raw_writel(ccsr | 0x2, &mxc_ccm->ccsr);
> > +		__raw_writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
> > +				&mxc_ccm->ccsr);
> >  		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
> >  					pll_param->mfi, pll_param->mfn,
> >  					pll_param->mfd);
> >  		/* Switch back */
> > -		__raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr);
> > +		__raw_writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
> > +				&mxc_ccm->ccsr);
> >  		break;
> >  	case PLL3_CLOCK:
> >  		/* Switch to pll3 bypass clock */
> > -		__raw_writel(ccsr | 0x1, &mxc_ccm->ccsr);
> > +		__raw_writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
> > +				&mxc_ccm->ccsr);
> >  		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
> >  					pll_param->mfi, pll_param->mfn,
> >  					pll_param->mfd);
> >  		/* Switch back */
> > -		__raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr);
> > +		__raw_writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
> > +				&mxc_ccm->ccsr);
> >  		break;
> > +#ifdef CONFIG_MX53
> >  	case PLL4_CLOCK:
> >  		/* Switch to pll4 bypass clock */
> > -		__raw_writel(ccsr | 0x20, &mxc_ccm->ccsr);
> > +		__raw_writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
> > +				&mxc_ccm->ccsr);
> >  		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
> >  					pll_param->mfi, pll_param->mfn,
> >  					pll_param->mfd);
> >  		/* Switch back */
> > -		__raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr);
> > +		__raw_writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
> > +				&mxc_ccm->ccsr);
> >  		break;
> > +#endif
> >  	default:
> >  		return -EINVAL;
> >  	}
> > diff --git
> > u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/crm_regs.h
> > u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/crm_regs.h index
> > 4fd8dba..7c21351 100644
> > --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/crm_regs.h
> > +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/crm_regs.h
> > @@ -82,6 +82,23 @@ struct mxc_ccm_reg {
> >  	u32 cmeor;
> >  };
> > 
> > +/* Define the bits in register CCSR */
> > +#if defined(CONFIG_MX51)
> > +#define MXC_CCM_CCSR_LP_APM			(0x1 << 9)
> > +#elif defined(CONFIG_MX53)
> > +#define MXC_CCM_CCSR_LP_APM			(0x1 << 10)
> > +#define MXC_CCM_CCSR_PLL4_SW_CLK_SEL		(0x1 << 9)
> > +#endif
> > +#define MXC_CCM_CCSR_STEP_SEL_OFFSET		7
> > +#define MXC_CCM_CCSR_STEP_SEL_MASK		(0x3 << 7)
> > +#define MXC_CCM_CCSR_PLL2_DIV_PODF_OFFSET	5
> > +#define MXC_CCM_CCSR_PLL2_DIV_PODF_MASK		(0x3 << 5)
> > +#define MXC_CCM_CCSR_PLL3_DIV_PODF_OFFSET	3
> > +#define MXC_CCM_CCSR_PLL3_DIV_PODF_MASK		(0x3 << 3)
> > +#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL		(0x1 << 2)
> > +#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL		(0x1 << 1)
> > +#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL		0x1
> > +
> >  /* Define the bits in register CACRR */
> >  #define MXC_CCM_CACRR_ARM_PODF_OFFSET		0
> >  #define MXC_CCM_CACRR_ARM_PODF_MASK		0x7
> 

Best regards,
Beno?t

[U-Boot] [PATCH 07/10] mx5 clocks: Fix get_uart_clk()

[Stefano Babic]

On 14/08/2012 20:07, Beno?t Th?baudeau wrote:
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---

Hi Beno?t,

>  .../arch/arm/cpu/armv7/mx5/clock.c                 |   45 ++++++++++++--------
>  1 file changed, 27 insertions(+), 18 deletions(-)
> 

You should add in the commit message which is the bug you found and fixed.

> diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
> index b13c55a..75a6eae 100644
> --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
> +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
> @@ -378,31 +378,40 @@ static u32 get_ipg_per_clk(void)
>  	return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
>  }
>  
> +/* Get the output clock rate of a standard PLL MUX for peripherals. */
> +static u32 get_standard_pll_sel_clk(u32 clk_sel)

Why should we pass a parameter to this function ? Can it be used in
another context ? I do not think so, because it decodes the value in the
cscmr1 register.

I think it is better if you move the reading of the cscmr1 register
inside this function and you drop the unneeded parameter.

> +{
> +	u32 freq;
> +
> +	switch (clk_sel & 0x3) {
> +	case 0:
> +		freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
> +		break;
> +	case 1:
> +		freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
> +		break;
> +	case 2:
> +		freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
> +		break;
> +	case 3:
> +		freq = get_lp_apm();
> +		break;

Ok, this is the fix, describe it.

> +	}
> +
> +	return freq;
> +}
> +
>  /*
>   * Get the rate of uart clk.
>   */
>  static u32 get_uart_clk(void)
>  {
> -	unsigned int freq, reg, pred, podf;
> +	unsigned int clk_sel, freq, reg, pred, podf;
>  
>  	reg = __raw_readl(&mxc_ccm->cscmr1);
> -	switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
> -		MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
> -	case 0x0:
> -		freq = decode_pll(mxc_plls[PLL1_CLOCK],
> -				    CONFIG_SYS_MX5_HCLK);
> -		break;
> -	case 0x1:
> -		freq = decode_pll(mxc_plls[PLL2_CLOCK],
> -				    CONFIG_SYS_MX5_HCLK);
> -		break;
> -	case 0x2:
> -		freq = decode_pll(mxc_plls[PLL3_CLOCK],
> -				    CONFIG_SYS_MX5_HCLK);
> -		break;
> -	default:
> -		return 66500000;
> -	}
> +	clk_sel = (reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
> +			MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET;
> +	freq = get_standard_pll_sel_clk(clk_sel);
>  
>  	reg = __raw_readl(&mxc_ccm->cscdr1);
>  
> 

Best regards,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 07/10] mx5 clocks: Fix get_uart_clk()

[Stefano Babic]

On 20/08/2012 11:52, Stefano Babic wrote:
> Why should we pass a parameter to this function ? Can it be used in
> another context ? I do not think so, because it decodes the value in the
> cscmr1 register.
> 
> I think it is better if you move the reading of the cscmr1 register
> inside this function and you drop the unneeded parameter.

Never mind - I had not yet read the next patch. Discharge this comment.

Best regards,
Stefano


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 01/10] mx5: Undeclare imx_decode_pll()

[Stefano Babic]

On 14/08/2012 20:06, Beno?t Th?baudeau wrote:
> The imx_decode_pll() function does not exist for mx5, so remove its declaration.
> 
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 01/14] mx5/6: Define default SoC input clock frequencies

[Benoît Thébaudeau]

Define default SoC input clock frequencies for i.MX5/6 in order to get rid of
duplicated definitions.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Jason Liu <r64343@freescale.com>
Cc: Matt Sealey <matt@genesi-usa.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
---
The CONFIG_SYS_MX{5|6}_HCLK and CONFIG_SYS_MX{5|6}_CLK32 definitions set
to 24000000 and 32768 should also be removed from any new board config file
added in the meantime if this is applied to the next branch instead of the
master branch. I am thinking especially about include/configs/mx6qsabresd.h .

This patch supersedes http://patchwork.ozlabs.org/patch/177303/ .
Changes for v2:
 - Remove duplicated definition usages instead of spreading them.

 .../arch/arm/cpu/armv7/mx5/clock.c                 |   45 +++++++++-----------
 .../arch/arm/cpu/armv7/mx6/clock.c                 |   20 ++++-----
 .../arch/arm/imx-common/timer.c                    |   12 +++---
 .../arch/arm/include/asm/arch-mx5/clock.h          |   14 ++++++
 .../arch/arm/include/asm/arch-mx6/clock.h          |   14 ++++++
 .../board/freescale/mx53loco/mx53loco.c            |    2 +-
 .../include/configs/ima3-mx53.h                    |    3 --
 .../include/configs/mx51_efikamx.h                 |    2 -
 .../include/configs/mx51evk.h                      |    2 -
 .../include/configs/mx53ard.h                      |    2 -
 .../include/configs/mx53evk.h                      |    2 -
 .../include/configs/mx53loco.h                     |    2 -
 .../include/configs/mx53smd.h                      |    2 -
 .../include/configs/mx6qarm2.h                     |    2 -
 .../include/configs/mx6qsabrelite.h                |    2 -
 .../include/configs/vision2.h                      |    2 -
 16 files changed, 64 insertions(+), 64 deletions(-)

diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
index c67c3cf..1f95536 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
@@ -69,7 +69,7 @@ struct fixed_pll_mfd {
 };
 
 const struct fixed_pll_mfd fixed_mfd[] = {
-	{CONFIG_SYS_MX5_HCLK, 24 * 16},
+	{MXC_HCLK, 24 * 16},
 };
 
 struct pll_param {
@@ -242,7 +242,7 @@ u32 get_mcu_main_clk(void)
 
 	reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
 		MXC_CCM_CACRR_ARM_PODF_OFFSET;
-	freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
+	freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
 	return freq / (reg + 1);
 }
 
@@ -255,14 +255,14 @@ u32 get_periph_clk(void)
 
 	reg = __raw_readl(&mxc_ccm->cbcdr);
 	if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
-		return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
+		return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
 	reg = __raw_readl(&mxc_ccm->cbcmr);
 	switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
 		MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
 	case 0:
-		return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
+		return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
 	case 1:
-		return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
+		return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
 	default:
 		return 0;
 	}
@@ -317,16 +317,13 @@ static u32 get_uart_clk(void)
 	switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
 		MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
 	case 0x0:
-		freq = decode_pll(mxc_plls[PLL1_CLOCK],
-				    CONFIG_SYS_MX5_HCLK);
+		freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
 		break;
 	case 0x1:
-		freq = decode_pll(mxc_plls[PLL2_CLOCK],
-				    CONFIG_SYS_MX5_HCLK);
+		freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
 		break;
 	case 0x2:
-		freq = decode_pll(mxc_plls[PLL3_CLOCK],
-				    CONFIG_SYS_MX5_HCLK);
+		freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
 		break;
 	default:
 		return 66500000;
@@ -353,9 +350,9 @@ static u32 get_lp_apm(void)
 	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
 
 	if (((ccsr >> 9) & 1) == 0)
-		ret_val = CONFIG_SYS_MX5_HCLK;
+		ret_val = MXC_HCLK;
 	else
-		ret_val = ((32768 * 1024));
+		ret_val = MXC_CLK32 * 1024;
 
 	return ret_val;
 }
@@ -378,18 +375,15 @@ static u32 imx_get_cspiclk(void)
 
 	switch (clk_sel) {
 	case 0:
-		ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
-					CONFIG_SYS_MX5_HCLK) /
+		ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK) /
 					((pre_pdf + 1) * (pdf + 1));
 		break;
 	case 1:
-		ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
-					CONFIG_SYS_MX5_HCLK) /
+		ret_val = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK) /
 					((pre_pdf + 1) * (pdf + 1));
 		break;
 	case 2:
-		ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
-					CONFIG_SYS_MX5_HCLK) /
+		ret_val = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK) /
 					((pre_pdf + 1) * (pdf + 1));
 		break;
 	default:
@@ -443,7 +437,7 @@ static u32 get_ddr_clk(void)
 		u32 ddr_clk_podf = (cbcdr & MXC_CCM_CBCDR_DDR_PODF_MASK) >> \
 					MXC_CCM_CBCDR_DDR_PODF_OFFSET;
 
-		ret_val = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
+		ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
 		ret_val /= ddr_clk_podf + 1;
 
 		return ret_val;
@@ -488,8 +482,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 	case MXC_CSPI_CLK:
 		return imx_get_cspiclk();
 	case MXC_FEC_CLK:
-		return decode_pll(mxc_plls[PLL1_CLOCK],
-				    CONFIG_SYS_MX5_HCLK);
+		return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
 	case MXC_SATA_CLK:
 		return get_ahb_clk();
 	case MXC_DDR_CLK:
@@ -874,14 +867,14 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	u32 freq;
 
-	freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
+	freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
 	printf("PLL1       %8d MHz\n", freq / 1000000);
-	freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
+	freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
 	printf("PLL2       %8d MHz\n", freq / 1000000);
-	freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
+	freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
 	printf("PLL3       %8d MHz\n", freq / 1000000);
 #ifdef	CONFIG_MX53
-	freq = decode_pll(mxc_plls[PLL4_CLOCK], CONFIG_SYS_MX5_HCLK);
+	freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
 	printf("PLL4       %8d MHz\n", freq / 1000000);
 #endif
 
diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx6/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx6/clock.c
index fddb373..7b31e4f 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx6/clock.c
+++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx6/clock.c
@@ -108,7 +108,7 @@ static u32 get_mcu_main_clk(void)
 	reg = __raw_readl(&imx_ccm->cacrr);
 	reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
 	reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
-	freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
+	freq = decode_pll(PLL_SYS, MXC_HCLK);
 
 	return freq / (reg + 1);
 }
@@ -125,11 +125,11 @@ u32 get_periph_clk(void)
 
 		switch (reg) {
 		case 0:
-			freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
+			freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 			break;
 		case 1:
 		case 2:
-			freq = CONFIG_SYS_MX6_HCLK;
+			freq = MXC_HCLK;
 			break;
 		default:
 			break;
@@ -141,7 +141,7 @@ u32 get_periph_clk(void)
 
 		switch (reg) {
 		case 0:
-			freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
+			freq = decode_pll(PLL_BUS, MXC_HCLK);
 			break;
 		case 1:
 			freq = PLL2_PFD2_FREQ;
@@ -237,7 +237,7 @@ static u32 get_emi_slow_clk(void)
 		root_freq = get_axi_clk();
 		break;
 	case 1:
-		root_freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
+		root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 		break;
 	case 2:
 		root_freq = PLL2_PFD2_FREQ;
@@ -309,7 +309,7 @@ u32 imx_get_uartclk(void)
 
 u32 imx_get_fecclk(void)
 {
-	return decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
+	return decode_pll(PLL_ENET, MXC_HCLK);
 }
 
 int enable_sata_clock(void)
@@ -389,13 +389,13 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	u32 freq;
-	freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
+	freq = decode_pll(PLL_SYS, MXC_HCLK);
 	printf("PLL_SYS    %8d MHz\n", freq / 1000000);
-	freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
+	freq = decode_pll(PLL_BUS, MXC_HCLK);
 	printf("PLL_BUS    %8d MHz\n", freq / 1000000);
-	freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
+	freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 	printf("PLL_OTG    %8d MHz\n", freq / 1000000);
-	freq = decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
+	freq = decode_pll(PLL_ENET, MXC_HCLK);
 	printf("PLL_NET    %8d MHz\n", freq / 1000000);
 
 	printf("\n");
diff --git u-boot-imx-e1eb75b.orig/arch/arm/imx-common/timer.c u-boot-imx-e1eb75b/arch/arm/imx-common/timer.c
index e2725e1..b021903 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/imx-common/timer.c
+++ u-boot-imx-e1eb75b/arch/arm/imx-common/timer.c
@@ -27,6 +27,7 @@
 #include <asm/io.h>
 #include <div64.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
 
 /* General purpose timers registers */
 struct mxc_gpt {
@@ -44,7 +45,6 @@ static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
 #define GPTCR_FRR		(1 << 9)	/* Freerun / restart */
 #define GPTCR_CLKSOURCE_32	(4 << 6)	/* Clock source */
 #define GPTCR_TEN		1		/* Timer enable */
-#define CLK_32KHZ		32768		/* 32Khz input */
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -54,14 +54,14 @@ DECLARE_GLOBAL_DATA_PTR;
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
 	tick *= CONFIG_SYS_HZ;
-	do_div(tick, CLK_32KHZ);
+	do_div(tick, MXC_CLK32);
 
 	return tick;
 }
 
 static inline unsigned long long us_to_tick(unsigned long long usec)
 {
-	usec = usec * CLK_32KHZ + 999999;
+	usec = usec * MXC_CLK32 + 999999;
 	do_div(usec, 1000000);
 
 	return usec;
@@ -86,7 +86,7 @@ int timer_init(void)
 	__raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
 
 	val = __raw_readl(&cur_gpt->counter);
-	lastinc = val / (CLK_32KHZ / CONFIG_SYS_HZ);
+	lastinc = val / (MXC_CLK32 / CONFIG_SYS_HZ);
 	timestamp = 0;
 
 	return 0;
@@ -114,7 +114,7 @@ ulong get_timer_masked(void)
 {
 	/*
 	 * get_ticks() returns a long long (64 bit), it wraps in
-	 * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+	 * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
 	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
 	 * 5 * 10^6 days - long enough.
 	 */
@@ -145,5 +145,5 @@ void __udelay(unsigned long usec)
  */
 ulong get_tbclk(void)
 {
-	return CLK_32KHZ;
+	return MXC_CLK32;
 }
diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/clock.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/clock.h
index 8d8fa18..55e3b51 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/clock.h
+++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/clock.h
@@ -24,6 +24,20 @@
 #ifndef __ASM_ARCH_CLOCK_H
 #define __ASM_ARCH_CLOCK_H
 
+#include <common.h>
+
+#ifdef CONFIG_SYS_MX5_HCLK
+#define MXC_HCLK	CONFIG_SYS_MX5_HCLK
+#else
+#define MXC_HCLK	24000000
+#endif
+
+#ifdef CONFIG_SYS_MX5_CLK32
+#define MXC_CLK32	CONFIG_SYS_MX5_CLK32
+#else
+#define MXC_CLK32	32768
+#endif
+
 enum mxc_clock {
 	MXC_ARM_CLK = 0,
 	MXC_AHB_CLK,
diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx6/clock.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx6/clock.h
index c55c18d..44b2359 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx6/clock.h
+++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx6/clock.h
@@ -24,6 +24,20 @@
 #ifndef __ASM_ARCH_CLOCK_H
 #define __ASM_ARCH_CLOCK_H
 
+#include <common.h>
+
+#ifdef CONFIG_SYS_MX6_HCLK
+#define MXC_HCLK	CONFIG_SYS_MX6_HCLK
+#else
+#define MXC_HCLK	24000000
+#endif
+
+#ifdef CONFIG_SYS_MX6_CLK32
+#define MXC_CLK32	CONFIG_SYS_MX6_CLK32
+#else
+#define MXC_CLK32	32768
+#endif
+
 enum mxc_clock {
 	MXC_ARM_CLK = 0,
 	MXC_PER_CLK,
diff --git u-boot-imx-e1eb75b.orig/board/freescale/mx53loco/mx53loco.c u-boot-imx-e1eb75b/board/freescale/mx53loco/mx53loco.c
index 8f82125..6543209 100644
--- u-boot-imx-e1eb75b.orig/board/freescale/mx53loco/mx53loco.c
+++ u-boot-imx-e1eb75b/board/freescale/mx53loco/mx53loco.c
@@ -394,7 +394,7 @@ static int power_init(void)
 static void clock_1GHz(void)
 {
 	int ret;
-	u32 ref_clk = CONFIG_SYS_MX5_HCLK;
+	u32 ref_clk = MXC_HCLK;
 	/*
 	 * After increasing voltage to 1.25V, we can switch
 	 * CPU clock to 1GHz and DDR to 400MHz safely
diff --git u-boot-imx-e1eb75b.orig/include/configs/ima3-mx53.h u-boot-imx-e1eb75b/include/configs/ima3-mx53.h
index dbc59b9..499fb37 100644
--- u-boot-imx-e1eb75b.orig/include/configs/ima3-mx53.h
+++ u-boot-imx-e1eb75b/include/configs/ima3-mx53.h
@@ -28,9 +28,6 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx5x_pins.h>
 
-#define CONFIG_SYS_MX5_HCLK		24000000
-#define CONFIG_SYS_MX5_CLK32		32768
-
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
diff --git u-boot-imx-e1eb75b.orig/include/configs/mx51_efikamx.h u-boot-imx-e1eb75b/include/configs/mx51_efikamx.h
index 439b5f3..ffe771f 100644
--- u-boot-imx-e1eb75b.orig/include/configs/mx51_efikamx.h
+++ u-boot-imx-e1eb75b/include/configs/mx51_efikamx.h
@@ -37,8 +37,6 @@
 
 #include <asm/arch/imx-regs.h>
 
-#define CONFIG_SYS_MX5_HCLK		24000000
-#define CONFIG_SYS_MX5_CLK32		32768
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
diff --git u-boot-imx-e1eb75b.orig/include/configs/mx51evk.h u-boot-imx-e1eb75b/include/configs/mx51evk.h
index 7b027b4..34b0783 100644
--- u-boot-imx-e1eb75b.orig/include/configs/mx51evk.h
+++ u-boot-imx-e1eb75b/include/configs/mx51evk.h
@@ -28,8 +28,6 @@
 
 #define CONFIG_MX51	/* in a mx51 */
 
-#define CONFIG_SYS_MX5_HCLK	24000000
-#define CONFIG_SYS_MX5_CLK32		32768
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
diff --git u-boot-imx-e1eb75b.orig/include/configs/mx53ard.h u-boot-imx-e1eb75b/include/configs/mx53ard.h
index 6ab4cde..fea93b4 100644
--- u-boot-imx-e1eb75b.orig/include/configs/mx53ard.h
+++ u-boot-imx-e1eb75b/include/configs/mx53ard.h
@@ -24,8 +24,6 @@
 
 #define CONFIG_MX53
 
-#define CONFIG_SYS_MX5_HCLK	24000000
-#define CONFIG_SYS_MX5_CLK32		32768
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
diff --git u-boot-imx-e1eb75b.orig/include/configs/mx53evk.h u-boot-imx-e1eb75b/include/configs/mx53evk.h
index b46855f..832050e 100644
--- u-boot-imx-e1eb75b.orig/include/configs/mx53evk.h
+++ u-boot-imx-e1eb75b/include/configs/mx53evk.h
@@ -24,8 +24,6 @@
 
 #define CONFIG_MX53
 
-#define CONFIG_SYS_MX5_HCLK	24000000
-#define CONFIG_SYS_MX5_CLK32		32768
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
diff --git u-boot-imx-e1eb75b.orig/include/configs/mx53loco.h u-boot-imx-e1eb75b/include/configs/mx53loco.h
index 8cbaf08..6a6aaa1 100644
--- u-boot-imx-e1eb75b.orig/include/configs/mx53loco.h
+++ u-boot-imx-e1eb75b/include/configs/mx53loco.h
@@ -25,8 +25,6 @@
 
 #define CONFIG_MX53
 
-#define CONFIG_SYS_MX5_HCLK	24000000
-#define CONFIG_SYS_MX5_CLK32		32768
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_MACH_TYPE	MACH_TYPE_MX53_LOCO
diff --git u-boot-imx-e1eb75b.orig/include/configs/mx53smd.h u-boot-imx-e1eb75b/include/configs/mx53smd.h
index f54d328..ff2a290 100644
--- u-boot-imx-e1eb75b.orig/include/configs/mx53smd.h
+++ u-boot-imx-e1eb75b/include/configs/mx53smd.h
@@ -24,8 +24,6 @@
 
 #define CONFIG_MX53
 
-#define CONFIG_SYS_MX5_HCLK	24000000
-#define CONFIG_SYS_MX5_CLK32		32768
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
diff --git u-boot-imx-e1eb75b.orig/include/configs/mx6qarm2.h u-boot-imx-e1eb75b/include/configs/mx6qarm2.h
index 6c17895..965bea3 100644
--- u-boot-imx-e1eb75b.orig/include/configs/mx6qarm2.h
+++ u-boot-imx-e1eb75b/include/configs/mx6qarm2.h
@@ -23,8 +23,6 @@
 #define __CONFIG_H
 
 #define CONFIG_MX6Q
-#define CONFIG_SYS_MX6_HCLK		24000000
-#define CONFIG_SYS_MX6_CLK32		32768
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
diff --git u-boot-imx-e1eb75b.orig/include/configs/mx6qsabrelite.h u-boot-imx-e1eb75b/include/configs/mx6qsabrelite.h
index 72d0154..e7bf658 100644
--- u-boot-imx-e1eb75b.orig/include/configs/mx6qsabrelite.h
+++ u-boot-imx-e1eb75b/include/configs/mx6qsabrelite.h
@@ -23,8 +23,6 @@
 #define __CONFIG_H
 
 #define CONFIG_MX6Q
-#define CONFIG_SYS_MX6_HCLK	       24000000
-#define CONFIG_SYS_MX6_CLK32	       32768
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
diff --git u-boot-imx-e1eb75b.orig/include/configs/vision2.h u-boot-imx-e1eb75b/include/configs/vision2.h
index fba897c..848df88 100644
--- u-boot-imx-e1eb75b.orig/include/configs/vision2.h
+++ u-boot-imx-e1eb75b/include/configs/vision2.h
@@ -30,8 +30,6 @@
 
 #include <asm/arch/imx-regs.h>
 
-#define CONFIG_SYS_MX5_HCLK	24000000
-#define CONFIG_SYS_MX5_CLK32		32768
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 

[U-Boot] [PATCH v2 02/14] mx5 clocks: Cleanup

[Benoît Thébaudeau]

Clean up the i.MX5 clock driver:
 - Use readl() and writel() instead of their __raw_ counterparts.
 - Use the clr/setbits_le32() family of macros rather than expanding code.
 - Use accessor macros for bit-fields instead of _MASK and _OFFSET.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2:
 - New patch.

 .../arch/arm/cpu/armv7/mx5/clock.c                 |  237 ++++++++------------
 .../arch/arm/include/asm/arch-mx5/crm_regs.h       |   99 +++++++-
 2 files changed, 184 insertions(+), 152 deletions(-)

diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
index 1f95536..5fca775 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
@@ -89,94 +89,65 @@ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 
 void set_usboh3_clk(void)
 {
-	unsigned int reg;
-
-	reg = readl(&mxc_ccm->cscmr1) &
-		 ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
-	reg |= 1 << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
-	writel(reg, &mxc_ccm->cscmr1);
-
-	reg = readl(&mxc_ccm->cscdr1);
-	reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK;
-	reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK;
-	reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET;
-	reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET;
-
-	writel(reg, &mxc_ccm->cscdr1);
+	clrsetbits_le32(&mxc_ccm->cscmr1,
+			MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK,
+			MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1));
+	clrsetbits_le32(&mxc_ccm->cscdr1,
+			MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK |
+			MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK,
+			MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) |
+			MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
 }
 
 void enable_usboh3_clk(unsigned char enable)
 {
-	unsigned int reg;
-
-	reg = readl(&mxc_ccm->CCGR2);
 	if (enable)
-		reg |= 1 << MXC_CCM_CCGR2_CG14_OFFSET;
+		setbits_le32(&mxc_ccm->CCGR2, 1 << MXC_CCM_CCGR2_CG14_OFFSET);
 	else
-		reg &= ~(1 << MXC_CCM_CCGR2_CG14_OFFSET);
-	writel(reg, &mxc_ccm->CCGR2);
+		clrbits_le32(&mxc_ccm->CCGR2, 1 << MXC_CCM_CCGR2_CG14_OFFSET);
 }
 
 #ifdef CONFIG_I2C_MXC
 /* i2c_num can be from 0 - 2 */
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 {
-	u32 reg;
 	u32 mask;
 
 	if (i2c_num > 2)
 		return -EINVAL;
 	mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 9) << 1);
-	reg = __raw_readl(&mxc_ccm->CCGR1);
 	if (enable)
-		reg |= mask;
+		setbits_le32(&mxc_ccm->CCGR1, mask);
 	else
-		reg &= ~mask;
-	__raw_writel(reg, &mxc_ccm->CCGR1);
+		clrbits_le32(&mxc_ccm->CCGR1, mask);
 	return 0;
 }
 #endif
 
 void set_usb_phy1_clk(void)
 {
-	unsigned int reg;
-
-	reg = readl(&mxc_ccm->cscmr1);
-	reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
-	writel(reg, &mxc_ccm->cscmr1);
+	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
 }
 
 void enable_usb_phy1_clk(unsigned char enable)
 {
-	unsigned int reg;
-
-	reg = readl(&mxc_ccm->CCGR4);
 	if (enable)
-		reg |= 1 << MXC_CCM_CCGR4_CG5_OFFSET;
+		setbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG5_OFFSET);
 	else
-		reg &= ~(1 << MXC_CCM_CCGR4_CG5_OFFSET);
-	writel(reg, &mxc_ccm->CCGR4);
+		clrbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG5_OFFSET);
 }
 
 void set_usb_phy2_clk(void)
 {
-	unsigned int reg;
-
-	reg = readl(&mxc_ccm->cscmr1);
-	reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
-	writel(reg, &mxc_ccm->cscmr1);
+	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
 }
 
 void enable_usb_phy2_clk(unsigned char enable)
 {
-	unsigned int reg;
-
-	reg = readl(&mxc_ccm->CCGR4);
 	if (enable)
-		reg |= 1 << MXC_CCM_CCGR4_CG6_OFFSET;
+		setbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG6_OFFSET);
 	else
-		reg &= ~(1 << MXC_CCM_CCGR4_CG6_OFFSET);
-	writel(reg, &mxc_ccm->CCGR4);
+		clrbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG6_OFFSET);
 }
 
 /*
@@ -191,19 +162,19 @@ static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
 	ctrl = readl(&pll->ctrl);
 
 	if (ctrl & MXC_DPLLC_CTL_HFSM) {
-		mfn = __raw_readl(&pll->hfs_mfn);
-		mfd = __raw_readl(&pll->hfs_mfd);
-		op = __raw_readl(&pll->hfs_op);
+		mfn = readl(&pll->hfs_mfn);
+		mfd = readl(&pll->hfs_mfd);
+		op = readl(&pll->hfs_op);
 	} else {
-		mfn = __raw_readl(&pll->mfn);
-		mfd = __raw_readl(&pll->mfd);
-		op = __raw_readl(&pll->op);
+		mfn = readl(&pll->mfn);
+		mfd = readl(&pll->mfd);
+		op = readl(&pll->op);
 	}
 
 	mfd &= MXC_DPLLC_MFD_MFD_MASK;
 	mfn &= MXC_DPLLC_MFN_MFN_MASK;
 	pdf = op & MXC_DPLLC_OP_PDF_MASK;
-	mfi = (op & MXC_DPLLC_OP_MFI_MASK) >> MXC_DPLLC_OP_MFI_OFFSET;
+	mfi = MXC_DPLLC_OP_MFI_RD(op);
 
 	/* 21.2.3 */
 	if (mfi < 5)
@@ -240,8 +211,7 @@ u32 get_mcu_main_clk(void)
 {
 	u32 reg, freq;
 
-	reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
-		MXC_CCM_CACRR_ARM_PODF_OFFSET;
+	reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr));
 	freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
 	return freq / (reg + 1);
 }
@@ -253,12 +223,11 @@ u32 get_periph_clk(void)
 {
 	u32 reg;
 
-	reg = __raw_readl(&mxc_ccm->cbcdr);
+	reg = readl(&mxc_ccm->cbcdr);
 	if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
 		return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
-	reg = __raw_readl(&mxc_ccm->cbcmr);
-	switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
-		MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
+	reg = readl(&mxc_ccm->cbcmr);
+	switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) {
 	case 0:
 		return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
 	case 1:
@@ -278,9 +247,8 @@ static u32 get_ipg_clk(void)
 
 	freq = get_ahb_clk();
 
-	reg = __raw_readl(&mxc_ccm->cbcdr);
-	div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
-			MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
+	reg = readl(&mxc_ccm->cbcdr);
+	div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1;
 
 	return freq / div;
 }
@@ -292,17 +260,13 @@ static u32 get_ipg_per_clk(void)
 {
 	u32 pred1, pred2, podf;
 
-	if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
+	if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
 		return get_ipg_clk();
 	/* Fixme: not handle what about lpm*/
-	podf = __raw_readl(&mxc_ccm->cbcdr);
-	pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
-		MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
-	pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
-		MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
-	podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
-		MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
-
+	podf = readl(&mxc_ccm->cbcdr);
+	pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf);
+	pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf);
+	podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf);
 	return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
 }
 
@@ -313,9 +277,8 @@ static u32 get_uart_clk(void)
 {
 	unsigned int freq, reg, pred, podf;
 
-	reg = __raw_readl(&mxc_ccm->cscmr1);
-	switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
-		MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
+	reg = readl(&mxc_ccm->cscmr1);
+	switch (MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg)) {
 	case 0x0:
 		freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
 		break;
@@ -329,13 +292,9 @@ static u32 get_uart_clk(void)
 		return 66500000;
 	}
 
-	reg = __raw_readl(&mxc_ccm->cscdr1);
-
-	pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
-		MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
-
-	podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
-		MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
+	reg = readl(&mxc_ccm->cscdr1);
+	pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);
+	podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);
 	freq /= (pred + 1) * (podf + 1);
 
 	return freq;
@@ -347,7 +306,7 @@ static u32 get_uart_clk(void)
 static u32 get_lp_apm(void)
 {
 	u32 ret_val = 0;
-	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
+	u32 ccsr = readl(&mxc_ccm->ccsr);
 
 	if (((ccsr >> 9) & 1) == 0)
 		ret_val = MXC_HCLK;
@@ -363,15 +322,12 @@ static u32 get_lp_apm(void)
 static u32 imx_get_cspiclk(void)
 {
 	u32 ret_val = 0, pdf, pre_pdf, clk_sel;
-	u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
-	u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2);
+	u32 cscmr1 = readl(&mxc_ccm->cscmr1);
+	u32 cscdr2 = readl(&mxc_ccm->cscdr2);
 
-	pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
-			>> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
-	pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
-			>> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
-	clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
-			>> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
+	pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
+	pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
+	clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
 
 	switch (clk_sel) {
 	case 0:
@@ -396,28 +352,25 @@ static u32 imx_get_cspiclk(void)
 
 static u32 get_axi_a_clk(void)
 {
-	u32 cbcdr =  __raw_readl(&mxc_ccm->cbcdr);
-	u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_A_PODF_MASK) \
-			>> MXC_CCM_CBCDR_AXI_A_PODF_OFFSET;
+	u32 cbcdr = readl(&mxc_ccm->cbcdr);
+	u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr);
 
 	return  get_periph_clk() / (pdf + 1);
 }
 
 static u32 get_axi_b_clk(void)
 {
-	u32 cbcdr =  __raw_readl(&mxc_ccm->cbcdr);
-	u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_B_PODF_MASK) \
-			>> MXC_CCM_CBCDR_AXI_B_PODF_OFFSET;
+	u32 cbcdr = readl(&mxc_ccm->cbcdr);
+	u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr);
 
 	return  get_periph_clk() / (pdf + 1);
 }
 
 static u32 get_emi_slow_clk(void)
 {
-	u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+	u32 cbcdr = readl(&mxc_ccm->cbcdr);
 	u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
-	u32 pdf = (cbcdr & MXC_CCM_CBCDR_EMI_PODF_MASK) \
-			>> MXC_CCM_CBCDR_EMI_PODF_OFFSET;
+	u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr);
 
 	if (emi_clk_sel)
 		return  get_ahb_clk() / (pdf + 1);
@@ -428,14 +381,12 @@ static u32 get_emi_slow_clk(void)
 static u32 get_ddr_clk(void)
 {
 	u32 ret_val = 0;
-	u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
-	u32 ddr_clk_sel = (cbcmr & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) \
-				>> MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET;
+	u32 cbcmr = readl(&mxc_ccm->cbcmr);
+	u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
 #ifdef CONFIG_MX51
-	u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+	u32 cbcdr = readl(&mxc_ccm->cbcdr);
 	if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
-		u32 ddr_clk_podf = (cbcdr & MXC_CCM_CBCDR_DDR_PODF_MASK) >> \
-					MXC_CCM_CBCDR_DDR_PODF_OFFSET;
+		u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
 
 		ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
 		ret_val /= ddr_clk_podf + 1;
@@ -603,62 +554,62 @@ static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
 
 #define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
 	{	\
-		__raw_writel(0x1232, &pll->ctrl);		\
-		__raw_writel(0x2, &pll->config);		\
-		__raw_writel((((pd) - 1) << 0) | ((fi) << 4),	\
-			&pll->op);				\
-		__raw_writel(fn, &(pll->mfn));			\
-		__raw_writel((fd) - 1, &pll->mfd);		\
-		__raw_writel((((pd) - 1) << 0) | ((fi) << 4),	\
-			&pll->hfs_op);				\
-		__raw_writel(fn, &pll->hfs_mfn);		\
-		__raw_writel((fd) - 1, &pll->hfs_mfd);		\
-		__raw_writel(0x1232, &pll->ctrl);		\
-		while (!__raw_readl(&pll->ctrl) & 0x1)		\
+		writel(0x1232, &pll->ctrl);		\
+		writel(0x2, &pll->config);		\
+		writel((((pd) - 1) << 0) | ((fi) << 4),	\
+			&pll->op);			\
+		writel(fn, &(pll->mfn));		\
+		writel((fd) - 1, &pll->mfd);		\
+		writel((((pd) - 1) << 0) | ((fi) << 4),	\
+			&pll->hfs_op);			\
+		writel(fn, &pll->hfs_mfn);		\
+		writel((fd) - 1, &pll->hfs_mfd);	\
+		writel(0x1232, &pll->ctrl);		\
+		while (!readl(&pll->ctrl) & 0x1)	\
 			;\
 	}
 
 static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
 {
-	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
+	u32 ccsr = readl(&mxc_ccm->ccsr);
 	struct mxc_pll_reg *pll = mxc_plls[index];
 
 	switch (index) {
 	case PLL1_CLOCK:
 		/* Switch ARM to PLL2 clock */
-		__raw_writel(ccsr | 0x4, &mxc_ccm->ccsr);
+		writel(ccsr | 0x4, &mxc_ccm->ccsr);
 		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
 					pll_param->mfi, pll_param->mfn,
 					pll_param->mfd);
 		/* Switch back */
-		__raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr);
+		writel(ccsr & ~0x4, &mxc_ccm->ccsr);
 		break;
 	case PLL2_CLOCK:
 		/* Switch to pll2 bypass clock */
-		__raw_writel(ccsr | 0x2, &mxc_ccm->ccsr);
+		writel(ccsr | 0x2, &mxc_ccm->ccsr);
 		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
 					pll_param->mfi, pll_param->mfn,
 					pll_param->mfd);
 		/* Switch back */
-		__raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr);
+		writel(ccsr & ~0x2, &mxc_ccm->ccsr);
 		break;
 	case PLL3_CLOCK:
 		/* Switch to pll3 bypass clock */
-		__raw_writel(ccsr | 0x1, &mxc_ccm->ccsr);
+		writel(ccsr | 0x1, &mxc_ccm->ccsr);
 		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
 					pll_param->mfi, pll_param->mfn,
 					pll_param->mfd);
 		/* Switch back */
-		__raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr);
+		writel(ccsr & ~0x1, &mxc_ccm->ccsr);
 		break;
 	case PLL4_CLOCK:
 		/* Switch to pll4 bypass clock */
-		__raw_writel(ccsr | 0x20, &mxc_ccm->ccsr);
+		writel(ccsr | 0x20, &mxc_ccm->ccsr);
 		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
 					pll_param->mfi, pll_param->mfn,
 					pll_param->mfd);
 		/* Switch back */
-		__raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr);
+		writel(ccsr & ~0x20, &mxc_ccm->ccsr);
 		break;
 	default:
 		return -EINVAL;
@@ -687,7 +638,6 @@ static int config_core_clk(u32 ref, u32 freq)
 
 static int config_nfc_clk(u32 nfc_clk)
 {
-	u32 reg;
 	u32 parent_rate = get_emi_slow_clk();
 	u32 div = parent_rate / nfc_clk;
 
@@ -697,11 +647,10 @@ static int config_nfc_clk(u32 nfc_clk)
 		div++;
 	if (parent_rate / div > NFC_CLK_MAX)
 		div++;
-	reg = __raw_readl(&mxc_ccm->cbcdr);
-	reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
-	reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
-	__raw_writel(reg, &mxc_ccm->cbcdr);
-	while (__raw_readl(&mxc_ccm->cdhipr) != 0)
+	clrsetbits_le32(&mxc_ccm->cbcdr,
+			MXC_CCM_CBCDR_NFC_PODF_MASK,
+			MXC_CCM_CBCDR_NFC_PODF(div - 1));
+	while (readl(&mxc_ccm->cdhipr) != 0)
 		;
 	return 0;
 }
@@ -714,16 +663,15 @@ static int config_periph_clk(u32 ref, u32 freq)
 
 	memset(&pll_param, 0, sizeof(struct pll_param));
 
-	if (__raw_readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
+	if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
 		ret = calc_pll_params(ref, freq, &pll_param);
 		if (ret != 0) {
 			printf("Error:Can't find pll parameters: %d\n",
 				ret);
 			return ret;
 		}
-		switch ((__raw_readl(&mxc_ccm->cbcmr) & \
-			MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> \
-			MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
+		switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(
+				readl(&mxc_ccm->cbcmr))) {
 		case 0:
 			return config_pll_clk(PLL1_CLOCK, &pll_param);
 			break;
@@ -742,8 +690,7 @@ static int config_ddr_clk(u32 emi_clk)
 {
 	u32 clk_src;
 	s32 shift = 0, clk_sel, div = 1;
-	u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
-	u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+	u32 cbcmr = readl(&mxc_ccm->cbcmr);
 
 	if (emi_clk > MAX_DDR_CLK) {
 		printf("Warning:DDR clock should not exceed %d MHz\n",
@@ -753,7 +700,7 @@ static int config_ddr_clk(u32 emi_clk)
 
 	clk_src = get_periph_clk();
 	/* Find DDR clock input */
-	clk_sel = (cbcmr >> 10) & 0x3;
+	clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
 	switch (clk_sel) {
 	case 0:
 		shift = 16;
@@ -778,12 +725,10 @@ static int config_ddr_clk(u32 emi_clk)
 	if (div > 8)
 		div = 8;
 
-	cbcdr = cbcdr & ~(0x7 << shift);
-	cbcdr |= ((div - 1) << shift);
-	__raw_writel(cbcdr, &mxc_ccm->cbcdr);
-	while (__raw_readl(&mxc_ccm->cdhipr) != 0)
+	clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift);
+	while (readl(&mxc_ccm->cdhipr) != 0)
 		;
-	__raw_writel(0x0, &mxc_ccm->ccdr);
+	writel(0x0, &mxc_ccm->ccdr);
 
 	return 0;
 }
@@ -856,7 +801,7 @@ void mxc_set_sata_internal_clock(void)
 
 	set_usb_phy1_clk();
 
-	writel((readl(tmp_base) & (~0x6)) | 0x4, tmp_base);
+	clrsetbits_le32(tmp_base, 0x6, 0x4);
 }
 #endif
 
diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/crm_regs.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/crm_regs.h
index 4e0fc1b..ab0e818 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -85,115 +85,200 @@ struct mxc_ccm_reg {
 /* Define the bits in register CACRR */
 #define MXC_CCM_CACRR_ARM_PODF_OFFSET		0
 #define MXC_CCM_CACRR_ARM_PODF_MASK		0x7
+#define MXC_CCM_CACRR_ARM_PODF(v)		((v) & 0x7)
+#define MXC_CCM_CACRR_ARM_PODF_RD(r)		((r) & 0x7)
 
 /* Define the bits in register CBCDR */
 #define MXC_CCM_CBCDR_DDR_HIFREQ_SEL		(0x1 << 30)
-#define MXC_CCM_CBCDR_DDR_PODF_MASK		(0x7 << 27)
 #define MXC_CCM_CBCDR_DDR_PODF_OFFSET		27
+#define MXC_CCM_CBCDR_DDR_PODF_MASK		(0x7 << 27)
+#define MXC_CCM_CBCDR_DDR_PODF(v)		(((v) & 0x7) << 27)
+#define MXC_CCM_CBCDR_DDR_PODF_RD(r)		(((r) >> 27) & 0x7)
 #define MXC_CCM_CBCDR_EMI_CLK_SEL		(0x1 << 26)
 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL		(0x1 << 25)
 #define MXC_CCM_CBCDR_EMI_PODF_OFFSET		22
 #define MXC_CCM_CBCDR_EMI_PODF_MASK		(0x7 << 22)
+#define MXC_CCM_CBCDR_EMI_PODF(v)		(((v) & 0x7) << 22)
+#define MXC_CCM_CBCDR_EMI_PODF_RD(r)		(((r) >> 22) & 0x7)
 #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET		19
 #define MXC_CCM_CBCDR_AXI_B_PODF_MASK		(0x7 << 19)
+#define MXC_CCM_CBCDR_AXI_B_PODF(v)		(((v) & 0x7) << 19)
+#define MXC_CCM_CBCDR_AXI_B_PODF_RD(r)		(((r) >> 19) & 0x7)
 #define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET		16
 #define MXC_CCM_CBCDR_AXI_A_PODF_MASK		(0x7 << 16)
+#define MXC_CCM_CBCDR_AXI_A_PODF(v)		(((v) & 0x7) << 16)
+#define MXC_CCM_CBCDR_AXI_A_PODF_RD(r)		(((r) >> 16) & 0x7)
 #define MXC_CCM_CBCDR_NFC_PODF_OFFSET		13
 #define MXC_CCM_CBCDR_NFC_PODF_MASK		(0x7 << 13)
+#define MXC_CCM_CBCDR_NFC_PODF(v)		(((v) & 0x7) << 13)
+#define MXC_CCM_CBCDR_NFC_PODF_RD(r)		(((r) >> 13) & 0x7)
 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET		10
 #define MXC_CCM_CBCDR_AHB_PODF_MASK		(0x7 << 10)
+#define MXC_CCM_CBCDR_AHB_PODF(v)		(((v) & 0x7) << 10)
+#define MXC_CCM_CBCDR_AHB_PODF_RD(r)		(((r) >> 10) & 0x7)
 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET		8
 #define MXC_CCM_CBCDR_IPG_PODF_MASK		(0x3 << 8)
+#define MXC_CCM_CBCDR_IPG_PODF(v)		(((v) & 0x3) << 8)
+#define MXC_CCM_CBCDR_IPG_PODF_RD(r)		(((r) >> 8) & 0x3)
 #define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET	6
 #define MXC_CCM_CBCDR_PERCLK_PRED1_MASK		(0x3 << 6)
+#define MXC_CCM_CBCDR_PERCLK_PRED1(v)		(((v) & 0x3) << 6)
+#define MXC_CCM_CBCDR_PERCLK_PRED1_RD(r)	(((r) >> 6) & 0x3)
 #define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET	3
 #define MXC_CCM_CBCDR_PERCLK_PRED2_MASK		(0x7 << 3)
+#define MXC_CCM_CBCDR_PERCLK_PRED2(v)		(((v) & 0x7) << 3)
+#define MXC_CCM_CBCDR_PERCLK_PRED2_RD(r)	(((r) >> 3) & 0x7)
 #define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET	0
 #define MXC_CCM_CBCDR_PERCLK_PODF_MASK		0x7
+#define MXC_CCM_CBCDR_PERCLK_PODF(v)		((v) & 0x7)
+#define MXC_CCM_CBCDR_PERCLK_PODF_RD(r)		((r) & 0x7)
 
 /* Define the bits in register CSCMR1 */
 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET		30
 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK		(0x3 << 30)
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL(v)		(((v) & 0x3) << 30)
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_RD(r)		(((r) >> 30) & 0x3)
 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET		28
 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK		(0x3 << 28)
-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET		26
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL(v)		(((v) & 0x3) << 28)
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_RD(r)		(((r) >> 28) & 0x3)
 #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL			(0x1 << 26)
 #define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET		24
 #define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK		(0x3 << 24)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL(v)			(((v) & 0x3) << 24)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_RD(r)		(((r) >> 24) & 0x3)
 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET		22
 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK		(0x3 << 22)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL(v)		(((v) & 0x3) << 22)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_RD(r)		(((r) >> 22) & 0x3)
 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET	20
 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK	(0x3 << 20)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL(v)		(((v) & 0x3) << 20)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(r)	(((r) >> 20) & 0x3)
 #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL			(0x1 << 19)
 #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL			(0x1 << 18)
 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET	16
 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK	(0x3 << 16)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL(v)		(((v) & 0x3) << 16)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(r)	(((r) >> 16) & 0x3)
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET		14
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_RD(r)		(((r) >> 14) & 0x3)
 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET		12
 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK		(0x3 << 12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_RD(r)		(((r) >> 12) & 0x3)
 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL			(0x1 << 11)
 #define MXC_CCM_CSCMR1_VPU_RCLK_SEL			(0x1 << 10)
 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET		8
 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK		(0x3 << 8)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL(v)		(((v) & 0x3) << 8)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_RD(r)		(((r) >> 8) & 0x3)
 #define MXC_CCM_CSCMR1_TVE_CLK_SEL			(0x1 << 7)
 #define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL			(0x1 << 6)
 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET		4
 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK		(0x3 << 4)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL(v)			(((v) & 0x3) << 4)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(r)		(((r) >> 4) & 0x3)
 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET		2
 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK		(0x3 << 2)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL(v)			(((v) & 0x3) << 2)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_RD(r)		(((r) >> 2) & 0x3)
 #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL		(0x1 << 1)
 #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL		0x1
 
 /* Define the bits in register CSCDR2 */
 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET		25
 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK		(0x7 << 25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED(v)			(((v) & 0x7) << 25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(r)		(((r) >> 25) & 0x7)
 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET		19
 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK		(0x3F << 19)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF(v)			(((v) & 0x3F) << 19)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(r)		(((r) >> 19) & 0x3F)
 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET		16
 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK		(0x7 << 16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED(v)			(((v) & 0x7) << 16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_RD(r)		(((r) >> 16) & 0x7)
 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET		9
 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK		(0x3F << 9)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF(v)			(((v) & 0x3F) << 9)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_RD(r)		(((r) >> 9) & 0x3F)
 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET		6
-#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK		(0x7 << 6)
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET		0
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK		0x3F
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_MASK		(0x7 << 6)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED(v)		(((v) & 0x7) << 6)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_RD(r)		(((r) >> 6) & 0x7)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_OFFSET		0
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_MASK		0x3F
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF(v)		((v) & 0x3F)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_RD(r)		((r) & 0x3F)
 
 /* Define the bits in register CBCMR */
 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET		14
 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL(v)		(((v) & 0x3) << 14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_RD(r)		(((r) >> 14) & 0x3)
 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET		12
 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK		(0x3 << 12)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(r)		(((r) >> 12) & 0x3)
 #define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET		10
 #define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK			(0x3 << 10)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_RD(r)			(((r) >> 10) & 0x3)
 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET		8
 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK		(0x3 << 8)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL(v)		(((v) & 0x3) << 8)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_RD(r)		(((r) >> 8) & 0x3)
 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET		6
 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK		(0x3 << 6)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(v)		(((v) & 0x3) << 6)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_RD(r)		(((r) >> 6) & 0x3)
 #define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET		4
 #define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK			(0x3 << 4)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL(v)			(((v) & 0x3) << 4)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_RD(r)			(((r) >> 4) & 0x3)
 #define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL		(0x1 << 1)
 #define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL		(0x1 << 0)
 
 /* Define the bits in register CSCDR1 */
 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET	22
 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK	(0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED(v)		(((v) & 0x7) << 22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(r)	(((r) >> 22) & 0x7)
 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET	19
 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK	(0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF(v)		(((v) & 0x7) << 19)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(r)	(((r) >> 19) & 0x7)
 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET	16
 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK	(0x7 << 16)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED(v)		(((v) & 0x7) << 16)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(r)	(((r) >> 16) & 0x7)
 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET		14
 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK		(0x3 << 14)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_RD(r)		(((r) >> 14) & 0x3)
 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET	11
 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK	(0x7 << 11)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF(v)		(((v) & 0x7) << 11)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(r)	(((r) >> 11) & 0x7)
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET		8
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK		(0x7 << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED(v)		(((v) & 0x7) << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_RD(r)		(((r) >> 8) & 0x7)
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		6
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF(v)		(((v) & 0x3) << 6)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_RD(r)		(((r) >> 6) & 0x3)
 #define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET		3
 #define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK		(0x7 << 3)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED(v)			(((v) & 0x7) << 3)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_RD(r)		(((r) >> 3) & 0x7)
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		0
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x7
+#define MXC_CCM_CSCDR1_UART_CLK_PODF(v)			((v) & 0x7)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r)		((r) & 0x7)
 
 /* Define the bits in register CCDR */
 #define MXC_CCM_CCDR_IPU_HS_MASK			(0x1 << 17)
@@ -213,8 +298,10 @@ struct mxc_ccm_reg {
 #define	MXC_DPLLC_CTL_DPDCK0_2_EN			(1 << 12)
 
 #define	MXC_DPLLC_OP_PDF_MASK				0xf
-#define	MXC_DPLLC_OP_MFI_MASK				(0xf << 4)
 #define	MXC_DPLLC_OP_MFI_OFFSET				4
+#define	MXC_DPLLC_OP_MFI_MASK				(0xf << 4)
+#define	MXC_DPLLC_OP_MFI(v)				(((v) & 0xf) << 4)
+#define	MXC_DPLLC_OP_MFI_RD(r)				(((r) >> 4) & 0xf)
 
 #define	MXC_DPLLC_MFD_MFD_MASK				0x7ffffff
 

[U-Boot] [PATCH v2 03/14] mx5: Use explicit clock gate names

[Benoît Thébaudeau]

Use clock gate definitions having names showing clearly the gated clock instead
of names giving only a register field index.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
This change reveals (clock.c won't build) that the USB PHY clock functions were
broken on i.MX51, which is fixed by the following 2 patches.

This patch supersedes http://patchwork.ozlabs.org/patch/177403/ .
Changes for v2:
 - Split patch into 3 parts (the 3, 4 and 5 from this v2 series).
 - Use the created definitions for enable_i2c_clk().

 .../arch/arm/cpu/armv7/mx5/clock.c                 |   15 +-
 .../arch/arm/include/asm/arch-mx5/crm_regs.h       |  279 +++++++++++++++++++-
 .../drivers/video/ipu_common.c                     |    2 +-
 3 files changed, 284 insertions(+), 12 deletions(-)

diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
index 5fca775..32a69d4 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
@@ -102,9 +102,9 @@ void set_usboh3_clk(void)
 void enable_usboh3_clk(unsigned char enable)
 {
 	if (enable)
-		setbits_le32(&mxc_ccm->CCGR2, 1 << MXC_CCM_CCGR2_CG14_OFFSET);
+		setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_USBOH3_60M(1));
 	else
-		clrbits_le32(&mxc_ccm->CCGR2, 1 << MXC_CCM_CCGR2_CG14_OFFSET);
+		clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_USBOH3_60M(1));
 }
 
 #ifdef CONFIG_I2C_MXC
@@ -115,7 +115,8 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 
 	if (i2c_num > 2)
 		return -EINVAL;
-	mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 9) << 1);
+	mask = MXC_CCM_CCGR_CG_MASK <<
+			(MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));
 	if (enable)
 		setbits_le32(&mxc_ccm->CCGR1, mask);
 	else
@@ -132,9 +133,9 @@ void set_usb_phy1_clk(void)
 void enable_usb_phy1_clk(unsigned char enable)
 {
 	if (enable)
-		setbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG5_OFFSET);
+		setbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY1(1));
 	else
-		clrbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG5_OFFSET);
+		clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY1(1));
 }
 
 void set_usb_phy2_clk(void)
@@ -145,9 +146,9 @@ void set_usb_phy2_clk(void)
 void enable_usb_phy2_clk(unsigned char enable)
 {
 	if (enable)
-		setbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG6_OFFSET);
+		setbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY2(1));
 	else
-		clrbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG6_OFFSET);
+		clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY2(1));
 }
 
 /*
diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/crm_regs.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/crm_regs.h
index ab0e818..d5eb303 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -286,10 +286,281 @@ struct mxc_ccm_reg {
 /* Define the bits in register CCGRx */
 #define MXC_CCM_CCGR_CG_MASK				0x3
 
-#define MXC_CCM_CCGR4_CG5_OFFSET			10
-#define MXC_CCM_CCGR4_CG6_OFFSET			12
-#define MXC_CCM_CCGR5_CG5_OFFSET			10
-#define MXC_CCM_CCGR2_CG14_OFFSET			28
+#define MXC_CCM_CCGR0_ARM_BUS_OFFSET			0
+#define MXC_CCM_CCGR0_ARM_BUS(v)			(((v) & 0x3) << 0)
+#define MXC_CCM_CCGR0_ARM_AXI_OFFSET			2
+#define MXC_CCM_CCGR0_ARM_AXI(v)			(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR0_ARM_DEBUG_OFFSET			4
+#define MXC_CCM_CCGR0_ARM_DEBUG(v)			(((v) & 0x3) << 4)
+#define MXC_CCM_CCGR0_TZIC_OFFSET			6
+#define MXC_CCM_CCGR0_TZIC(v)				(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR0_DAP_OFFSET			8
+#define MXC_CCM_CCGR0_DAP(v)				(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR0_TPIU_OFFSET			10
+#define MXC_CCM_CCGR0_TPIU(v)				(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR0_CTI2_OFFSET			12
+#define MXC_CCM_CCGR0_CTI2(v)				(((v) & 0x3) << 12)
+#define MXC_CCM_CCGR0_CTI3_OFFSET			14
+#define MXC_CCM_CCGR0_CTI3(v)				(((v) & 0x3) << 14)
+#define MXC_CCM_CCGR0_AHBMUX1_OFFSET			16
+#define MXC_CCM_CCGR0_AHBMUX1(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR0_AHBMUX2_OFFSET			18
+#define MXC_CCM_CCGR0_AHBMUX2(v)			(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR0_ROMCP_OFFSET			20
+#define MXC_CCM_CCGR0_ROMCP(v)				(((v) & 0x3) << 20)
+#define MXC_CCM_CCGR0_ROM_OFFSET			22
+#define MXC_CCM_CCGR0_ROM(v)				(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET			24
+#define MXC_CCM_CCGR0_AIPS_TZ1(v)			(((v) & 0x3) << 24)
+#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET			26
+#define MXC_CCM_CCGR0_AIPS_TZ2(v)			(((v) & 0x3) << 26)
+#define MXC_CCM_CCGR0_AHB_MAX_OFFSET			28
+#define MXC_CCM_CCGR0_AHB_MAX(v)			(((v) & 0x3) << 28)
+#define MXC_CCM_CCGR0_IIM_OFFSET			30
+#define MXC_CCM_CCGR0_IIM(v)				(((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR1_TMAX1_OFFSET			0
+#define MXC_CCM_CCGR1_TMAX1(v)				(((v) & 0x3) << 0)
+#define MXC_CCM_CCGR1_TMAX2_OFFSET			2
+#define MXC_CCM_CCGR1_TMAX2(v)				(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR1_TMAX3_OFFSET			4
+#define MXC_CCM_CCGR1_TMAX3(v)				(((v) & 0x3) << 4)
+#define MXC_CCM_CCGR1_UART1_IPG_OFFSET			6
+#define MXC_CCM_CCGR1_UART1_IPG(v)			(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR1_UART1_PER_OFFSET			8
+#define MXC_CCM_CCGR1_UART1_PER(v)			(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR1_UART2_IPG_OFFSET			10
+#define MXC_CCM_CCGR1_UART2_IPG(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR1_UART2_PER_OFFSET			12
+#define MXC_CCM_CCGR1_UART2_PER(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CCGR1_UART3_IPG_OFFSET			14
+#define MXC_CCM_CCGR1_UART3_IPG(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CCGR1_UART3_PER_OFFSET			16
+#define MXC_CCM_CCGR1_UART3_PER(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR1_I2C1_OFFSET			18
+#define MXC_CCM_CCGR1_I2C1(v)				(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR1_I2C2_OFFSET			20
+#define MXC_CCM_CCGR1_I2C2(v)				(((v) & 0x3) << 20)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET			22
+#define MXC_CCM_CCGR1_HSI2C_IPG(v)			(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR1_HSI2C_SERIAL_OFFSET		24
+#define MXC_CCM_CCGR1_HSI2C_SERIAL(v)			(((v) & 0x3) << 24)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR1_I2C3_OFFSET			22
+#define MXC_CCM_CCGR1_I2C3(v)				(((v) & 0x3) << 22)
+#endif
+#define MXC_CCM_CCGR1_FIRI_IPG_OFFSET			26
+#define MXC_CCM_CCGR1_FIRI_IPG(v)			(((v) & 0x3) << 26)
+#define MXC_CCM_CCGR1_FIRI_SERIAL_OFFSET		28
+#define MXC_CCM_CCGR1_FIRI_SERIAL(v)			(((v) & 0x3) << 28)
+#define MXC_CCM_CCGR1_SCC_OFFSET			30
+#define MXC_CCM_CCGR1_SCC(v)				(((v) & 0x3) << 30)
+
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR2_USB_PHY_OFFSET			0
+#define MXC_CCM_CCGR2_USB_PHY(v)			(((v) & 0x3) << 0)
+#endif
+#define MXC_CCM_CCGR2_EPIT1_IPG_OFFSET			2
+#define MXC_CCM_CCGR2_EPIT1_IPG(v)			(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR2_EPIT1_HF_OFFSET			4
+#define MXC_CCM_CCGR2_EPIT1_HF(v)			(((v) & 0x3) << 4)
+#define MXC_CCM_CCGR2_EPIT2_IPG_OFFSET			6
+#define MXC_CCM_CCGR2_EPIT2_IPG(v)			(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR2_EPIT2_HF_OFFSET			8
+#define MXC_CCM_CCGR2_EPIT2_HF(v)			(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR2_PWM1_IPG_OFFSET			10
+#define MXC_CCM_CCGR2_PWM1_IPG(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR2_PWM1_HF_OFFSET			12
+#define MXC_CCM_CCGR2_PWM1_HF(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CCGR2_PWM2_IPG_OFFSET			14
+#define MXC_CCM_CCGR2_PWM2_IPG(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CCGR2_PWM2_HF_OFFSET			16
+#define MXC_CCM_CCGR2_PWM2_HF(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR2_GPT_IPG_OFFSET			18
+#define MXC_CCM_CCGR2_GPT_IPG(v)			(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR2_GPT_HF_OFFSET			20
+#define MXC_CCM_CCGR2_GPT_HF(v)				(((v) & 0x3) << 20)
+#define MXC_CCM_CCGR2_OWIRE_OFFSET			22
+#define MXC_CCM_CCGR2_OWIRE(v)				(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR2_FEC_OFFSET			24
+#define MXC_CCM_CCGR2_FEC(v)				(((v) & 0x3) << 24)
+#define MXC_CCM_CCGR2_USBOH3_IPG_AHB_OFFSET		26
+#define MXC_CCM_CCGR2_USBOH3_IPG_AHB(v)			(((v) & 0x3) << 26)
+#define MXC_CCM_CCGR2_USBOH3_60M_OFFSET			28
+#define MXC_CCM_CCGR2_USBOH3_60M(v)			(((v) & 0x3) << 28)
+#define MXC_CCM_CCGR2_TVE_OFFSET			30
+#define MXC_CCM_CCGR2_TVE(v)				(((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR3_ESDHC1_IPG_OFFSET			0
+#define MXC_CCM_CCGR3_ESDHC1_IPG(v)			(((v) & 0x3) << 0)
+#define MXC_CCM_CCGR3_ESDHC1_PER_OFFSET			2
+#define MXC_CCM_CCGR3_ESDHC1_PER(v)			(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR3_ESDHC2_IPG_OFFSET			4
+#define MXC_CCM_CCGR3_ESDHC2_IPG(v)			(((v) & 0x3) << 4)
+#define MXC_CCM_CCGR3_ESDHC2_PER_OFFSET			6
+#define MXC_CCM_CCGR3_ESDHC2_PER(v)			(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR3_ESDHC3_IPG_OFFSET			8
+#define MXC_CCM_CCGR3_ESDHC3_IPG(v)			(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR3_ESDHC3_PER_OFFSET			10
+#define MXC_CCM_CCGR3_ESDHC3_PER(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR3_ESDHC4_IPG_OFFSET			12
+#define MXC_CCM_CCGR3_ESDHC4_IPG(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CCGR3_ESDHC4_PER_OFFSET			14
+#define MXC_CCM_CCGR3_ESDHC4_PER(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CCGR3_SSI1_IPG_OFFSET			16
+#define MXC_CCM_CCGR3_SSI1_IPG(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR3_SSI1_SSI_OFFSET			18
+#define MXC_CCM_CCGR3_SSI1_SSI(v)			(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR3_SSI2_IPG_OFFSET			20
+#define MXC_CCM_CCGR3_SSI2_IPG(v)			(((v) & 0x3) << 20)
+#define MXC_CCM_CCGR3_SSI2_SSI_OFFSET			22
+#define MXC_CCM_CCGR3_SSI2_SSI(v)			(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR3_SSI3_IPG_OFFSET			24
+#define MXC_CCM_CCGR3_SSI3_IPG(v)			(((v) & 0x3) << 24)
+#define MXC_CCM_CCGR3_SSI3_SSI_OFFSET			26
+#define MXC_CCM_CCGR3_SSI3_SSI(v)			(((v) & 0x3) << 26)
+#define MXC_CCM_CCGR3_SSI_EXT1_OFFSET			28
+#define MXC_CCM_CCGR3_SSI_EXT1(v)			(((v) & 0x3) << 28)
+#define MXC_CCM_CCGR3_SSI_EXT2_OFFSET			30
+#define MXC_CCM_CCGR3_SSI_EXT2(v)			(((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR4_PATA_OFFSET			0
+#define MXC_CCM_CCGR4_PATA(v)				(((v) & 0x3) << 0)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR4_SIM_IPG_OFFSET			2
+#define MXC_CCM_CCGR4_SIM_IPG(v)			(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR4_SIM_SERIAL_OFFSET			4
+#define MXC_CCM_CCGR4_SIM_SERIAL(v)			(((v) & 0x3) << 4)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR4_SATA_OFFSET			2
+#define MXC_CCM_CCGR4_SATA(v)				(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR4_CAN2_IPG_OFFSET			6
+#define MXC_CCM_CCGR4_CAN2_IPG(v)			(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR4_CAN2_SERIAL_OFFSET		8
+#define MXC_CCM_CCGR4_CAN2_SERIAL(v)			(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR4_USB_PHY1_OFFSET			10
+#define MXC_CCM_CCGR4_USB_PHY1(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR4_USB_PHY2_OFFSET			12
+#define MXC_CCM_CCGR4_USB_PHY2(v)			(((v) & 0x3) << 12)
+#endif
+#define MXC_CCM_CCGR4_SAHARA_OFFSET			14
+#define MXC_CCM_CCGR4_SAHARA(v)				(((v) & 0x3) << 14)
+#define MXC_CCM_CCGR4_RTIC_OFFSET			16
+#define MXC_CCM_CCGR4_RTIC(v)				(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR4_ECSPI1_IPG_OFFSET			18
+#define MXC_CCM_CCGR4_ECSPI1_IPG(v)			(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR4_ECSPI1_PER_OFFSET			20
+#define MXC_CCM_CCGR4_ECSPI1_PER(v)			(((v) & 0x3) << 20)
+#define MXC_CCM_CCGR4_ECSPI2_IPG_OFFSET			22
+#define MXC_CCM_CCGR4_ECSPI2_IPG(v)			(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR4_ECSPI2_PER_OFFSET			24
+#define MXC_CCM_CCGR4_ECSPI2_PER(v)			(((v) & 0x3) << 24)
+#define MXC_CCM_CCGR4_CSPI_IPG_OFFSET			26
+#define MXC_CCM_CCGR4_CSPI_IPG(v)			(((v) & 0x3) << 26)
+#define MXC_CCM_CCGR4_SRTC_OFFSET			28
+#define MXC_CCM_CCGR4_SRTC(v)				(((v) & 0x3) << 28)
+#define MXC_CCM_CCGR4_SDMA_OFFSET			30
+#define MXC_CCM_CCGR4_SDMA(v)				(((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR5_SPBA_OFFSET			0
+#define MXC_CCM_CCGR5_SPBA(v)				(((v) & 0x3) << 0)
+#define MXC_CCM_CCGR5_GPU_OFFSET			2
+#define MXC_CCM_CCGR5_GPU(v)				(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR5_GARB_OFFSET			4
+#define MXC_CCM_CCGR5_GARB(v)				(((v) & 0x3) << 4)
+#define MXC_CCM_CCGR5_VPU_OFFSET			6
+#define MXC_CCM_CCGR5_VPU(v)				(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR5_VPU_REF_OFFSET			8
+#define MXC_CCM_CCGR5_VPU_REF(v)			(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR5_IPU_OFFSET			10
+#define MXC_CCM_CCGR5_IPU(v)				(((v) & 0x3) << 10)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR5_IPUMUX12_OFFSET			12
+#define MXC_CCM_CCGR5_IPUMUX12(v)			(((v) & 0x3) << 12)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR5_IPUMUX1_OFFSET			12
+#define MXC_CCM_CCGR5_IPUMUX1(v)			(((v) & 0x3) << 12)
+#endif
+#define MXC_CCM_CCGR5_EMI_FAST_OFFSET			14
+#define MXC_CCM_CCGR5_EMI_FAST(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CCGR5_EMI_SLOW_OFFSET			16
+#define MXC_CCM_CCGR5_EMI_SLOW(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR5_EMI_INT1_OFFSET			18
+#define MXC_CCM_CCGR5_EMI_INT1(v)			(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR5_EMI_ENFC_OFFSET			20
+#define MXC_CCM_CCGR5_EMI_ENFC(v)			(((v) & 0x3) << 20)
+#define MXC_CCM_CCGR5_EMI_WRCK_OFFSET			22
+#define MXC_CCM_CCGR5_EMI_WRCK(v)			(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR5_GPC_IPG_OFFSET			24
+#define MXC_CCM_CCGR5_GPC_IPG(v)			(((v) & 0x3) << 24)
+#define MXC_CCM_CCGR5_SPDIF0_OFFSET			26
+#define MXC_CCM_CCGR5_SPDIF0(v)				(((v) & 0x3) << 26)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR5_SPDIF1_OFFSET			28
+#define MXC_CCM_CCGR5_SPDIF1(v)				(((v) & 0x3) << 28)
+#endif
+#define MXC_CCM_CCGR5_SPDIF_IPG_OFFSET			30
+#define MXC_CCM_CCGR5_SPDIF_IPG(v)			(((v) & 0x3) << 30)
+
+#if defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_IPUMUX2_OFFSET			0
+#define MXC_CCM_CCGR6_IPUMUX2(v)			(((v) & 0x3) << 0)
+#define MXC_CCM_CCGR6_OCRAM_OFFSET			2
+#define MXC_CCM_CCGR6_OCRAM(v)				(((v) & 0x3) << 2)
+#endif
+#define MXC_CCM_CCGR6_CSI_MCLK1_OFFSET			4
+#define MXC_CCM_CCGR6_CSI_MCLK1(v)			(((v) & 0x3) << 4)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR6_CSI_MCLK2_OFFSET			6
+#define MXC_CCM_CCGR6_CSI_MCLK2(v)			(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR6_EMI_GARB_OFFSET			8
+#define MXC_CCM_CCGR6_EMI_GARB(v)			(((v) & 0x3) << 8)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_EMI_INT2_OFFSET			8
+#define MXC_CCM_CCGR6_EMI_INT2(v)			(((v) & 0x3) << 8)
+#endif
+#define MXC_CCM_CCGR6_IPU_DI0_OFFSET			10
+#define MXC_CCM_CCGR6_IPU_DI0(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR6_IPU_DI1_OFFSET			12
+#define MXC_CCM_CCGR6_IPU_DI1(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CCGR6_GPU2D_OFFSET			14
+#define MXC_CCM_CCGR6_GPU2D(v)				(((v) & 0x3) << 14)
+#if defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_ESAI_IPG_OFFSET			16
+#define MXC_CCM_CCGR6_ESAI_IPG(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR6_ESAI_ROOT_OFFSET			18
+#define MXC_CCM_CCGR6_ESAI_ROOT(v)			(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR6_CAN1_IPG_OFFSET			20
+#define MXC_CCM_CCGR6_CAN1_IPG(v)			(((v) & 0x3) << 20)
+#define MXC_CCM_CCGR6_CAN1_SERIAL_OFFSET		22
+#define MXC_CCM_CCGR6_CAN1_SERIAL(v)			(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR6_PL301_4X1_OFFSET			24
+#define MXC_CCM_CCGR6_PL301_4X1(v)			(((v) & 0x3) << 24)
+#define MXC_CCM_CCGR6_PL301_2X2_OFFSET			26
+#define MXC_CCM_CCGR6_PL301_2X2(v)			(((v) & 0x3) << 26)
+#define MXC_CCM_CCGR6_LDB_DI0_OFFSET			28
+#define MXC_CCM_CCGR6_LDB_DI0(v)			(((v) & 0x3) << 28)
+#define MXC_CCM_CCGR6_LDB_DI1_OFFSET			30
+#define MXC_CCM_CCGR6_LDB_DI1(v)			(((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR7_ASRC_IPG_OFFSET			0
+#define MXC_CCM_CCGR7_ASRC_IPG(v)			(((v) & 0x3) << 0)
+#define MXC_CCM_CCGR7_ASRC_ASRCK_OFFSET			2
+#define MXC_CCM_CCGR7_ASRC_ASRCK(v)			(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR7_MLB_OFFSET			4
+#define MXC_CCM_CCGR7_MLB(v)				(((v) & 0x3) << 4)
+#define MXC_CCM_CCGR7_IEEE1588_OFFSET			6
+#define MXC_CCM_CCGR7_IEEE1588(v)			(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR7_UART4_IPG_OFFSET			8
+#define MXC_CCM_CCGR7_UART4_IPG(v)			(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR7_UART4_PER_OFFSET			10
+#define MXC_CCM_CCGR7_UART4_PER(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR7_UART5_IPG_OFFSET			12
+#define MXC_CCM_CCGR7_UART5_IPG(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CCGR7_UART5_PER_OFFSET			14
+#define MXC_CCM_CCGR7_UART5_PER(v)			(((v) & 0x3) << 14)
+#endif
 
 /* Define the bits in register CLPCR */
 #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS                 (0x1 << 18)
diff --git u-boot-imx-e1eb75b.orig/drivers/video/ipu_common.c u-boot-imx-e1eb75b/drivers/video/ipu_common.c
index 2020da9..7869d65 100644
--- u-boot-imx-e1eb75b.orig/drivers/video/ipu_common.c
+++ u-boot-imx-e1eb75b/drivers/video/ipu_common.c
@@ -213,7 +213,7 @@ static struct clk ipu_clk = {
 	.rate = CONFIG_IPUV3_CLK,
 	.enable_reg = (u32 *)(CCM_BASE_ADDR +
 		offsetof(struct mxc_ccm_reg, CCGR5)),
-	.enable_shift = MXC_CCM_CCGR5_CG5_OFFSET,
+	.enable_shift = MXC_CCM_CCGR5_IPU_OFFSET,
 	.enable = clk_ipu_enable,
 	.disable = clk_ipu_disable,
 	.usecount = 0,

[U-Boot] [PATCH v2 04/14] mx5: Fix clock gate values

[Benoît Thébaudeau]

The clock gate values are 2-bit bit-fields. Hence, setting or clearing only one
of these bits like what was done is wrong and can lead to unpredictable behavior
depending on the original value of these bit-fields.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
This patch supersedes http://patchwork.ozlabs.org/patch/177403/ .
Changes for v2:
 - Split patch into 3 parts (the 3, 4 and 5 from this v2 series).

 .../arch/arm/cpu/armv7/mx5/clock.c                 |   27 +++++++++++---------
 .../arch/arm/include/asm/arch-mx5/crm_regs.h       |    3 +++
 2 files changed, 18 insertions(+), 12 deletions(-)

diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
index 32a69d4..df7e5cd 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
@@ -101,10 +101,11 @@ void set_usboh3_clk(void)
 
 void enable_usboh3_clk(unsigned char enable)
 {
-	if (enable)
-		setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_USBOH3_60M(1));
-	else
-		clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_USBOH3_60M(1));
+	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+	clrsetbits_le32(&mxc_ccm->CCGR2,
+			MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK),
+			MXC_CCM_CCGR2_USBOH3_60M(cg));
 }
 
 #ifdef CONFIG_I2C_MXC
@@ -132,10 +133,11 @@ void set_usb_phy1_clk(void)
 
 void enable_usb_phy1_clk(unsigned char enable)
 {
-	if (enable)
-		setbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY1(1));
-	else
-		clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY1(1));
+	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+	clrsetbits_le32(&mxc_ccm->CCGR4,
+			MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
+			MXC_CCM_CCGR4_USB_PHY1(cg));
 }
 
 void set_usb_phy2_clk(void)
@@ -145,10 +147,11 @@ void set_usb_phy2_clk(void)
 
 void enable_usb_phy2_clk(unsigned char enable)
 {
-	if (enable)
-		setbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY2(1));
-	else
-		clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY2(1));
+	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+	clrsetbits_le32(&mxc_ccm->CCGR4,
+			MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
+			MXC_CCM_CCGR4_USB_PHY2(cg));
 }
 
 /*
diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/crm_regs.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/crm_regs.h
index d5eb303..3b0ed64 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -285,6 +285,9 @@ struct mxc_ccm_reg {
 
 /* Define the bits in register CCGRx */
 #define MXC_CCM_CCGR_CG_MASK				0x3
+#define MXC_CCM_CCGR_CG_OFF				0x0
+#define MXC_CCM_CCGR_CG_RUN_ON				0x1
+#define MXC_CCM_CCGR_CG_ON				0x3
 
 #define MXC_CCM_CCGR0_ARM_BUS_OFFSET			0
 #define MXC_CCM_CCGR0_ARM_BUS(v)			(((v) & 0x3) << 0)

[U-Boot] [PATCH v2 05/14] mx51: Fix USB PHY clocks

[Benoît Thébaudeau]

The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks
have different clock gate control bit-fields.

The existing code was correct only for i.MX53, so this patch fixes the i.MX51
use case.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Jana Rapava <fermata7@gmail.com>
Cc: Wolfgang Grandegger <wg@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
---
This patch supersedes http://patchwork.ozlabs.org/patch/177403/ .
Changes for v2:
 - Split patch into 3 parts (the 3, 4 and 5 from this v2 series).
 - Merge the various set_usb_phy*_clk() functions (they were identical).

 .../arch/arm/cpu/armv7/mx5/clock.c                 |   20 +++++++++++++-------
 .../arch/arm/include/asm/arch-mx5/clock.h          |    7 ++++++-
 .../drivers/usb/host/ehci-mx5.c                    |    6 +++++-
 3 files changed, 24 insertions(+), 9 deletions(-)

diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
index df7e5cd..f727cfa 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
@@ -126,11 +126,21 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 }
 #endif
 
-void set_usb_phy1_clk(void)
+void set_usb_phy_clk(void)
 {
 	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
 }
 
+#if defined(CONFIG_MX51)
+void enable_usb_phy_clk(unsigned char enable)
+{
+	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+	clrsetbits_le32(&mxc_ccm->CCGR2,
+			MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
+			MXC_CCM_CCGR2_USB_PHY(cg));
+}
+#elif defined(CONFIG_MX53)
 void enable_usb_phy1_clk(unsigned char enable)
 {
 	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
@@ -140,11 +150,6 @@ void enable_usb_phy1_clk(unsigned char enable)
 			MXC_CCM_CCGR4_USB_PHY1(cg));
 }
 
-void set_usb_phy2_clk(void)
-{
-	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
-}
-
 void enable_usb_phy2_clk(unsigned char enable)
 {
 	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
@@ -153,6 +158,7 @@ void enable_usb_phy2_clk(unsigned char enable)
 			MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
 			MXC_CCM_CCGR4_USB_PHY2(cg));
 }
+#endif
 
 /*
  * Calculate the frequency of PLLn.
@@ -803,7 +809,7 @@ void mxc_set_sata_internal_clock(void)
 	u32 *tmp_base =
 		(u32 *)(IIM_BASE_ADDR + 0x180c);
 
-	set_usb_phy1_clk();
+	set_usb_phy_clk();
 
 	clrsetbits_le32(tmp_base, 0x6, 0x4);
 }
diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/clock.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/clock.h
index 55e3b51..e4ca417 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/clock.h
+++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/clock.h
@@ -56,8 +56,13 @@ u32 imx_get_uartclk(void);
 u32 imx_get_fecclk(void);
 unsigned int mxc_get_clock(enum mxc_clock clk);
 int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
-void set_usb_phy2_clk(void);
+void set_usb_phy_clk(void);
+#if defined(CONFIG_MX51)
+void enable_usb_phy_clk(unsigned char enable);
+#elif defined(CONFIG_MX53)
+void enable_usb_phy1_clk(unsigned char enable);
 void enable_usb_phy2_clk(unsigned char enable);
+#endif
 void set_usboh3_clk(void);
 void enable_usboh3_clk(unsigned char enable);
 void mxc_set_sata_internal_clock(void);
diff --git u-boot-imx-e1eb75b.orig/drivers/usb/host/ehci-mx5.c u-boot-imx-e1eb75b/drivers/usb/host/ehci-mx5.c
index 58cdcbe..5bf89f0 100644
--- u-boot-imx-e1eb75b.orig/drivers/usb/host/ehci-mx5.c
+++ u-boot-imx-e1eb75b/drivers/usb/host/ehci-mx5.c
@@ -221,8 +221,12 @@ int ehci_hcd_init(void)
 
 	set_usboh3_clk();
 	enable_usboh3_clk(1);
-	set_usb_phy2_clk();
+	set_usb_phy_clk();
+#if defined(CONFIG_MX51) && CONFIG_MXC_USB_PORT == 0
+	enable_usb_phy_clk(1);
+#elif defined(CONFIG_MX53)
 	enable_usb_phy2_clk(1);
+#endif
 	mdelay(1);
 
 	/* Do board specific initialization */

[U-Boot] [PATCH v2 06/14] mx5 clocks: Add and use CCSR definitions

[Benoît Thébaudeau]

This fixes config_pll_clk(), which used 0x20 instead of 0x200 for PLL4_CLOCK.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
This patch supersedes http://patchwork.ozlabs.org/patch/177404/ .
Changes for v2:
 - Consequences from the previous cleanup patches.

 .../arch/arm/cpu/armv7/mx5/clock.c                 |   34 +++++++++++++-------
 .../arch/arm/include/asm/arch-mx5/crm_regs.h       |   23 +++++++++++++
 2 files changed, 46 insertions(+), 11 deletions(-)

diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
index f727cfa..137a6f9 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
@@ -36,7 +36,9 @@ enum pll_clocks {
 	PLL1_CLOCK = 0,
 	PLL2_CLOCK,
 	PLL3_CLOCK,
+#ifdef CONFIG_MX53
 	PLL4_CLOCK,
+#endif
 	PLL_CLOCKS,
 };
 
@@ -318,10 +320,10 @@ static u32 get_lp_apm(void)
 	u32 ret_val = 0;
 	u32 ccsr = readl(&mxc_ccm->ccsr);
 
-	if (((ccsr >> 9) & 1) == 0)
-		ret_val = MXC_HCLK;
-	else
+	if (ccsr & MXC_CCM_CCSR_LP_APM)
 		ret_val = MXC_CLK32 * 1024;
+	else
+		ret_val = MXC_HCLK;
 
 	return ret_val;
 }
@@ -587,40 +589,50 @@ static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
 	switch (index) {
 	case PLL1_CLOCK:
 		/* Switch ARM to PLL2 clock */
-		writel(ccsr | 0x4, &mxc_ccm->ccsr);
+		writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
+				&mxc_ccm->ccsr);
 		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
 					pll_param->mfi, pll_param->mfn,
 					pll_param->mfd);
 		/* Switch back */
-		writel(ccsr & ~0x4, &mxc_ccm->ccsr);
+		writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
+				&mxc_ccm->ccsr);
 		break;
 	case PLL2_CLOCK:
 		/* Switch to pll2 bypass clock */
-		writel(ccsr | 0x2, &mxc_ccm->ccsr);
+		writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
+				&mxc_ccm->ccsr);
 		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
 					pll_param->mfi, pll_param->mfn,
 					pll_param->mfd);
 		/* Switch back */
-		writel(ccsr & ~0x2, &mxc_ccm->ccsr);
+		writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
+				&mxc_ccm->ccsr);
 		break;
 	case PLL3_CLOCK:
 		/* Switch to pll3 bypass clock */
-		writel(ccsr | 0x1, &mxc_ccm->ccsr);
+		writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
+				&mxc_ccm->ccsr);
 		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
 					pll_param->mfi, pll_param->mfn,
 					pll_param->mfd);
 		/* Switch back */
-		writel(ccsr & ~0x1, &mxc_ccm->ccsr);
+		writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
+				&mxc_ccm->ccsr);
 		break;
+#ifdef CONFIG_MX53
 	case PLL4_CLOCK:
 		/* Switch to pll4 bypass clock */
-		writel(ccsr | 0x20, &mxc_ccm->ccsr);
+		writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
+				&mxc_ccm->ccsr);
 		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
 					pll_param->mfi, pll_param->mfn,
 					pll_param->mfd);
 		/* Switch back */
-		writel(ccsr & ~0x20, &mxc_ccm->ccsr);
+		writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
+				&mxc_ccm->ccsr);
 		break;
+#endif
 	default:
 		return -EINVAL;
 	}
diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/crm_regs.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/crm_regs.h
index 3b0ed64..56dceb4 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -82,6 +82,29 @@ struct mxc_ccm_reg {
 	u32 cmeor;
 };
 
+/* Define the bits in register CCSR */
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCSR_LP_APM			(0x1 << 9)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCSR_LP_APM			(0x1 << 10)
+#define MXC_CCM_CCSR_PLL4_SW_CLK_SEL		(0x1 << 9)
+#endif
+#define MXC_CCM_CCSR_STEP_SEL_OFFSET		7
+#define MXC_CCM_CCSR_STEP_SEL_MASK		(0x3 << 7)
+#define MXC_CCM_CCSR_STEP_SEL(v)		(((v) & 0x3) << 7)
+#define MXC_CCM_CCSR_STEP_SEL_RD(r)		(((r) >> 7) & 0x3)
+#define MXC_CCM_CCSR_PLL2_DIV_PODF_OFFSET	5
+#define MXC_CCM_CCSR_PLL2_DIV_PODF_MASK		(0x3 << 5)
+#define MXC_CCM_CCSR_PLL2_DIV_PODF(v)		(((v) & 0x3) << 5)
+#define MXC_CCM_CCSR_PLL2_DIV_PODF_RD(r)	(((r) >> 5) & 0x3)
+#define MXC_CCM_CCSR_PLL3_DIV_PODF_OFFSET	3
+#define MXC_CCM_CCSR_PLL3_DIV_PODF_MASK		(0x3 << 3)
+#define MXC_CCM_CCSR_PLL3_DIV_PODF(v)		(((v) & 0x3) << 3)
+#define MXC_CCM_CCSR_PLL3_DIV_PODF_RD(r)	(((r) >> 3) & 0x3)
+#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL		(0x1 << 2)
+#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL		(0x1 << 1)
+#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL		0x1
+
 /* Define the bits in register CACRR */
 #define MXC_CCM_CACRR_ARM_PODF_OFFSET		0
 #define MXC_CCM_CACRR_ARM_PODF_MASK		0x7

[U-Boot] [PATCH v2 07/14] mx5 clocks: Fix get_lp_apm()

[Benoît Thébaudeau]

If CCM.CCSR.lp_apm is set, the lp_apm clock is not necessarily 32768 Hz x 1024.
In that case:
 - on i.MX51, this clock comes from the output of the FPM,
 - on i.MX53, this clock comes from the output of PLL4.

This patch fixes the code accordingly.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
This patch supersedes http://patchwork.ozlabs.org/patch/177405/ .
Changes for v2:
 - Consequences from the previous cleanup patches.
 - Add detailed description.

 .../arch/arm/cpu/armv7/mx5/clock.c                 |   24 +++++++++++++++++++-
 .../arch/arm/include/asm/arch-mx5/crm_regs.h       |   15 ++++++++++++
 2 files changed, 38 insertions(+), 1 deletion(-)

diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
index 137a6f9..6d984cb 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
@@ -216,6 +216,24 @@ static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
 	return ret;
 }
 
+#ifdef CONFIG_MX51
+/*
+ * This function returns the Frequency Pre-Multiplier clock.
+ */
+static u32 get_fpm(void)
+{
+	u32 mult;
+	u32 ccr = readl(&mxc_ccm->ccr);
+
+	if (ccr & MXC_CCM_CCR_FPM_MULT)
+		mult = 1024;
+	else
+		mult = 512;
+
+	return MXC_CLK32 * mult;
+}
+#endif
+
 /*
  * Get mcu main rate
  */
@@ -321,7 +339,11 @@ static u32 get_lp_apm(void)
 	u32 ccsr = readl(&mxc_ccm->ccsr);
 
 	if (ccsr & MXC_CCM_CCSR_LP_APM)
-		ret_val = MXC_CLK32 * 1024;
+#if defined(CONFIG_MX51)
+		ret_val = get_fpm();
+#elif defined(CONFIG_MX53)
+		ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
+#endif
 	else
 		ret_val = MXC_HCLK;
 
diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/crm_regs.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/crm_regs.h
index 56dceb4..ddfab70 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -82,6 +82,21 @@ struct mxc_ccm_reg {
 	u32 cmeor;
 };
 
+/* Define the bits in register CCR */
+#define MXC_CCM_CCR_COSC_EN			(0x1 << 12)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCR_FPM_MULT			(0x1 << 11)
+#endif
+#define MXC_CCM_CCR_CAMP2_EN			(0x1 << 10)
+#define MXC_CCM_CCR_CAMP1_EN			(0x1 << 9)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCR_FPM_EN			(0x1 << 8)
+#endif
+#define MXC_CCM_CCR_OSCNT_OFFSET		0
+#define MXC_CCM_CCR_OSCNT_MASK			0xFF
+#define MXC_CCM_CCR_OSCNT(v)			((v) & 0xFF)
+#define MXC_CCM_CCR_OSCNT_RD(r)			((r) & 0xFF)
+
 /* Define the bits in register CCSR */
 #if defined(CONFIG_MX51)
 #define MXC_CCM_CCSR_LP_APM			(0x1 << 9)

[U-Boot] [PATCH v2 08/14] mx5 clocks: Fix get_periph_clk()

[Benoît Thébaudeau]

In the case periph_clk comes from periph_apm_clk, the latter is selected by the
CCM.CBCMR.periph_apm_sel mux, which can source the lp_apm clock from its
input ?2. get_periph_clk() returned 0 instead of the lp_apm clock frequency in
this case.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
This patch supersedes http://patchwork.ozlabs.org/patch/177406/ .
Changes for v2:
 - Consequences from the previous cleanup patches.
 - Add detailed description.

 .../arch/arm/cpu/armv7/mx5/clock.c                 |   42 ++++++++++----------
 1 file changed, 22 insertions(+), 20 deletions(-)

diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
index 6d984cb..b155214 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
@@ -235,6 +235,26 @@ static u32 get_fpm(void)
 #endif
 
 /*
+ * This function returns the low power audio clock.
+ */
+static u32 get_lp_apm(void)
+{
+	u32 ret_val = 0;
+	u32 ccsr = readl(&mxc_ccm->ccsr);
+
+	if (ccsr & MXC_CCM_CCSR_LP_APM)
+#if defined(CONFIG_MX51)
+		ret_val = get_fpm();
+#elif defined(CONFIG_MX53)
+		ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
+#endif
+	else
+		ret_val = MXC_HCLK;
+
+	return ret_val;
+}
+
+/*
  * Get mcu main rate
  */
 u32 get_mcu_main_clk(void)
@@ -262,6 +282,8 @@ u32 get_periph_clk(void)
 		return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
 	case 1:
 		return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
+	case 2:
+		return get_lp_apm();
 	default:
 		return 0;
 	}
@@ -331,26 +353,6 @@ static u32 get_uart_clk(void)
 }
 
 /*
- * This function returns the low power audio clock.
- */
-static u32 get_lp_apm(void)
-{
-	u32 ret_val = 0;
-	u32 ccsr = readl(&mxc_ccm->ccsr);
-
-	if (ccsr & MXC_CCM_CCSR_LP_APM)
-#if defined(CONFIG_MX51)
-		ret_val = get_fpm();
-#elif defined(CONFIG_MX53)
-		ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
-#endif
-	else
-		ret_val = MXC_HCLK;
-
-	return ret_val;
-}
-
-/*
  * get cspi clock rate.
  */
 static u32 imx_get_cspiclk(void)

[U-Boot] [PATCH v2 09/14] mx5 clocks: Fix get_ipg_per_clk()

[Benoît Thébaudeau]

This fixes the "IPG PERCLK" frequency printed by the clocks command. The issue
was that get_ipg_per_clk() used periph_clk instead of lp_apm in the case
CCM.CBCMR.perclk_lp_apm_sel is set.

It also fixes I?C support.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
This patch supersedes http://patchwork.ozlabs.org/patch/177407/ .
Changes for v2:
 - Consequences from the previous cleanup patches.
 - Improve detailed description.

 .../arch/arm/cpu/armv7/mx5/clock.c                 |   10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
index b155214..c7a3c36 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
@@ -310,16 +310,20 @@ static u32 get_ipg_clk(void)
  */
 static u32 get_ipg_per_clk(void)
 {
-	u32 pred1, pred2, podf;
+	u32 freq, pred1, pred2, podf;
 
 	if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
 		return get_ipg_clk();
-	/* Fixme: not handle what about lpm*/
+
+	if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL)
+		freq = get_lp_apm();
+	else
+		freq = get_periph_clk();
 	podf = readl(&mxc_ccm->cbcdr);
 	pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf);
 	pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf);
 	podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf);
-	return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
+	return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
 }
 
 /*

[U-Boot] [PATCH v2 10/14] mx5 clocks: Fix get_uart_clk()

[Benoît Thébaudeau]

This function returned 66500000 instead of the correct lp_apm clock frequency if
the CCM.CSCMR1.uart_clk_sel mux is set to 3.

This patch fixes this issue by introducing the get_standard_pll_sel_clk()
function that will be used by future patches to handle identical muxes used by
many other clocks.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
This patch supersedes http://patchwork.ozlabs.org/patch/177408/ .
Changes for v2:
 - Consequences from the previous cleanup patches.
 - Add detailed description.

 .../arch/arm/cpu/armv7/mx5/clock.c                 |   36 +++++++++++++-------
 1 file changed, 24 insertions(+), 12 deletions(-)

diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
index c7a3c36..40de128 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
@@ -326,28 +326,40 @@ static u32 get_ipg_per_clk(void)
 	return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
 }
 
-/*
- * Get the rate of uart clk.
- */
-static u32 get_uart_clk(void)
+/* Get the output clock rate of a standard PLL MUX for peripherals. */
+static u32 get_standard_pll_sel_clk(u32 clk_sel)
 {
-	unsigned int freq, reg, pred, podf;
+	u32 freq;
 
-	reg = readl(&mxc_ccm->cscmr1);
-	switch (MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg)) {
-	case 0x0:
+	switch (clk_sel & 0x3) {
+	case 0:
 		freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
 		break;
-	case 0x1:
+	case 1:
 		freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
 		break;
-	case 0x2:
+	case 2:
 		freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
 		break;
-	default:
-		return 66500000;
+	case 3:
+		freq = get_lp_apm();
+		break;
 	}
 
+	return freq;
+}
+
+/*
+ * Get the rate of uart clk.
+ */
+static u32 get_uart_clk(void)
+{
+	unsigned int clk_sel, freq, reg, pred, podf;
+
+	reg = readl(&mxc_ccm->cscmr1);
+	clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg);
+	freq = get_standard_pll_sel_clk(clk_sel);
+
 	reg = readl(&mxc_ccm->cscdr1);
 	pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);
 	podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);

[U-Boot] [PATCH v2 11/14] mx5 clocks: Simplify imx_get_cspiclk()

[Benoît Thébaudeau]

The code handling the dividers was duplicated for each possible input clock, and
this function can benefit from the newly introduced get_standard_pll_sel_clk()
function instead of duplicating this mux handling code.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
This patch supersedes http://patchwork.ozlabs.org/patch/177409/ .
Changes for v2:
 - Consequences from the previous cleanup patches.
 - Add detailed description.

 .../arch/arm/cpu/armv7/mx5/clock.c                 |   23 +++-----------------
 1 file changed, 3 insertions(+), 20 deletions(-)

diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
index 40de128..232d7c8 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
@@ -373,32 +373,15 @@ static u32 get_uart_clk(void)
  */
 static u32 imx_get_cspiclk(void)
 {
-	u32 ret_val = 0, pdf, pre_pdf, clk_sel;
+	u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq;
 	u32 cscmr1 = readl(&mxc_ccm->cscmr1);
 	u32 cscdr2 = readl(&mxc_ccm->cscdr2);
 
 	pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
 	pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
 	clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
-
-	switch (clk_sel) {
-	case 0:
-		ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK) /
-					((pre_pdf + 1) * (pdf + 1));
-		break;
-	case 1:
-		ret_val = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK) /
-					((pre_pdf + 1) * (pdf + 1));
-		break;
-	case 2:
-		ret_val = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK) /
-					((pre_pdf + 1) * (pdf + 1));
-		break;
-	default:
-		ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
-		break;
-	}
-
+	freq = get_standard_pll_sel_clk(clk_sel);
+	ret_val = freq / ((pre_pdf + 1) * (pdf + 1));
 	return ret_val;
 }
 

[U-Boot] [PATCH v2 12/14] mx5 clocks: Fix MXC_FEC_CLK

[Benoît Thébaudeau]

The FEC clock does not come from PLL1, but from the IPG clock. The previous code
was even inconsistent with itself, returning the IPG clock as expected for
imx_get_fecclk(), but the PLL1 clock for mxc_get_clock(MXC_FEC_CLK).

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
This patch supersedes http://patchwork.ozlabs.org/patch/177411/ .
Changes for v2:
 - Consequences from the previous cleanup patches.
 - Add detailed description.

 .../arch/arm/cpu/armv7/mx5/clock.c                 |    5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
index 232d7c8..32dbece 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
@@ -468,7 +468,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 	case MXC_CSPI_CLK:
 		return imx_get_cspiclk();
 	case MXC_FEC_CLK:
-		return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
+		return get_ipg_clk();
 	case MXC_SATA_CLK:
 		return get_ahb_clk();
 	case MXC_DDR_CLK:
@@ -484,10 +484,9 @@ u32 imx_get_uartclk(void)
 	return get_uart_clk();
 }
 
-
 u32 imx_get_fecclk(void)
 {
-	return mxc_get_clock(MXC_IPG_CLK);
+	return get_ipg_clk();
 }
 
 static int gcd(int m, int n)

[U-Boot] [PATCH v2 13/14] mx51: Fix I2C clock ID check

[Benoît Thébaudeau]

There are only 2 I?C instances on i.MX51, but 3 on i.MX53.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2:
 - New patch.

 .../arch/arm/cpu/armv7/mx5/clock.c                 |    6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
index 32dbece..3a60f8b 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
@@ -111,12 +111,16 @@ void enable_usboh3_clk(unsigned char enable)
 }
 
 #ifdef CONFIG_I2C_MXC
-/* i2c_num can be from 0 - 2 */
+/* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 {
 	u32 mask;
 
+#if defined(CONFIG_MX51)
+	if (i2c_num > 1)
+#elif defined(CONFIG_MX53)
 	if (i2c_num > 2)
+#endif
 		return -EINVAL;
 	mask = MXC_CCM_CCGR_CG_MASK <<
 			(MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));

[U-Boot] [PATCH v2 14/14] mx5/6 clocks: Fix SDHC clocks

[Benoît Thébaudeau]

The i.MX5 eSDHC clocks were considered as coming from the IPG clock although
they have dedicated clock paths.

Also, on i.MX5/6, each SDHC instance has a dedicated clock, so gd->sdhc_clk must
be set accordingly. This is good for the case only a single SDHC instance is
used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix
the multi-instance use case (initialization made directly with
fsl_esdhc_initialize()).

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Eric B?nard <eric@eukrea.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
---
This patch supersedes http://patchwork.ozlabs.org/patch/177410/ .
Changes for v2:
 - Consequences from the previous cleanup patches.
 - Add detailed description.
 - Differentiate SDHC instances for gd->sdhc_clk.

 .../arch/arm/cpu/armv7/mx5/clock.c                 |   46 ++++++++++++++++++++
 .../arch/arm/imx-common/speed.c                    |   18 +++++++-
 .../arch/arm/include/asm/arch-mx5/clock.h          |    4 ++
 3 files changed, 67 insertions(+), 1 deletion(-)

diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
index 3a60f8b..25362dc 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
@@ -389,6 +389,44 @@ static u32 imx_get_cspiclk(void)
 	return ret_val;
 }
 
+/*
+ * get esdhc clock rate.
+ */
+static u32 get_esdhc_clk(u32 port)
+{
+	u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;
+	u32 cscmr1 = readl(&mxc_ccm->cscmr1);
+	u32 cscdr1 = readl(&mxc_ccm->cscdr1);
+
+	switch (port) {
+	case 0:
+		clk_sel = MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(cscmr1);
+		pred = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(cscdr1);
+		podf = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(cscdr1);
+		break;
+	case 1:
+		clk_sel = MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(cscmr1);
+		pred = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(cscdr1);
+		podf = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(cscdr1);
+		break;
+	case 2:
+		if (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_CLK_SEL)
+			return get_esdhc_clk(1);
+		else
+			return get_esdhc_clk(0);
+	case 3:
+		if (cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL)
+			return get_esdhc_clk(1);
+		else
+			return get_esdhc_clk(0);
+	default:
+		break;
+	}
+
+	freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));
+	return freq;
+}
+
 static u32 get_axi_a_clk(void)
 {
 	u32 cbcdr = readl(&mxc_ccm->cbcdr);
@@ -471,6 +509,14 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 		return get_uart_clk();
 	case MXC_CSPI_CLK:
 		return imx_get_cspiclk();
+	case MXC_ESDHC_CLK:
+		return get_esdhc_clk(0);
+	case MXC_ESDHC2_CLK:
+		return get_esdhc_clk(1);
+	case MXC_ESDHC3_CLK:
+		return get_esdhc_clk(2);
+	case MXC_ESDHC4_CLK:
+		return get_esdhc_clk(3);
 	case MXC_FEC_CLK:
 		return get_ipg_clk();
 	case MXC_SATA_CLK:
diff --git u-boot-imx-e1eb75b.orig/arch/arm/imx-common/speed.c u-boot-imx-e1eb75b/arch/arm/imx-common/speed.c
index 80989c4..fbf4de3 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/imx-common/speed.c
+++ u-boot-imx-e1eb75b/arch/arm/imx-common/speed.c
@@ -36,9 +36,25 @@ int get_clocks(void)
 {
 #ifdef CONFIG_FSL_ESDHC
 #ifdef CONFIG_FSL_USDHC
+#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
+	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
+	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
+	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+#else
 	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#endif
+#else
+#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
+	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
+	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
+	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 #else
-	gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK);
+	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#endif
 #endif
 #endif
 	return 0;
diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/clock.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/clock.h
index e4ca417..fe0d168 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/clock.h
+++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/clock.h
@@ -45,6 +45,10 @@ enum mxc_clock {
 	MXC_IPG_PERCLK,
 	MXC_UART_CLK,
 	MXC_CSPI_CLK,
+	MXC_ESDHC_CLK,
+	MXC_ESDHC2_CLK,
+	MXC_ESDHC3_CLK,
+	MXC_ESDHC4_CLK,
 	MXC_FEC_CLK,
 	MXC_SATA_CLK,
 	MXC_DDR_CLK,

[U-Boot] [PATCH v2 05/14] mx51: Fix USB PHY clocks

[Marek Vasut]

Dear Beno?t Th?baudeau,

> The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3
> clocks have different clock gate control bit-fields.
> 
> The existing code was correct only for i.MX53, so this patch fixes the
> i.MX51 use case.
> 
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Jana Rapava <fermata7@gmail.com>
> Cc: Wolfgang Grandegger <wg@denx.de>
> Cc: Igor Grinberg <grinberg@compulab.co.il>

Sweet find :-)

Reviewed-by: Marek Vasut <marex@denx.de>

Best regards,
Marek Vasut

[U-Boot] [PATCH v2 05/14] mx51: Fix USB PHY clocks

[Igor Grinberg]

Hi Beno?t,

please, see a minor #ifdef comment below

On 09/27/12 22:21, Beno?t Th?baudeau wrote:
> The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks
> have different clock gate control bit-fields.
> 
> The existing code was correct only for i.MX53, so this patch fixes the i.MX51
> use case.
> 
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Jana Rapava <fermata7@gmail.com>
> Cc: Wolfgang Grandegger <wg@denx.de>
> Cc: Igor Grinberg <grinberg@compulab.co.il>
> ---
> This patch supersedes http://patchwork.ozlabs.org/patch/177403/ .
> Changes for v2:
>  - Split patch into 3 parts (the 3, 4 and 5 from this v2 series).
>  - Merge the various set_usb_phy*_clk() functions (they were identical).
> 
>  .../arch/arm/cpu/armv7/mx5/clock.c                 |   20 +++++++++++++-------
>  .../arch/arm/include/asm/arch-mx5/clock.h          |    7 ++++++-
>  .../drivers/usb/host/ehci-mx5.c                    |    6 +++++-
>  3 files changed, 24 insertions(+), 9 deletions(-)
> 
> diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
> index df7e5cd..f727cfa 100644
> --- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
> +++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
> @@ -126,11 +126,21 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
>  }
>  #endif
>  
> -void set_usb_phy1_clk(void)
> +void set_usb_phy_clk(void)
>  {
>  	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
>  }
>  
> +#if defined(CONFIG_MX51)
> +void enable_usb_phy_clk(unsigned char enable)

I think the same name as the MX53 case will do better, see explanation below.

> +{
> +	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
> +
> +	clrsetbits_le32(&mxc_ccm->CCGR2,
> +			MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
> +			MXC_CCM_CCGR2_USB_PHY(cg));
> +}

I would add here (again explanation below):
void enable_usb_phy2_clk(unsigned char enable)
{
	/* MX51 has a single USB PHY clock, so do nothing here */
}

> +#elif defined(CONFIG_MX53)
>  void enable_usb_phy1_clk(unsigned char enable)
>  {
>  	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
> @@ -140,11 +150,6 @@ void enable_usb_phy1_clk(unsigned char enable)
>  			MXC_CCM_CCGR4_USB_PHY1(cg));
>  }
>  
> -void set_usb_phy2_clk(void)
> -{
> -	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
> -}
> -
>  void enable_usb_phy2_clk(unsigned char enable)
>  {
>  	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
> @@ -153,6 +158,7 @@ void enable_usb_phy2_clk(unsigned char enable)
>  			MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
>  			MXC_CCM_CCGR4_USB_PHY2(cg));
>  }
> +#endif
>  
>  /*
>   * Calculate the frequency of PLLn.
> @@ -803,7 +809,7 @@ void mxc_set_sata_internal_clock(void)
>  	u32 *tmp_base =
>  		(u32 *)(IIM_BASE_ADDR + 0x180c);
>  
> -	set_usb_phy1_clk();
> +	set_usb_phy_clk();
>  
>  	clrsetbits_le32(tmp_base, 0x6, 0x4);
>  }
> diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/clock.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/clock.h
> index 55e3b51..e4ca417 100644
> --- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/clock.h
> +++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/clock.h
> @@ -56,8 +56,13 @@ u32 imx_get_uartclk(void);
>  u32 imx_get_fecclk(void);
>  unsigned int mxc_get_clock(enum mxc_clock clk);
>  int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
> -void set_usb_phy2_clk(void);
> +void set_usb_phy_clk(void);
> +#if defined(CONFIG_MX51)
> +void enable_usb_phy_clk(unsigned char enable);
> +#elif defined(CONFIG_MX53)
> +void enable_usb_phy1_clk(unsigned char enable);
>  void enable_usb_phy2_clk(unsigned char enable);
> +#endif

If you follow my suggestion above, then here you will only have:
 -void set_usb_phy2_clk(void);
 +void set_usb_phy_clk(void);
 +void enable_usb_phy1_clk(unsigned char enable);

and no complicating with #ifdefs needed.

>  void set_usboh3_clk(void);
>  void enable_usboh3_clk(unsigned char enable);
>  void mxc_set_sata_internal_clock(void);
> diff --git u-boot-imx-e1eb75b.orig/drivers/usb/host/ehci-mx5.c u-boot-imx-e1eb75b/drivers/usb/host/ehci-mx5.c
> index 58cdcbe..5bf89f0 100644
> --- u-boot-imx-e1eb75b.orig/drivers/usb/host/ehci-mx5.c
> +++ u-boot-imx-e1eb75b/drivers/usb/host/ehci-mx5.c
> @@ -221,8 +221,12 @@ int ehci_hcd_init(void)
>  
>  	set_usboh3_clk();
>  	enable_usboh3_clk(1);
> -	set_usb_phy2_clk();
> +	set_usb_phy_clk();
> +#if defined(CONFIG_MX51) && CONFIG_MXC_USB_PORT == 0
> +	enable_usb_phy_clk(1);
> +#elif defined(CONFIG_MX53)
>  	enable_usb_phy2_clk(1);
> +#endif

same here, it should be much cleaner.

>  	mdelay(1);
>  
>  	/* Do board specific initialization */
> 

-- 
Regards,
Igor.

[U-Boot] [PATCH v2 01/14] mx5/6: Define default SoC input clock frequencies

[Stefano Babic]

On 27/09/2012 22:19, Beno?t Th?baudeau wrote:
> Define default SoC input clock frequencies for i.MX5/6 in order to get rid of
> duplicated definitions.
> 
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Jason Liu <r64343@freescale.com>
> Cc: Matt Sealey <matt@genesi-usa.com>
> Cc: Fabio Estevam <fabio.estevam@freescale.com>
> ---
> The CONFIG_SYS_MX{5|6}_HCLK and CONFIG_SYS_MX{5|6}_CLK32 definitions set
> to 24000000 and 32768 should also be removed from any new board config file
> added in the meantime if this is applied to the next branch instead of the
> master branch. I am thinking especially about include/configs/mx6qsabresd.h .

That is correct. Fabio, waht do you mind if I drop directly the two
defines from your "configs: mx6: Add a common config file" ?

> 
> This patch supersedes http://patchwork.ozlabs.org/patch/177303/ .
> Changes for v2:
>  - Remove duplicated definition usages instead of spreading them.

We have mainly already discussed about this patch. This alignes the code
for MX5 to the other iMX SOCs.


>  .../arch/arm/cpu/armv7/mx5/clock.c                 |   45 +++++++++-----------
>  .../arch/arm/cpu/armv7/mx6/clock.c                 |   20 ++++-----
>  .../arch/arm/imx-common/timer.c                    |   12 +++---
>  .../arch/arm/include/asm/arch-mx5/clock.h          |   14 ++++++
>  .../arch/arm/include/asm/arch-mx6/clock.h          |   14 ++++++
>  .../board/freescale/mx53loco/mx53loco.c            |    2 +-
>  .../include/configs/ima3-mx53.h                    |    3 --
>  .../include/configs/mx51_efikamx.h                 |    2 -
>  .../include/configs/mx51evk.h                      |    2 -
>  .../include/configs/mx53ard.h                      |    2 -
>  .../include/configs/mx53evk.h                      |    2 -
>  .../include/configs/mx53loco.h                     |    2 -
>  .../include/configs/mx53smd.h                      |    2 -
>  .../include/configs/mx6qarm2.h                     |    2 -
>  .../include/configs/mx6qsabrelite.h                |    2 -
>  .../include/configs/vision2.h                      |    2 -
>  16 files changed, 64 insertions(+), 64 deletions(-)
> 
> diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
> index c67c3cf..1f95536 100644
> --- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
> +++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
> @@ -69,7 +69,7 @@ struct fixed_pll_mfd {
>  };
>  
>  const struct fixed_pll_mfd fixed_mfd[] = {
> -	{CONFIG_SYS_MX5_HCLK, 24 * 16},
> +	{MXC_HCLK, 24 * 16},
>  };
>  
>  struct pll_param {
> @@ -242,7 +242,7 @@ u32 get_mcu_main_clk(void)
>  
>  	reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
>  		MXC_CCM_CACRR_ARM_PODF_OFFSET;
> -	freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
> +	freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
>  	return freq / (reg + 1);
>  }
>  
> @@ -255,14 +255,14 @@ u32 get_periph_clk(void)
>  
>  	reg = __raw_readl(&mxc_ccm->cbcdr);
>  	if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
> -		return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
> +		return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
>  	reg = __raw_readl(&mxc_ccm->cbcmr);
>  	switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
>  		MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
>  	case 0:
> -		return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
> +		return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
>  	case 1:
> -		return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
> +		return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
>  	default:
>  		return 0;
>  	}
> @@ -317,16 +317,13 @@ static u32 get_uart_clk(void)
>  	switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
>  		MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
>  	case 0x0:
> -		freq = decode_pll(mxc_plls[PLL1_CLOCK],
> -				    CONFIG_SYS_MX5_HCLK);
> +		freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
>  		break;
>  	case 0x1:
> -		freq = decode_pll(mxc_plls[PLL2_CLOCK],
> -				    CONFIG_SYS_MX5_HCLK);
> +		freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
>  		break;
>  	case 0x2:
> -		freq = decode_pll(mxc_plls[PLL3_CLOCK],
> -				    CONFIG_SYS_MX5_HCLK);
> +		freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
>  		break;
>  	default:
>  		return 66500000;
> @@ -353,9 +350,9 @@ static u32 get_lp_apm(void)
>  	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
>  
>  	if (((ccsr >> 9) & 1) == 0)
> -		ret_val = CONFIG_SYS_MX5_HCLK;
> +		ret_val = MXC_HCLK;
>  	else
> -		ret_val = ((32768 * 1024));
> +		ret_val = MXC_CLK32 * 1024;
>  
>  	return ret_val;
>  }
> @@ -378,18 +375,15 @@ static u32 imx_get_cspiclk(void)
>  
>  	switch (clk_sel) {
>  	case 0:
> -		ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
> -					CONFIG_SYS_MX5_HCLK) /
> +		ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK) /
>  					((pre_pdf + 1) * (pdf + 1));
>  		break;
>  	case 1:
> -		ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
> -					CONFIG_SYS_MX5_HCLK) /
> +		ret_val = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK) /
>  					((pre_pdf + 1) * (pdf + 1));
>  		break;
>  	case 2:
> -		ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
> -					CONFIG_SYS_MX5_HCLK) /
> +		ret_val = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK) /
>  					((pre_pdf + 1) * (pdf + 1));
>  		break;
>  	default:
> @@ -443,7 +437,7 @@ static u32 get_ddr_clk(void)
>  		u32 ddr_clk_podf = (cbcdr & MXC_CCM_CBCDR_DDR_PODF_MASK) >> \
>  					MXC_CCM_CBCDR_DDR_PODF_OFFSET;
>  
> -		ret_val = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
> +		ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
>  		ret_val /= ddr_clk_podf + 1;
>  
>  		return ret_val;
> @@ -488,8 +482,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
>  	case MXC_CSPI_CLK:
>  		return imx_get_cspiclk();
>  	case MXC_FEC_CLK:
> -		return decode_pll(mxc_plls[PLL1_CLOCK],
> -				    CONFIG_SYS_MX5_HCLK);
> +		return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
>  	case MXC_SATA_CLK:
>  		return get_ahb_clk();
>  	case MXC_DDR_CLK:
> @@ -874,14 +867,14 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>  {
>  	u32 freq;
>  
> -	freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
> +	freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
>  	printf("PLL1       %8d MHz\n", freq / 1000000);
> -	freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
> +	freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
>  	printf("PLL2       %8d MHz\n", freq / 1000000);
> -	freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
> +	freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
>  	printf("PLL3       %8d MHz\n", freq / 1000000);
>  #ifdef	CONFIG_MX53
> -	freq = decode_pll(mxc_plls[PLL4_CLOCK], CONFIG_SYS_MX5_HCLK);
> +	freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
>  	printf("PLL4       %8d MHz\n", freq / 1000000);
>  #endif
>  
> diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx6/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx6/clock.c
> index fddb373..7b31e4f 100644
> --- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx6/clock.c
> +++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx6/clock.c
> @@ -108,7 +108,7 @@ static u32 get_mcu_main_clk(void)
>  	reg = __raw_readl(&imx_ccm->cacrr);
>  	reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
>  	reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
> -	freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
> +	freq = decode_pll(PLL_SYS, MXC_HCLK);
>  
>  	return freq / (reg + 1);
>  }
> @@ -125,11 +125,11 @@ u32 get_periph_clk(void)
>  
>  		switch (reg) {
>  		case 0:
> -			freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
> +			freq = decode_pll(PLL_USBOTG, MXC_HCLK);
>  			break;
>  		case 1:
>  		case 2:
> -			freq = CONFIG_SYS_MX6_HCLK;
> +			freq = MXC_HCLK;
>  			break;
>  		default:
>  			break;
> @@ -141,7 +141,7 @@ u32 get_periph_clk(void)
>  
>  		switch (reg) {
>  		case 0:
> -			freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
> +			freq = decode_pll(PLL_BUS, MXC_HCLK);
>  			break;
>  		case 1:
>  			freq = PLL2_PFD2_FREQ;
> @@ -237,7 +237,7 @@ static u32 get_emi_slow_clk(void)
>  		root_freq = get_axi_clk();
>  		break;
>  	case 1:
> -		root_freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
> +		root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
>  		break;
>  	case 2:
>  		root_freq = PLL2_PFD2_FREQ;
> @@ -309,7 +309,7 @@ u32 imx_get_uartclk(void)
>  
>  u32 imx_get_fecclk(void)
>  {
> -	return decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
> +	return decode_pll(PLL_ENET, MXC_HCLK);
>  }
>  
>  int enable_sata_clock(void)
> @@ -389,13 +389,13 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
>  int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>  {
>  	u32 freq;
> -	freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
> +	freq = decode_pll(PLL_SYS, MXC_HCLK);
>  	printf("PLL_SYS    %8d MHz\n", freq / 1000000);
> -	freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
> +	freq = decode_pll(PLL_BUS, MXC_HCLK);
>  	printf("PLL_BUS    %8d MHz\n", freq / 1000000);
> -	freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
> +	freq = decode_pll(PLL_USBOTG, MXC_HCLK);
>  	printf("PLL_OTG    %8d MHz\n", freq / 1000000);
> -	freq = decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
> +	freq = decode_pll(PLL_ENET, MXC_HCLK);
>  	printf("PLL_NET    %8d MHz\n", freq / 1000000);
>  
>  	printf("\n");
> diff --git u-boot-imx-e1eb75b.orig/arch/arm/imx-common/timer.c u-boot-imx-e1eb75b/arch/arm/imx-common/timer.c
> index e2725e1..b021903 100644
> --- u-boot-imx-e1eb75b.orig/arch/arm/imx-common/timer.c
> +++ u-boot-imx-e1eb75b/arch/arm/imx-common/timer.c
> @@ -27,6 +27,7 @@
>  #include <asm/io.h>
>  #include <div64.h>
>  #include <asm/arch/imx-regs.h>
> +#include <asm/arch/clock.h>
>  
>  /* General purpose timers registers */
>  struct mxc_gpt {
> @@ -44,7 +45,6 @@ static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
>  #define GPTCR_FRR		(1 << 9)	/* Freerun / restart */
>  #define GPTCR_CLKSOURCE_32	(4 << 6)	/* Clock source */
>  #define GPTCR_TEN		1		/* Timer enable */
> -#define CLK_32KHZ		32768		/* 32Khz input */
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> @@ -54,14 +54,14 @@ DECLARE_GLOBAL_DATA_PTR;
>  static inline unsigned long long tick_to_time(unsigned long long tick)
>  {
>  	tick *= CONFIG_SYS_HZ;
> -	do_div(tick, CLK_32KHZ);
> +	do_div(tick, MXC_CLK32);
>  
>  	return tick;
>  }
>  
>  static inline unsigned long long us_to_tick(unsigned long long usec)
>  {
> -	usec = usec * CLK_32KHZ + 999999;
> +	usec = usec * MXC_CLK32 + 999999;
>  	do_div(usec, 1000000);
>  
>  	return usec;
> @@ -86,7 +86,7 @@ int timer_init(void)
>  	__raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
>  
>  	val = __raw_readl(&cur_gpt->counter);
> -	lastinc = val / (CLK_32KHZ / CONFIG_SYS_HZ);
> +	lastinc = val / (MXC_CLK32 / CONFIG_SYS_HZ);
>  	timestamp = 0;
>  
>  	return 0;
> @@ -114,7 +114,7 @@ ulong get_timer_masked(void)
>  {
>  	/*
>  	 * get_ticks() returns a long long (64 bit), it wraps in
> -	 * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
> +	 * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
>  	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
>  	 * 5 * 10^6 days - long enough.
>  	 */
> @@ -145,5 +145,5 @@ void __udelay(unsigned long usec)
>   */
>  ulong get_tbclk(void)
>  {
> -	return CLK_32KHZ;
> +	return MXC_CLK32;
>  }
> diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/clock.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/clock.h
> index 8d8fa18..55e3b51 100644
> --- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/clock.h
> +++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/clock.h
> @@ -24,6 +24,20 @@
>  #ifndef __ASM_ARCH_CLOCK_H
>  #define __ASM_ARCH_CLOCK_H
>  
> +#include <common.h>
> +
> +#ifdef CONFIG_SYS_MX5_HCLK
> +#define MXC_HCLK	CONFIG_SYS_MX5_HCLK
> +#else
> +#define MXC_HCLK	24000000
> +#endif
> +
> +#ifdef CONFIG_SYS_MX5_CLK32
> +#define MXC_CLK32	CONFIG_SYS_MX5_CLK32
> +#else
> +#define MXC_CLK32	32768
> +#endif
> +
>  enum mxc_clock {
>  	MXC_ARM_CLK = 0,
>  	MXC_AHB_CLK,
> diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx6/clock.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx6/clock.h
> index c55c18d..44b2359 100644
> --- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx6/clock.h
> +++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx6/clock.h
> @@ -24,6 +24,20 @@
>  #ifndef __ASM_ARCH_CLOCK_H
>  #define __ASM_ARCH_CLOCK_H
>  
> +#include <common.h>
> +
> +#ifdef CONFIG_SYS_MX6_HCLK
> +#define MXC_HCLK	CONFIG_SYS_MX6_HCLK
> +#else
> +#define MXC_HCLK	24000000
> +#endif
> +
> +#ifdef CONFIG_SYS_MX6_CLK32
> +#define MXC_CLK32	CONFIG_SYS_MX6_CLK32
> +#else
> +#define MXC_CLK32	32768
> +#endif
> +
>  enum mxc_clock {
>  	MXC_ARM_CLK = 0,
>  	MXC_PER_CLK,
> diff --git u-boot-imx-e1eb75b.orig/board/freescale/mx53loco/mx53loco.c u-boot-imx-e1eb75b/board/freescale/mx53loco/mx53loco.c
> index 8f82125..6543209 100644
> --- u-boot-imx-e1eb75b.orig/board/freescale/mx53loco/mx53loco.c
> +++ u-boot-imx-e1eb75b/board/freescale/mx53loco/mx53loco.c
> @@ -394,7 +394,7 @@ static int power_init(void)
>  static void clock_1GHz(void)
>  {
>  	int ret;
> -	u32 ref_clk = CONFIG_SYS_MX5_HCLK;
> +	u32 ref_clk = MXC_HCLK;
>  	/*
>  	 * After increasing voltage to 1.25V, we can switch
>  	 * CPU clock to 1GHz and DDR to 400MHz safely
> diff --git u-boot-imx-e1eb75b.orig/include/configs/ima3-mx53.h u-boot-imx-e1eb75b/include/configs/ima3-mx53.h
> index dbc59b9..499fb37 100644
> --- u-boot-imx-e1eb75b.orig/include/configs/ima3-mx53.h
> +++ u-boot-imx-e1eb75b/include/configs/ima3-mx53.h
> @@ -28,9 +28,6 @@
>  #include <asm/arch/imx-regs.h>
>  #include <asm/arch/mx5x_pins.h>
>  
> -#define CONFIG_SYS_MX5_HCLK		24000000
> -#define CONFIG_SYS_MX5_CLK32		32768
> -
>  #define CONFIG_DISPLAY_CPUINFO
>  #define CONFIG_DISPLAY_BOARDINFO
>  
> diff --git u-boot-imx-e1eb75b.orig/include/configs/mx51_efikamx.h u-boot-imx-e1eb75b/include/configs/mx51_efikamx.h
> index 439b5f3..ffe771f 100644
> --- u-boot-imx-e1eb75b.orig/include/configs/mx51_efikamx.h
> +++ u-boot-imx-e1eb75b/include/configs/mx51_efikamx.h
> @@ -37,8 +37,6 @@
>  
>  #include <asm/arch/imx-regs.h>
>  
> -#define CONFIG_SYS_MX5_HCLK		24000000
> -#define CONFIG_SYS_MX5_CLK32		32768
>  #define CONFIG_DISPLAY_CPUINFO
>  #define CONFIG_DISPLAY_BOARDINFO
>  
> diff --git u-boot-imx-e1eb75b.orig/include/configs/mx51evk.h u-boot-imx-e1eb75b/include/configs/mx51evk.h
> index 7b027b4..34b0783 100644
> --- u-boot-imx-e1eb75b.orig/include/configs/mx51evk.h
> +++ u-boot-imx-e1eb75b/include/configs/mx51evk.h
> @@ -28,8 +28,6 @@
>  
>  #define CONFIG_MX51	/* in a mx51 */
>  
> -#define CONFIG_SYS_MX5_HCLK	24000000
> -#define CONFIG_SYS_MX5_CLK32		32768
>  #define CONFIG_DISPLAY_CPUINFO
>  #define CONFIG_DISPLAY_BOARDINFO
>  
> diff --git u-boot-imx-e1eb75b.orig/include/configs/mx53ard.h u-boot-imx-e1eb75b/include/configs/mx53ard.h
> index 6ab4cde..fea93b4 100644
> --- u-boot-imx-e1eb75b.orig/include/configs/mx53ard.h
> +++ u-boot-imx-e1eb75b/include/configs/mx53ard.h
> @@ -24,8 +24,6 @@
>  
>  #define CONFIG_MX53
>  
> -#define CONFIG_SYS_MX5_HCLK	24000000
> -#define CONFIG_SYS_MX5_CLK32		32768
>  #define CONFIG_DISPLAY_CPUINFO
>  #define CONFIG_DISPLAY_BOARDINFO
>  
> diff --git u-boot-imx-e1eb75b.orig/include/configs/mx53evk.h u-boot-imx-e1eb75b/include/configs/mx53evk.h
> index b46855f..832050e 100644
> --- u-boot-imx-e1eb75b.orig/include/configs/mx53evk.h
> +++ u-boot-imx-e1eb75b/include/configs/mx53evk.h
> @@ -24,8 +24,6 @@
>  
>  #define CONFIG_MX53
>  
> -#define CONFIG_SYS_MX5_HCLK	24000000
> -#define CONFIG_SYS_MX5_CLK32		32768
>  #define CONFIG_DISPLAY_CPUINFO
>  #define CONFIG_DISPLAY_BOARDINFO
>  
> diff --git u-boot-imx-e1eb75b.orig/include/configs/mx53loco.h u-boot-imx-e1eb75b/include/configs/mx53loco.h
> index 8cbaf08..6a6aaa1 100644
> --- u-boot-imx-e1eb75b.orig/include/configs/mx53loco.h
> +++ u-boot-imx-e1eb75b/include/configs/mx53loco.h
> @@ -25,8 +25,6 @@
>  
>  #define CONFIG_MX53
>  
> -#define CONFIG_SYS_MX5_HCLK	24000000
> -#define CONFIG_SYS_MX5_CLK32		32768
>  #define CONFIG_DISPLAY_BOARDINFO
>  
>  #define CONFIG_MACH_TYPE	MACH_TYPE_MX53_LOCO
> diff --git u-boot-imx-e1eb75b.orig/include/configs/mx53smd.h u-boot-imx-e1eb75b/include/configs/mx53smd.h
> index f54d328..ff2a290 100644
> --- u-boot-imx-e1eb75b.orig/include/configs/mx53smd.h
> +++ u-boot-imx-e1eb75b/include/configs/mx53smd.h
> @@ -24,8 +24,6 @@
>  
>  #define CONFIG_MX53
>  
> -#define CONFIG_SYS_MX5_HCLK	24000000
> -#define CONFIG_SYS_MX5_CLK32		32768
>  #define CONFIG_DISPLAY_CPUINFO
>  #define CONFIG_DISPLAY_BOARDINFO
>  
> diff --git u-boot-imx-e1eb75b.orig/include/configs/mx6qarm2.h u-boot-imx-e1eb75b/include/configs/mx6qarm2.h
> index 6c17895..965bea3 100644
> --- u-boot-imx-e1eb75b.orig/include/configs/mx6qarm2.h
> +++ u-boot-imx-e1eb75b/include/configs/mx6qarm2.h
> @@ -23,8 +23,6 @@
>  #define __CONFIG_H
>  
>  #define CONFIG_MX6Q
> -#define CONFIG_SYS_MX6_HCLK		24000000
> -#define CONFIG_SYS_MX6_CLK32		32768
>  #define CONFIG_DISPLAY_CPUINFO
>  #define CONFIG_DISPLAY_BOARDINFO
>  
> diff --git u-boot-imx-e1eb75b.orig/include/configs/mx6qsabrelite.h u-boot-imx-e1eb75b/include/configs/mx6qsabrelite.h
> index 72d0154..e7bf658 100644
> --- u-boot-imx-e1eb75b.orig/include/configs/mx6qsabrelite.h
> +++ u-boot-imx-e1eb75b/include/configs/mx6qsabrelite.h
> @@ -23,8 +23,6 @@
>  #define __CONFIG_H
>  
>  #define CONFIG_MX6Q
> -#define CONFIG_SYS_MX6_HCLK	       24000000
> -#define CONFIG_SYS_MX6_CLK32	       32768
>  #define CONFIG_DISPLAY_CPUINFO
>  #define CONFIG_DISPLAY_BOARDINFO
>  
> diff --git u-boot-imx-e1eb75b.orig/include/configs/vision2.h u-boot-imx-e1eb75b/include/configs/vision2.h
> index fba897c..848df88 100644
> --- u-boot-imx-e1eb75b.orig/include/configs/vision2.h
> +++ u-boot-imx-e1eb75b/include/configs/vision2.h
> @@ -30,8 +30,6 @@
>  
>  #include <asm/arch/imx-regs.h>
>  
> -#define CONFIG_SYS_MX5_HCLK	24000000
> -#define CONFIG_SYS_MX5_CLK32		32768
>  #define CONFIG_DISPLAY_CPUINFO
>  #define CONFIG_DISPLAY_BOARDINFO
>  
> 

Acked-by: Stefano Babic <sbabic@denx.de>
Tested-by: Stefano Babic <sbabic@denx.de>

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 02/14] mx5 clocks: Cleanup

[Stefano Babic]

On 27/09/2012 22:20, Beno?t Th?baudeau wrote:
> Clean up the i.MX5 clock driver:
>  - Use readl() and writel() instead of their __raw_ counterparts.
>  - Use the clr/setbits_le32() family of macros rather than expanding code.
>  - Use accessor macros for bit-fields instead of _MASK and _OFFSET.
> 
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> Changes for v2:
>  - New patch.
> 
>  .../arch/arm/cpu/armv7/mx5/clock.c                 |  237 ++++++++------------
>  .../arch/arm/include/asm/arch-mx5/crm_regs.h       |   99 +++++++-
>  2 files changed, 184 insertions(+), 152 deletions(-)
> 
> diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
> index 1f95536..5fca775 100644
> --- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
> +++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
> @@ -89,94 +89,65 @@ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
>  
>  void set_usboh3_clk(void)
>  {
> -	unsigned int reg;
> -
> -	reg = readl(&mxc_ccm->cscmr1) &
> -		 ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
> -	reg |= 1 << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
> -	writel(reg, &mxc_ccm->cscmr1);
> -
> -	reg = readl(&mxc_ccm->cscdr1);
> -	reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK;
> -	reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK;
> -	reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET;
> -	reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET;
> -
> -	writel(reg, &mxc_ccm->cscdr1);
> +	clrsetbits_le32(&mxc_ccm->cscmr1,
> +			MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK,
> +			MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1));
> +	clrsetbits_le32(&mxc_ccm->cscdr1,
> +			MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK |
> +			MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK,
> +			MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) |
> +			MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
>  }
>  
>  void enable_usboh3_clk(unsigned char enable)
>  {
> -	unsigned int reg;
> -
> -	reg = readl(&mxc_ccm->CCGR2);
>  	if (enable)
> -		reg |= 1 << MXC_CCM_CCGR2_CG14_OFFSET;
> +		setbits_le32(&mxc_ccm->CCGR2, 1 << MXC_CCM_CCGR2_CG14_OFFSET);
>  	else
> -		reg &= ~(1 << MXC_CCM_CCGR2_CG14_OFFSET);
> -	writel(reg, &mxc_ccm->CCGR2);
> +		clrbits_le32(&mxc_ccm->CCGR2, 1 << MXC_CCM_CCGR2_CG14_OFFSET);
>  }
>  
>  #ifdef CONFIG_I2C_MXC
>  /* i2c_num can be from 0 - 2 */
>  int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
>  {
> -	u32 reg;
>  	u32 mask;
>  
>  	if (i2c_num > 2)
>  		return -EINVAL;
>  	mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 9) << 1);
> -	reg = __raw_readl(&mxc_ccm->CCGR1);
>  	if (enable)
> -		reg |= mask;
> +		setbits_le32(&mxc_ccm->CCGR1, mask);
>  	else
> -		reg &= ~mask;
> -	__raw_writel(reg, &mxc_ccm->CCGR1);
> +		clrbits_le32(&mxc_ccm->CCGR1, mask);
>  	return 0;
>  }
>  #endif
>  
>  void set_usb_phy1_clk(void)
>  {
> -	unsigned int reg;
> -
> -	reg = readl(&mxc_ccm->cscmr1);
> -	reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
> -	writel(reg, &mxc_ccm->cscmr1);
> +	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
>  }
>  
>  void enable_usb_phy1_clk(unsigned char enable)
>  {
> -	unsigned int reg;
> -
> -	reg = readl(&mxc_ccm->CCGR4);
>  	if (enable)
> -		reg |= 1 << MXC_CCM_CCGR4_CG5_OFFSET;
> +		setbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG5_OFFSET);
>  	else
> -		reg &= ~(1 << MXC_CCM_CCGR4_CG5_OFFSET);
> -	writel(reg, &mxc_ccm->CCGR4);
> +		clrbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG5_OFFSET);
>  }
>  
>  void set_usb_phy2_clk(void)
>  {
> -	unsigned int reg;
> -
> -	reg = readl(&mxc_ccm->cscmr1);
> -	reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
> -	writel(reg, &mxc_ccm->cscmr1);
> +	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
>  }
>  
>  void enable_usb_phy2_clk(unsigned char enable)
>  {
> -	unsigned int reg;
> -
> -	reg = readl(&mxc_ccm->CCGR4);
>  	if (enable)
> -		reg |= 1 << MXC_CCM_CCGR4_CG6_OFFSET;
> +		setbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG6_OFFSET);
>  	else
> -		reg &= ~(1 << MXC_CCM_CCGR4_CG6_OFFSET);
> -	writel(reg, &mxc_ccm->CCGR4);
> +		clrbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG6_OFFSET);
>  }
>  
>  /*
> @@ -191,19 +162,19 @@ static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
>  	ctrl = readl(&pll->ctrl);
>  
>  	if (ctrl & MXC_DPLLC_CTL_HFSM) {
> -		mfn = __raw_readl(&pll->hfs_mfn);
> -		mfd = __raw_readl(&pll->hfs_mfd);
> -		op = __raw_readl(&pll->hfs_op);
> +		mfn = readl(&pll->hfs_mfn);
> +		mfd = readl(&pll->hfs_mfd);
> +		op = readl(&pll->hfs_op);
>  	} else {
> -		mfn = __raw_readl(&pll->mfn);
> -		mfd = __raw_readl(&pll->mfd);
> -		op = __raw_readl(&pll->op);
> +		mfn = readl(&pll->mfn);
> +		mfd = readl(&pll->mfd);
> +		op = readl(&pll->op);
>  	}
>  
>  	mfd &= MXC_DPLLC_MFD_MFD_MASK;
>  	mfn &= MXC_DPLLC_MFN_MFN_MASK;
>  	pdf = op & MXC_DPLLC_OP_PDF_MASK;
> -	mfi = (op & MXC_DPLLC_OP_MFI_MASK) >> MXC_DPLLC_OP_MFI_OFFSET;
> +	mfi = MXC_DPLLC_OP_MFI_RD(op);
>  
>  	/* 21.2.3 */
>  	if (mfi < 5)
> @@ -240,8 +211,7 @@ u32 get_mcu_main_clk(void)
>  {
>  	u32 reg, freq;
>  
> -	reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
> -		MXC_CCM_CACRR_ARM_PODF_OFFSET;
> +	reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr));
>  	freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
>  	return freq / (reg + 1);
>  }
> @@ -253,12 +223,11 @@ u32 get_periph_clk(void)
>  {
>  	u32 reg;
>  
> -	reg = __raw_readl(&mxc_ccm->cbcdr);
> +	reg = readl(&mxc_ccm->cbcdr);
>  	if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
>  		return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
> -	reg = __raw_readl(&mxc_ccm->cbcmr);
> -	switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
> -		MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
> +	reg = readl(&mxc_ccm->cbcmr);
> +	switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) {
>  	case 0:
>  		return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
>  	case 1:
> @@ -278,9 +247,8 @@ static u32 get_ipg_clk(void)
>  
>  	freq = get_ahb_clk();
>  
> -	reg = __raw_readl(&mxc_ccm->cbcdr);
> -	div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
> -			MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
> +	reg = readl(&mxc_ccm->cbcdr);
> +	div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1;
>  
>  	return freq / div;
>  }
> @@ -292,17 +260,13 @@ static u32 get_ipg_per_clk(void)
>  {
>  	u32 pred1, pred2, podf;
>  
> -	if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
> +	if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
>  		return get_ipg_clk();
>  	/* Fixme: not handle what about lpm*/
> -	podf = __raw_readl(&mxc_ccm->cbcdr);
> -	pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
> -		MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
> -	pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
> -		MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
> -	podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
> -		MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
> -
> +	podf = readl(&mxc_ccm->cbcdr);
> +	pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf);
> +	pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf);
> +	podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf);
>  	return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
>  }
>  
> @@ -313,9 +277,8 @@ static u32 get_uart_clk(void)
>  {
>  	unsigned int freq, reg, pred, podf;
>  
> -	reg = __raw_readl(&mxc_ccm->cscmr1);
> -	switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
> -		MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
> +	reg = readl(&mxc_ccm->cscmr1);
> +	switch (MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg)) {
>  	case 0x0:
>  		freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
>  		break;
> @@ -329,13 +292,9 @@ static u32 get_uart_clk(void)
>  		return 66500000;
>  	}
>  
> -	reg = __raw_readl(&mxc_ccm->cscdr1);
> -
> -	pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
> -		MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
> -
> -	podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
> -		MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
> +	reg = readl(&mxc_ccm->cscdr1);
> +	pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);
> +	podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);
>  	freq /= (pred + 1) * (podf + 1);
>  
>  	return freq;
> @@ -347,7 +306,7 @@ static u32 get_uart_clk(void)
>  static u32 get_lp_apm(void)
>  {
>  	u32 ret_val = 0;
> -	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
> +	u32 ccsr = readl(&mxc_ccm->ccsr);
>  
>  	if (((ccsr >> 9) & 1) == 0)
>  		ret_val = MXC_HCLK;
> @@ -363,15 +322,12 @@ static u32 get_lp_apm(void)
>  static u32 imx_get_cspiclk(void)
>  {
>  	u32 ret_val = 0, pdf, pre_pdf, clk_sel;
> -	u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
> -	u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2);
> +	u32 cscmr1 = readl(&mxc_ccm->cscmr1);
> +	u32 cscdr2 = readl(&mxc_ccm->cscdr2);
>  
> -	pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
> -			>> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
> -	pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
> -			>> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
> -	clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
> -			>> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
> +	pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
> +	pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
> +	clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
>  
>  	switch (clk_sel) {
>  	case 0:
> @@ -396,28 +352,25 @@ static u32 imx_get_cspiclk(void)
>  
>  static u32 get_axi_a_clk(void)
>  {
> -	u32 cbcdr =  __raw_readl(&mxc_ccm->cbcdr);
> -	u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_A_PODF_MASK) \
> -			>> MXC_CCM_CBCDR_AXI_A_PODF_OFFSET;
> +	u32 cbcdr = readl(&mxc_ccm->cbcdr);
> +	u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr);
>  
>  	return  get_periph_clk() / (pdf + 1);
>  }
>  
>  static u32 get_axi_b_clk(void)
>  {
> -	u32 cbcdr =  __raw_readl(&mxc_ccm->cbcdr);
> -	u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_B_PODF_MASK) \
> -			>> MXC_CCM_CBCDR_AXI_B_PODF_OFFSET;
> +	u32 cbcdr = readl(&mxc_ccm->cbcdr);
> +	u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr);
>  
>  	return  get_periph_clk() / (pdf + 1);
>  }
>  
>  static u32 get_emi_slow_clk(void)
>  {
> -	u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
> +	u32 cbcdr = readl(&mxc_ccm->cbcdr);
>  	u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
> -	u32 pdf = (cbcdr & MXC_CCM_CBCDR_EMI_PODF_MASK) \
> -			>> MXC_CCM_CBCDR_EMI_PODF_OFFSET;
> +	u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr);
>  
>  	if (emi_clk_sel)
>  		return  get_ahb_clk() / (pdf + 1);
> @@ -428,14 +381,12 @@ static u32 get_emi_slow_clk(void)
>  static u32 get_ddr_clk(void)
>  {
>  	u32 ret_val = 0;
> -	u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
> -	u32 ddr_clk_sel = (cbcmr & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) \
> -				>> MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET;
> +	u32 cbcmr = readl(&mxc_ccm->cbcmr);
> +	u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
>  #ifdef CONFIG_MX51
> -	u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
> +	u32 cbcdr = readl(&mxc_ccm->cbcdr);
>  	if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
> -		u32 ddr_clk_podf = (cbcdr & MXC_CCM_CBCDR_DDR_PODF_MASK) >> \
> -					MXC_CCM_CBCDR_DDR_PODF_OFFSET;
> +		u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
>  
>  		ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
>  		ret_val /= ddr_clk_podf + 1;
> @@ -603,62 +554,62 @@ static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
>  
>  #define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
>  	{	\
> -		__raw_writel(0x1232, &pll->ctrl);		\
> -		__raw_writel(0x2, &pll->config);		\
> -		__raw_writel((((pd) - 1) << 0) | ((fi) << 4),	\
> -			&pll->op);				\
> -		__raw_writel(fn, &(pll->mfn));			\
> -		__raw_writel((fd) - 1, &pll->mfd);		\
> -		__raw_writel((((pd) - 1) << 0) | ((fi) << 4),	\
> -			&pll->hfs_op);				\
> -		__raw_writel(fn, &pll->hfs_mfn);		\
> -		__raw_writel((fd) - 1, &pll->hfs_mfd);		\
> -		__raw_writel(0x1232, &pll->ctrl);		\
> -		while (!__raw_readl(&pll->ctrl) & 0x1)		\
> +		writel(0x1232, &pll->ctrl);		\
> +		writel(0x2, &pll->config);		\
> +		writel((((pd) - 1) << 0) | ((fi) << 4),	\
> +			&pll->op);			\
> +		writel(fn, &(pll->mfn));		\
> +		writel((fd) - 1, &pll->mfd);		\
> +		writel((((pd) - 1) << 0) | ((fi) << 4),	\
> +			&pll->hfs_op);			\
> +		writel(fn, &pll->hfs_mfn);		\
> +		writel((fd) - 1, &pll->hfs_mfd);	\
> +		writel(0x1232, &pll->ctrl);		\
> +		while (!readl(&pll->ctrl) & 0x1)	\
>  			;\
>  	}
>  
>  static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
>  {
> -	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
> +	u32 ccsr = readl(&mxc_ccm->ccsr);
>  	struct mxc_pll_reg *pll = mxc_plls[index];
>  
>  	switch (index) {
>  	case PLL1_CLOCK:
>  		/* Switch ARM to PLL2 clock */
> -		__raw_writel(ccsr | 0x4, &mxc_ccm->ccsr);
> +		writel(ccsr | 0x4, &mxc_ccm->ccsr);
>  		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
>  					pll_param->mfi, pll_param->mfn,
>  					pll_param->mfd);
>  		/* Switch back */
> -		__raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr);
> +		writel(ccsr & ~0x4, &mxc_ccm->ccsr);
>  		break;
>  	case PLL2_CLOCK:
>  		/* Switch to pll2 bypass clock */
> -		__raw_writel(ccsr | 0x2, &mxc_ccm->ccsr);
> +		writel(ccsr | 0x2, &mxc_ccm->ccsr);
>  		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
>  					pll_param->mfi, pll_param->mfn,
>  					pll_param->mfd);
>  		/* Switch back */
> -		__raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr);
> +		writel(ccsr & ~0x2, &mxc_ccm->ccsr);
>  		break;
>  	case PLL3_CLOCK:
>  		/* Switch to pll3 bypass clock */
> -		__raw_writel(ccsr | 0x1, &mxc_ccm->ccsr);
> +		writel(ccsr | 0x1, &mxc_ccm->ccsr);
>  		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
>  					pll_param->mfi, pll_param->mfn,
>  					pll_param->mfd);
>  		/* Switch back */
> -		__raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr);
> +		writel(ccsr & ~0x1, &mxc_ccm->ccsr);
>  		break;
>  	case PLL4_CLOCK:
>  		/* Switch to pll4 bypass clock */
> -		__raw_writel(ccsr | 0x20, &mxc_ccm->ccsr);
> +		writel(ccsr | 0x20, &mxc_ccm->ccsr);
>  		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
>  					pll_param->mfi, pll_param->mfn,
>  					pll_param->mfd);
>  		/* Switch back */
> -		__raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr);
> +		writel(ccsr & ~0x20, &mxc_ccm->ccsr);
>  		break;
>  	default:
>  		return -EINVAL;
> @@ -687,7 +638,6 @@ static int config_core_clk(u32 ref, u32 freq)
>  
>  static int config_nfc_clk(u32 nfc_clk)
>  {
> -	u32 reg;
>  	u32 parent_rate = get_emi_slow_clk();
>  	u32 div = parent_rate / nfc_clk;
>  
> @@ -697,11 +647,10 @@ static int config_nfc_clk(u32 nfc_clk)
>  		div++;
>  	if (parent_rate / div > NFC_CLK_MAX)
>  		div++;
> -	reg = __raw_readl(&mxc_ccm->cbcdr);
> -	reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
> -	reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
> -	__raw_writel(reg, &mxc_ccm->cbcdr);
> -	while (__raw_readl(&mxc_ccm->cdhipr) != 0)
> +	clrsetbits_le32(&mxc_ccm->cbcdr,
> +			MXC_CCM_CBCDR_NFC_PODF_MASK,
> +			MXC_CCM_CBCDR_NFC_PODF(div - 1));
> +	while (readl(&mxc_ccm->cdhipr) != 0)
>  		;
>  	return 0;
>  }
> @@ -714,16 +663,15 @@ static int config_periph_clk(u32 ref, u32 freq)
>  
>  	memset(&pll_param, 0, sizeof(struct pll_param));
>  
> -	if (__raw_readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
> +	if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
>  		ret = calc_pll_params(ref, freq, &pll_param);
>  		if (ret != 0) {
>  			printf("Error:Can't find pll parameters: %d\n",
>  				ret);
>  			return ret;
>  		}
> -		switch ((__raw_readl(&mxc_ccm->cbcmr) & \
> -			MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> \
> -			MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
> +		switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(
> +				readl(&mxc_ccm->cbcmr))) {
>  		case 0:
>  			return config_pll_clk(PLL1_CLOCK, &pll_param);
>  			break;
> @@ -742,8 +690,7 @@ static int config_ddr_clk(u32 emi_clk)
>  {
>  	u32 clk_src;
>  	s32 shift = 0, clk_sel, div = 1;
> -	u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
> -	u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
> +	u32 cbcmr = readl(&mxc_ccm->cbcmr);
>  
>  	if (emi_clk > MAX_DDR_CLK) {
>  		printf("Warning:DDR clock should not exceed %d MHz\n",
> @@ -753,7 +700,7 @@ static int config_ddr_clk(u32 emi_clk)
>  
>  	clk_src = get_periph_clk();
>  	/* Find DDR clock input */
> -	clk_sel = (cbcmr >> 10) & 0x3;
> +	clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
>  	switch (clk_sel) {
>  	case 0:
>  		shift = 16;
> @@ -778,12 +725,10 @@ static int config_ddr_clk(u32 emi_clk)
>  	if (div > 8)
>  		div = 8;
>  
> -	cbcdr = cbcdr & ~(0x7 << shift);
> -	cbcdr |= ((div - 1) << shift);
> -	__raw_writel(cbcdr, &mxc_ccm->cbcdr);
> -	while (__raw_readl(&mxc_ccm->cdhipr) != 0)
> +	clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift);
> +	while (readl(&mxc_ccm->cdhipr) != 0)
>  		;
> -	__raw_writel(0x0, &mxc_ccm->ccdr);
> +	writel(0x0, &mxc_ccm->ccdr);
>  
>  	return 0;
>  }
> @@ -856,7 +801,7 @@ void mxc_set_sata_internal_clock(void)
>  
>  	set_usb_phy1_clk();
>  
> -	writel((readl(tmp_base) & (~0x6)) | 0x4, tmp_base);
> +	clrsetbits_le32(tmp_base, 0x6, 0x4);
>  }
>  #endif
>  
> diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/crm_regs.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/crm_regs.h
> index 4e0fc1b..ab0e818 100644
> --- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/crm_regs.h
> +++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/crm_regs.h
> @@ -85,115 +85,200 @@ struct mxc_ccm_reg {
>  /* Define the bits in register CACRR */
>  #define MXC_CCM_CACRR_ARM_PODF_OFFSET		0
>  #define MXC_CCM_CACRR_ARM_PODF_MASK		0x7
> +#define MXC_CCM_CACRR_ARM_PODF(v)		((v) & 0x7)
> +#define MXC_CCM_CACRR_ARM_PODF_RD(r)		((r) & 0x7)
>  
>  /* Define the bits in register CBCDR */
>  #define MXC_CCM_CBCDR_DDR_HIFREQ_SEL		(0x1 << 30)
> -#define MXC_CCM_CBCDR_DDR_PODF_MASK		(0x7 << 27)
>  #define MXC_CCM_CBCDR_DDR_PODF_OFFSET		27
> +#define MXC_CCM_CBCDR_DDR_PODF_MASK		(0x7 << 27)
> +#define MXC_CCM_CBCDR_DDR_PODF(v)		(((v) & 0x7) << 27)
> +#define MXC_CCM_CBCDR_DDR_PODF_RD(r)		(((r) >> 27) & 0x7)
>  #define MXC_CCM_CBCDR_EMI_CLK_SEL		(0x1 << 26)
>  #define MXC_CCM_CBCDR_PERIPH_CLK_SEL		(0x1 << 25)
>  #define MXC_CCM_CBCDR_EMI_PODF_OFFSET		22
>  #define MXC_CCM_CBCDR_EMI_PODF_MASK		(0x7 << 22)
> +#define MXC_CCM_CBCDR_EMI_PODF(v)		(((v) & 0x7) << 22)
> +#define MXC_CCM_CBCDR_EMI_PODF_RD(r)		(((r) >> 22) & 0x7)
>  #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET		19
>  #define MXC_CCM_CBCDR_AXI_B_PODF_MASK		(0x7 << 19)
> +#define MXC_CCM_CBCDR_AXI_B_PODF(v)		(((v) & 0x7) << 19)
> +#define MXC_CCM_CBCDR_AXI_B_PODF_RD(r)		(((r) >> 19) & 0x7)
>  #define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET		16
>  #define MXC_CCM_CBCDR_AXI_A_PODF_MASK		(0x7 << 16)
> +#define MXC_CCM_CBCDR_AXI_A_PODF(v)		(((v) & 0x7) << 16)
> +#define MXC_CCM_CBCDR_AXI_A_PODF_RD(r)		(((r) >> 16) & 0x7)
>  #define MXC_CCM_CBCDR_NFC_PODF_OFFSET		13
>  #define MXC_CCM_CBCDR_NFC_PODF_MASK		(0x7 << 13)
> +#define MXC_CCM_CBCDR_NFC_PODF(v)		(((v) & 0x7) << 13)
> +#define MXC_CCM_CBCDR_NFC_PODF_RD(r)		(((r) >> 13) & 0x7)
>  #define MXC_CCM_CBCDR_AHB_PODF_OFFSET		10
>  #define MXC_CCM_CBCDR_AHB_PODF_MASK		(0x7 << 10)
> +#define MXC_CCM_CBCDR_AHB_PODF(v)		(((v) & 0x7) << 10)
> +#define MXC_CCM_CBCDR_AHB_PODF_RD(r)		(((r) >> 10) & 0x7)
>  #define MXC_CCM_CBCDR_IPG_PODF_OFFSET		8
>  #define MXC_CCM_CBCDR_IPG_PODF_MASK		(0x3 << 8)
> +#define MXC_CCM_CBCDR_IPG_PODF(v)		(((v) & 0x3) << 8)
> +#define MXC_CCM_CBCDR_IPG_PODF_RD(r)		(((r) >> 8) & 0x3)
>  #define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET	6
>  #define MXC_CCM_CBCDR_PERCLK_PRED1_MASK		(0x3 << 6)
> +#define MXC_CCM_CBCDR_PERCLK_PRED1(v)		(((v) & 0x3) << 6)
> +#define MXC_CCM_CBCDR_PERCLK_PRED1_RD(r)	(((r) >> 6) & 0x3)
>  #define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET	3
>  #define MXC_CCM_CBCDR_PERCLK_PRED2_MASK		(0x7 << 3)
> +#define MXC_CCM_CBCDR_PERCLK_PRED2(v)		(((v) & 0x7) << 3)
> +#define MXC_CCM_CBCDR_PERCLK_PRED2_RD(r)	(((r) >> 3) & 0x7)
>  #define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET	0
>  #define MXC_CCM_CBCDR_PERCLK_PODF_MASK		0x7
> +#define MXC_CCM_CBCDR_PERCLK_PODF(v)		((v) & 0x7)
> +#define MXC_CCM_CBCDR_PERCLK_PODF_RD(r)		((r) & 0x7)
>  
>  /* Define the bits in register CSCMR1 */
>  #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET		30
>  #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK		(0x3 << 30)
> +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL(v)		(((v) & 0x3) << 30)
> +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_RD(r)		(((r) >> 30) & 0x3)
>  #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET		28
>  #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK		(0x3 << 28)
> -#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET		26
> +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL(v)		(((v) & 0x3) << 28)
> +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_RD(r)		(((r) >> 28) & 0x3)
>  #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL			(0x1 << 26)
>  #define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET		24
>  #define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK		(0x3 << 24)
> +#define MXC_CCM_CSCMR1_UART_CLK_SEL(v)			(((v) & 0x3) << 24)
> +#define MXC_CCM_CSCMR1_UART_CLK_SEL_RD(r)		(((r) >> 24) & 0x3)
>  #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET		22
>  #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK		(0x3 << 22)
> +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL(v)		(((v) & 0x3) << 22)
> +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_RD(r)		(((r) >> 22) & 0x3)
>  #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET	20
>  #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK	(0x3 << 20)
> +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL(v)		(((v) & 0x3) << 20)
> +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(r)	(((r) >> 20) & 0x3)
>  #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL			(0x1 << 19)
>  #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL			(0x1 << 18)
>  #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET	16
>  #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK	(0x3 << 16)
> +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL(v)		(((v) & 0x3) << 16)
> +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(r)	(((r) >> 16) & 0x3)
>  #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET		14
>  #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK		(0x3 << 14)
> +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL(v)			(((v) & 0x3) << 14)
> +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_RD(r)		(((r) >> 14) & 0x3)
>  #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET		12
>  #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK		(0x3 << 12)
> +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL(v)			(((v) & 0x3) << 12)
> +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_RD(r)		(((r) >> 12) & 0x3)
>  #define MXC_CCM_CSCMR1_SSI3_CLK_SEL			(0x1 << 11)
>  #define MXC_CCM_CSCMR1_VPU_RCLK_SEL			(0x1 << 10)
>  #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET		8
>  #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK		(0x3 << 8)
> +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL(v)		(((v) & 0x3) << 8)
> +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_RD(r)		(((r) >> 8) & 0x3)
>  #define MXC_CCM_CSCMR1_TVE_CLK_SEL			(0x1 << 7)
>  #define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL			(0x1 << 6)
>  #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET		4
>  #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK		(0x3 << 4)
> +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL(v)			(((v) & 0x3) << 4)
> +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(r)		(((r) >> 4) & 0x3)
>  #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET		2
>  #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK		(0x3 << 2)
> +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL(v)			(((v) & 0x3) << 2)
> +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_RD(r)		(((r) >> 2) & 0x3)
>  #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL		(0x1 << 1)
>  #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL		0x1
>  
>  /* Define the bits in register CSCDR2 */
>  #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET		25
>  #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK		(0x7 << 25)
> +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED(v)			(((v) & 0x7) << 25)
> +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(r)		(((r) >> 25) & 0x7)
>  #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET		19
>  #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK		(0x3F << 19)
> +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF(v)			(((v) & 0x3F) << 19)
> +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(r)		(((r) >> 19) & 0x3F)
>  #define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET		16
>  #define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK		(0x7 << 16)
> +#define MXC_CCM_CSCDR2_SIM_CLK_PRED(v)			(((v) & 0x7) << 16)
> +#define MXC_CCM_CSCDR2_SIM_CLK_PRED_RD(r)		(((r) >> 16) & 0x7)
>  #define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET		9
>  #define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK		(0x3F << 9)
> +#define MXC_CCM_CSCDR2_SIM_CLK_PODF(v)			(((v) & 0x3F) << 9)
> +#define MXC_CCM_CSCDR2_SIM_CLK_PODF_RD(r)		(((r) >> 9) & 0x3F)
>  #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET		6
> -#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK		(0x7 << 6)
> -#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET		0
> -#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK		0x3F
> +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_MASK		(0x7 << 6)
> +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED(v)		(((v) & 0x7) << 6)
> +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_RD(r)		(((r) >> 6) & 0x7)
> +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_OFFSET		0
> +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_MASK		0x3F
> +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF(v)		((v) & 0x3F)
> +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_RD(r)		((r) & 0x3F)
>  
>  /* Define the bits in register CBCMR */
>  #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET		14
>  #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK		(0x3 << 14)
> +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL(v)		(((v) & 0x3) << 14)
> +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_RD(r)		(((r) >> 14) & 0x3)
>  #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET		12
>  #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK		(0x3 << 12)
> +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL(v)			(((v) & 0x3) << 12)
> +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(r)		(((r) >> 12) & 0x3)
>  #define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET		10
>  #define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK			(0x3 << 10)
> +#define MXC_CCM_CBCMR_DDR_CLK_SEL(v)			(((v) & 0x3) << 10)
> +#define MXC_CCM_CBCMR_DDR_CLK_SEL_RD(r)			(((r) >> 10) & 0x3)
>  #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET		8
>  #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK		(0x3 << 8)
> +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL(v)		(((v) & 0x3) << 8)
> +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_RD(r)		(((r) >> 8) & 0x3)
>  #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET		6
>  #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK		(0x3 << 6)
> +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(v)		(((v) & 0x3) << 6)
> +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_RD(r)		(((r) >> 6) & 0x3)
>  #define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET		4
>  #define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK			(0x3 << 4)
> +#define MXC_CCM_CBCMR_GPU_CLK_SEL(v)			(((v) & 0x3) << 4)
> +#define MXC_CCM_CBCMR_GPU_CLK_SEL_RD(r)			(((r) >> 4) & 0x3)
>  #define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL		(0x1 << 1)
>  #define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL		(0x1 << 0)
>  
>  /* Define the bits in register CSCDR1 */
>  #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET	22
>  #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK	(0x7 << 22)
> +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED(v)		(((v) & 0x7) << 22)
> +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(r)	(((r) >> 22) & 0x7)
>  #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET	19
>  #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK	(0x7 << 19)
> +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF(v)		(((v) & 0x7) << 19)
> +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(r)	(((r) >> 19) & 0x7)
>  #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET	16
>  #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK	(0x7 << 16)
> +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED(v)		(((v) & 0x7) << 16)
> +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(r)	(((r) >> 16) & 0x7)
>  #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET		14
>  #define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK		(0x3 << 14)
> +#define MXC_CCM_CSCDR1_PGC_CLK_PODF(v)			(((v) & 0x3) << 14)
> +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_RD(r)		(((r) >> 14) & 0x3)
>  #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET	11
>  #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK	(0x7 << 11)
> +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF(v)		(((v) & 0x7) << 11)
> +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(r)	(((r) >> 11) & 0x7)
>  #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET		8
>  #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK		(0x7 << 8)
> +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED(v)		(((v) & 0x7) << 8)
> +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_RD(r)		(((r) >> 8) & 0x7)
>  #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		6
>  #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
> +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF(v)		(((v) & 0x3) << 6)
> +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_RD(r)		(((r) >> 6) & 0x3)
>  #define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET		3
>  #define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK		(0x7 << 3)
> +#define MXC_CCM_CSCDR1_UART_CLK_PRED(v)			(((v) & 0x7) << 3)
> +#define MXC_CCM_CSCDR1_UART_CLK_PRED_RD(r)		(((r) >> 3) & 0x7)
>  #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		0
>  #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x7
> +#define MXC_CCM_CSCDR1_UART_CLK_PODF(v)			((v) & 0x7)
> +#define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r)		((r) & 0x7)
>  
>  /* Define the bits in register CCDR */
>  #define MXC_CCM_CCDR_IPU_HS_MASK			(0x1 << 17)
> @@ -213,8 +298,10 @@ struct mxc_ccm_reg {
>  #define	MXC_DPLLC_CTL_DPDCK0_2_EN			(1 << 12)
>  
>  #define	MXC_DPLLC_OP_PDF_MASK				0xf
> -#define	MXC_DPLLC_OP_MFI_MASK				(0xf << 4)
>  #define	MXC_DPLLC_OP_MFI_OFFSET				4
> +#define	MXC_DPLLC_OP_MFI_MASK				(0xf << 4)
> +#define	MXC_DPLLC_OP_MFI(v)				(((v) & 0xf) << 4)
> +#define	MXC_DPLLC_OP_MFI_RD(r)				(((r) >> 4) & 0xf)
>  
>  #define	MXC_DPLLC_MFD_MFD_MASK				0x7ffffff
>  
> 

Acked-by: Stefano Babic <sbabic@denx.de>

Best regards,
Stefano Babic

-- 
=====================================================================
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Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 03/14] mx5: Use explicit clock gate names

[Stefano Babic]

On 27/09/2012 22:21, Beno?t Th?baudeau wrote:
> Use clock gate definitions having names showing clearly the gated clock instead
> of names giving only a register field index.
> 
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> This change reveals (clock.c won't build) that the USB PHY clock functions were
> broken on i.MX51, which is fixed by the following 2 patches.
> 
> This patch supersedes http://patchwork.ozlabs.org/patch/177403/ .
> Changes for v2:
>  - Split patch into 3 parts (the 3, 4 and 5 from this v2 series).
>  - Use the created definitions for enable_i2c_clk().
> 
>  .../arch/arm/cpu/armv7/mx5/clock.c                 |   15 +-
>  .../arch/arm/include/asm/arch-mx5/crm_regs.h       |  279 +++++++++++++++++++-
>  .../drivers/video/ipu_common.c                     |    2 +-
>  3 files changed, 284 insertions(+), 12 deletions(-)
> 
> diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
> index 5fca775..32a69d4 100644
> --- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
> +++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
> @@ -102,9 +102,9 @@ void set_usboh3_clk(void)
>  void enable_usboh3_clk(unsigned char enable)
>  {
>  	if (enable)
> -		setbits_le32(&mxc_ccm->CCGR2, 1 << MXC_CCM_CCGR2_CG14_OFFSET);
> +		setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_USBOH3_60M(1));
>  	else
> -		clrbits_le32(&mxc_ccm->CCGR2, 1 << MXC_CCM_CCGR2_CG14_OFFSET);
> +		clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_USBOH3_60M(1));
>  }
>  
>  #ifdef CONFIG_I2C_MXC
> @@ -115,7 +115,8 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
>  
>  	if (i2c_num > 2)
>  		return -EINVAL;
> -	mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 9) << 1);
> +	mask = MXC_CCM_CCGR_CG_MASK <<
> +			(MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));

I admit the code in your patch is straightforward and easy to understand
with the manual - thanks for this cleanup !


>  	if (enable)
>  		setbits_le32(&mxc_ccm->CCGR1, mask);
>  	else
> @@ -132,9 +133,9 @@ void set_usb_phy1_clk(void)
>  void enable_usb_phy1_clk(unsigned char enable)
>  {
>  	if (enable)
> -		setbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG5_OFFSET);
> +		setbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY1(1));
>  	else
> -		clrbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG5_OFFSET);
> +		clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY1(1));
>  }
>  
>  void set_usb_phy2_clk(void)
> @@ -145,9 +146,9 @@ void set_usb_phy2_clk(void)
>  void enable_usb_phy2_clk(unsigned char enable)
>  {
>  	if (enable)
> -		setbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG6_OFFSET);
> +		setbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY2(1));
>  	else
> -		clrbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG6_OFFSET);
> +		clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY2(1));
>  }
>  
>  /*
> diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/crm_regs.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/crm_regs.h
> index ab0e818..d5eb303 100644
> --- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/crm_regs.h
> +++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/crm_regs.h
> @@ -286,10 +286,281 @@ struct mxc_ccm_reg {
>  /* Define the bits in register CCGRx */
>  #define MXC_CCM_CCGR_CG_MASK				0x3
>  
> -#define MXC_CCM_CCGR4_CG5_OFFSET			10
> -#define MXC_CCM_CCGR4_CG6_OFFSET			12
> -#define MXC_CCM_CCGR5_CG5_OFFSET			10
> -#define MXC_CCM_CCGR2_CG14_OFFSET			28
> +#define MXC_CCM_CCGR0_ARM_BUS_OFFSET			0
> +#define MXC_CCM_CCGR0_ARM_BUS(v)			(((v) & 0x3) << 0)
> +#define MXC_CCM_CCGR0_ARM_AXI_OFFSET			2
> +#define MXC_CCM_CCGR0_ARM_AXI(v)			(((v) & 0x3) << 2)
> +#define MXC_CCM_CCGR0_ARM_DEBUG_OFFSET			4
> +#define MXC_CCM_CCGR0_ARM_DEBUG(v)			(((v) & 0x3) << 4)
> +#define MXC_CCM_CCGR0_TZIC_OFFSET			6
> +#define MXC_CCM_CCGR0_TZIC(v)				(((v) & 0x3) << 6)
> +#define MXC_CCM_CCGR0_DAP_OFFSET			8
> +#define MXC_CCM_CCGR0_DAP(v)				(((v) & 0x3) << 8)
> +#define MXC_CCM_CCGR0_TPIU_OFFSET			10
> +#define MXC_CCM_CCGR0_TPIU(v)				(((v) & 0x3) << 10)
> +#define MXC_CCM_CCGR0_CTI2_OFFSET			12
> +#define MXC_CCM_CCGR0_CTI2(v)				(((v) & 0x3) << 12)
> +#define MXC_CCM_CCGR0_CTI3_OFFSET			14
> +#define MXC_CCM_CCGR0_CTI3(v)				(((v) & 0x3) << 14)
> +#define MXC_CCM_CCGR0_AHBMUX1_OFFSET			16
> +#define MXC_CCM_CCGR0_AHBMUX1(v)			(((v) & 0x3) << 16)
> +#define MXC_CCM_CCGR0_AHBMUX2_OFFSET			18
> +#define MXC_CCM_CCGR0_AHBMUX2(v)			(((v) & 0x3) << 18)
> +#define MXC_CCM_CCGR0_ROMCP_OFFSET			20
> +#define MXC_CCM_CCGR0_ROMCP(v)				(((v) & 0x3) << 20)
> +#define MXC_CCM_CCGR0_ROM_OFFSET			22
> +#define MXC_CCM_CCGR0_ROM(v)				(((v) & 0x3) << 22)
> +#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET			24
> +#define MXC_CCM_CCGR0_AIPS_TZ1(v)			(((v) & 0x3) << 24)
> +#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET			26
> +#define MXC_CCM_CCGR0_AIPS_TZ2(v)			(((v) & 0x3) << 26)
> +#define MXC_CCM_CCGR0_AHB_MAX_OFFSET			28
> +#define MXC_CCM_CCGR0_AHB_MAX(v)			(((v) & 0x3) << 28)
> +#define MXC_CCM_CCGR0_IIM_OFFSET			30
> +#define MXC_CCM_CCGR0_IIM(v)				(((v) & 0x3) << 30)
> +
> +#define MXC_CCM_CCGR1_TMAX1_OFFSET			0
> +#define MXC_CCM_CCGR1_TMAX1(v)				(((v) & 0x3) << 0)
> +#define MXC_CCM_CCGR1_TMAX2_OFFSET			2
> +#define MXC_CCM_CCGR1_TMAX2(v)				(((v) & 0x3) << 2)
> +#define MXC_CCM_CCGR1_TMAX3_OFFSET			4
> +#define MXC_CCM_CCGR1_TMAX3(v)				(((v) & 0x3) << 4)
> +#define MXC_CCM_CCGR1_UART1_IPG_OFFSET			6
> +#define MXC_CCM_CCGR1_UART1_IPG(v)			(((v) & 0x3) << 6)
> +#define MXC_CCM_CCGR1_UART1_PER_OFFSET			8
> +#define MXC_CCM_CCGR1_UART1_PER(v)			(((v) & 0x3) << 8)
> +#define MXC_CCM_CCGR1_UART2_IPG_OFFSET			10
> +#define MXC_CCM_CCGR1_UART2_IPG(v)			(((v) & 0x3) << 10)
> +#define MXC_CCM_CCGR1_UART2_PER_OFFSET			12
> +#define MXC_CCM_CCGR1_UART2_PER(v)			(((v) & 0x3) << 12)
> +#define MXC_CCM_CCGR1_UART3_IPG_OFFSET			14
> +#define MXC_CCM_CCGR1_UART3_IPG(v)			(((v) & 0x3) << 14)
> +#define MXC_CCM_CCGR1_UART3_PER_OFFSET			16
> +#define MXC_CCM_CCGR1_UART3_PER(v)			(((v) & 0x3) << 16)
> +#define MXC_CCM_CCGR1_I2C1_OFFSET			18
> +#define MXC_CCM_CCGR1_I2C1(v)				(((v) & 0x3) << 18)
> +#define MXC_CCM_CCGR1_I2C2_OFFSET			20
> +#define MXC_CCM_CCGR1_I2C2(v)				(((v) & 0x3) << 20)
> +#if defined(CONFIG_MX51)
> +#define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET			22
> +#define MXC_CCM_CCGR1_HSI2C_IPG(v)			(((v) & 0x3) << 22)
> +#define MXC_CCM_CCGR1_HSI2C_SERIAL_OFFSET		24
> +#define MXC_CCM_CCGR1_HSI2C_SERIAL(v)			(((v) & 0x3) << 24)
> +#elif defined(CONFIG_MX53)
> +#define MXC_CCM_CCGR1_I2C3_OFFSET			22
> +#define MXC_CCM_CCGR1_I2C3(v)				(((v) & 0x3) << 22)
> +#endif
> +#define MXC_CCM_CCGR1_FIRI_IPG_OFFSET			26
> +#define MXC_CCM_CCGR1_FIRI_IPG(v)			(((v) & 0x3) << 26)
> +#define MXC_CCM_CCGR1_FIRI_SERIAL_OFFSET		28
> +#define MXC_CCM_CCGR1_FIRI_SERIAL(v)			(((v) & 0x3) << 28)
> +#define MXC_CCM_CCGR1_SCC_OFFSET			30
> +#define MXC_CCM_CCGR1_SCC(v)				(((v) & 0x3) << 30)
> +
> +#if defined(CONFIG_MX51)
> +#define MXC_CCM_CCGR2_USB_PHY_OFFSET			0
> +#define MXC_CCM_CCGR2_USB_PHY(v)			(((v) & 0x3) << 0)
> +#endif
> +#define MXC_CCM_CCGR2_EPIT1_IPG_OFFSET			2
> +#define MXC_CCM_CCGR2_EPIT1_IPG(v)			(((v) & 0x3) << 2)
> +#define MXC_CCM_CCGR2_EPIT1_HF_OFFSET			4
> +#define MXC_CCM_CCGR2_EPIT1_HF(v)			(((v) & 0x3) << 4)
> +#define MXC_CCM_CCGR2_EPIT2_IPG_OFFSET			6
> +#define MXC_CCM_CCGR2_EPIT2_IPG(v)			(((v) & 0x3) << 6)
> +#define MXC_CCM_CCGR2_EPIT2_HF_OFFSET			8
> +#define MXC_CCM_CCGR2_EPIT2_HF(v)			(((v) & 0x3) << 8)
> +#define MXC_CCM_CCGR2_PWM1_IPG_OFFSET			10
> +#define MXC_CCM_CCGR2_PWM1_IPG(v)			(((v) & 0x3) << 10)
> +#define MXC_CCM_CCGR2_PWM1_HF_OFFSET			12
> +#define MXC_CCM_CCGR2_PWM1_HF(v)			(((v) & 0x3) << 12)
> +#define MXC_CCM_CCGR2_PWM2_IPG_OFFSET			14
> +#define MXC_CCM_CCGR2_PWM2_IPG(v)			(((v) & 0x3) << 14)
> +#define MXC_CCM_CCGR2_PWM2_HF_OFFSET			16
> +#define MXC_CCM_CCGR2_PWM2_HF(v)			(((v) & 0x3) << 16)
> +#define MXC_CCM_CCGR2_GPT_IPG_OFFSET			18
> +#define MXC_CCM_CCGR2_GPT_IPG(v)			(((v) & 0x3) << 18)
> +#define MXC_CCM_CCGR2_GPT_HF_OFFSET			20
> +#define MXC_CCM_CCGR2_GPT_HF(v)				(((v) & 0x3) << 20)
> +#define MXC_CCM_CCGR2_OWIRE_OFFSET			22
> +#define MXC_CCM_CCGR2_OWIRE(v)				(((v) & 0x3) << 22)
> +#define MXC_CCM_CCGR2_FEC_OFFSET			24
> +#define MXC_CCM_CCGR2_FEC(v)				(((v) & 0x3) << 24)
> +#define MXC_CCM_CCGR2_USBOH3_IPG_AHB_OFFSET		26
> +#define MXC_CCM_CCGR2_USBOH3_IPG_AHB(v)			(((v) & 0x3) << 26)
> +#define MXC_CCM_CCGR2_USBOH3_60M_OFFSET			28
> +#define MXC_CCM_CCGR2_USBOH3_60M(v)			(((v) & 0x3) << 28)
> +#define MXC_CCM_CCGR2_TVE_OFFSET			30
> +#define MXC_CCM_CCGR2_TVE(v)				(((v) & 0x3) << 30)
> +
> +#define MXC_CCM_CCGR3_ESDHC1_IPG_OFFSET			0
> +#define MXC_CCM_CCGR3_ESDHC1_IPG(v)			(((v) & 0x3) << 0)
> +#define MXC_CCM_CCGR3_ESDHC1_PER_OFFSET			2
> +#define MXC_CCM_CCGR3_ESDHC1_PER(v)			(((v) & 0x3) << 2)
> +#define MXC_CCM_CCGR3_ESDHC2_IPG_OFFSET			4
> +#define MXC_CCM_CCGR3_ESDHC2_IPG(v)			(((v) & 0x3) << 4)
> +#define MXC_CCM_CCGR3_ESDHC2_PER_OFFSET			6
> +#define MXC_CCM_CCGR3_ESDHC2_PER(v)			(((v) & 0x3) << 6)
> +#define MXC_CCM_CCGR3_ESDHC3_IPG_OFFSET			8
> +#define MXC_CCM_CCGR3_ESDHC3_IPG(v)			(((v) & 0x3) << 8)
> +#define MXC_CCM_CCGR3_ESDHC3_PER_OFFSET			10
> +#define MXC_CCM_CCGR3_ESDHC3_PER(v)			(((v) & 0x3) << 10)
> +#define MXC_CCM_CCGR3_ESDHC4_IPG_OFFSET			12
> +#define MXC_CCM_CCGR3_ESDHC4_IPG(v)			(((v) & 0x3) << 12)
> +#define MXC_CCM_CCGR3_ESDHC4_PER_OFFSET			14
> +#define MXC_CCM_CCGR3_ESDHC4_PER(v)			(((v) & 0x3) << 14)
> +#define MXC_CCM_CCGR3_SSI1_IPG_OFFSET			16
> +#define MXC_CCM_CCGR3_SSI1_IPG(v)			(((v) & 0x3) << 16)
> +#define MXC_CCM_CCGR3_SSI1_SSI_OFFSET			18
> +#define MXC_CCM_CCGR3_SSI1_SSI(v)			(((v) & 0x3) << 18)
> +#define MXC_CCM_CCGR3_SSI2_IPG_OFFSET			20
> +#define MXC_CCM_CCGR3_SSI2_IPG(v)			(((v) & 0x3) << 20)
> +#define MXC_CCM_CCGR3_SSI2_SSI_OFFSET			22
> +#define MXC_CCM_CCGR3_SSI2_SSI(v)			(((v) & 0x3) << 22)
> +#define MXC_CCM_CCGR3_SSI3_IPG_OFFSET			24
> +#define MXC_CCM_CCGR3_SSI3_IPG(v)			(((v) & 0x3) << 24)
> +#define MXC_CCM_CCGR3_SSI3_SSI_OFFSET			26
> +#define MXC_CCM_CCGR3_SSI3_SSI(v)			(((v) & 0x3) << 26)
> +#define MXC_CCM_CCGR3_SSI_EXT1_OFFSET			28
> +#define MXC_CCM_CCGR3_SSI_EXT1(v)			(((v) & 0x3) << 28)
> +#define MXC_CCM_CCGR3_SSI_EXT2_OFFSET			30
> +#define MXC_CCM_CCGR3_SSI_EXT2(v)			(((v) & 0x3) << 30)
> +
> +#define MXC_CCM_CCGR4_PATA_OFFSET			0
> +#define MXC_CCM_CCGR4_PATA(v)				(((v) & 0x3) << 0)
> +#if defined(CONFIG_MX51)
> +#define MXC_CCM_CCGR4_SIM_IPG_OFFSET			2
> +#define MXC_CCM_CCGR4_SIM_IPG(v)			(((v) & 0x3) << 2)
> +#define MXC_CCM_CCGR4_SIM_SERIAL_OFFSET			4
> +#define MXC_CCM_CCGR4_SIM_SERIAL(v)			(((v) & 0x3) << 4)
> +#elif defined(CONFIG_MX53)
> +#define MXC_CCM_CCGR4_SATA_OFFSET			2
> +#define MXC_CCM_CCGR4_SATA(v)				(((v) & 0x3) << 2)
> +#define MXC_CCM_CCGR4_CAN2_IPG_OFFSET			6
> +#define MXC_CCM_CCGR4_CAN2_IPG(v)			(((v) & 0x3) << 6)
> +#define MXC_CCM_CCGR4_CAN2_SERIAL_OFFSET		8
> +#define MXC_CCM_CCGR4_CAN2_SERIAL(v)			(((v) & 0x3) << 8)
> +#define MXC_CCM_CCGR4_USB_PHY1_OFFSET			10
> +#define MXC_CCM_CCGR4_USB_PHY1(v)			(((v) & 0x3) << 10)
> +#define MXC_CCM_CCGR4_USB_PHY2_OFFSET			12
> +#define MXC_CCM_CCGR4_USB_PHY2(v)			(((v) & 0x3) << 12)
> +#endif
> +#define MXC_CCM_CCGR4_SAHARA_OFFSET			14
> +#define MXC_CCM_CCGR4_SAHARA(v)				(((v) & 0x3) << 14)
> +#define MXC_CCM_CCGR4_RTIC_OFFSET			16
> +#define MXC_CCM_CCGR4_RTIC(v)				(((v) & 0x3) << 16)
> +#define MXC_CCM_CCGR4_ECSPI1_IPG_OFFSET			18
> +#define MXC_CCM_CCGR4_ECSPI1_IPG(v)			(((v) & 0x3) << 18)
> +#define MXC_CCM_CCGR4_ECSPI1_PER_OFFSET			20
> +#define MXC_CCM_CCGR4_ECSPI1_PER(v)			(((v) & 0x3) << 20)
> +#define MXC_CCM_CCGR4_ECSPI2_IPG_OFFSET			22
> +#define MXC_CCM_CCGR4_ECSPI2_IPG(v)			(((v) & 0x3) << 22)
> +#define MXC_CCM_CCGR4_ECSPI2_PER_OFFSET			24
> +#define MXC_CCM_CCGR4_ECSPI2_PER(v)			(((v) & 0x3) << 24)
> +#define MXC_CCM_CCGR4_CSPI_IPG_OFFSET			26
> +#define MXC_CCM_CCGR4_CSPI_IPG(v)			(((v) & 0x3) << 26)
> +#define MXC_CCM_CCGR4_SRTC_OFFSET			28
> +#define MXC_CCM_CCGR4_SRTC(v)				(((v) & 0x3) << 28)
> +#define MXC_CCM_CCGR4_SDMA_OFFSET			30
> +#define MXC_CCM_CCGR4_SDMA(v)				(((v) & 0x3) << 30)
> +
> +#define MXC_CCM_CCGR5_SPBA_OFFSET			0
> +#define MXC_CCM_CCGR5_SPBA(v)				(((v) & 0x3) << 0)
> +#define MXC_CCM_CCGR5_GPU_OFFSET			2
> +#define MXC_CCM_CCGR5_GPU(v)				(((v) & 0x3) << 2)
> +#define MXC_CCM_CCGR5_GARB_OFFSET			4
> +#define MXC_CCM_CCGR5_GARB(v)				(((v) & 0x3) << 4)
> +#define MXC_CCM_CCGR5_VPU_OFFSET			6
> +#define MXC_CCM_CCGR5_VPU(v)				(((v) & 0x3) << 6)
> +#define MXC_CCM_CCGR5_VPU_REF_OFFSET			8
> +#define MXC_CCM_CCGR5_VPU_REF(v)			(((v) & 0x3) << 8)
> +#define MXC_CCM_CCGR5_IPU_OFFSET			10
> +#define MXC_CCM_CCGR5_IPU(v)				(((v) & 0x3) << 10)
> +#if defined(CONFIG_MX51)
> +#define MXC_CCM_CCGR5_IPUMUX12_OFFSET			12
> +#define MXC_CCM_CCGR5_IPUMUX12(v)			(((v) & 0x3) << 12)
> +#elif defined(CONFIG_MX53)
> +#define MXC_CCM_CCGR5_IPUMUX1_OFFSET			12
> +#define MXC_CCM_CCGR5_IPUMUX1(v)			(((v) & 0x3) << 12)
> +#endif
> +#define MXC_CCM_CCGR5_EMI_FAST_OFFSET			14
> +#define MXC_CCM_CCGR5_EMI_FAST(v)			(((v) & 0x3) << 14)
> +#define MXC_CCM_CCGR5_EMI_SLOW_OFFSET			16
> +#define MXC_CCM_CCGR5_EMI_SLOW(v)			(((v) & 0x3) << 16)
> +#define MXC_CCM_CCGR5_EMI_INT1_OFFSET			18
> +#define MXC_CCM_CCGR5_EMI_INT1(v)			(((v) & 0x3) << 18)
> +#define MXC_CCM_CCGR5_EMI_ENFC_OFFSET			20
> +#define MXC_CCM_CCGR5_EMI_ENFC(v)			(((v) & 0x3) << 20)
> +#define MXC_CCM_CCGR5_EMI_WRCK_OFFSET			22
> +#define MXC_CCM_CCGR5_EMI_WRCK(v)			(((v) & 0x3) << 22)
> +#define MXC_CCM_CCGR5_GPC_IPG_OFFSET			24
> +#define MXC_CCM_CCGR5_GPC_IPG(v)			(((v) & 0x3) << 24)
> +#define MXC_CCM_CCGR5_SPDIF0_OFFSET			26
> +#define MXC_CCM_CCGR5_SPDIF0(v)				(((v) & 0x3) << 26)
> +#if defined(CONFIG_MX51)
> +#define MXC_CCM_CCGR5_SPDIF1_OFFSET			28
> +#define MXC_CCM_CCGR5_SPDIF1(v)				(((v) & 0x3) << 28)
> +#endif
> +#define MXC_CCM_CCGR5_SPDIF_IPG_OFFSET			30
> +#define MXC_CCM_CCGR5_SPDIF_IPG(v)			(((v) & 0x3) << 30)
> +
> +#if defined(CONFIG_MX53)
> +#define MXC_CCM_CCGR6_IPUMUX2_OFFSET			0
> +#define MXC_CCM_CCGR6_IPUMUX2(v)			(((v) & 0x3) << 0)
> +#define MXC_CCM_CCGR6_OCRAM_OFFSET			2
> +#define MXC_CCM_CCGR6_OCRAM(v)				(((v) & 0x3) << 2)
> +#endif
> +#define MXC_CCM_CCGR6_CSI_MCLK1_OFFSET			4
> +#define MXC_CCM_CCGR6_CSI_MCLK1(v)			(((v) & 0x3) << 4)
> +#if defined(CONFIG_MX51)
> +#define MXC_CCM_CCGR6_CSI_MCLK2_OFFSET			6
> +#define MXC_CCM_CCGR6_CSI_MCLK2(v)			(((v) & 0x3) << 6)
> +#define MXC_CCM_CCGR6_EMI_GARB_OFFSET			8
> +#define MXC_CCM_CCGR6_EMI_GARB(v)			(((v) & 0x3) << 8)
> +#elif defined(CONFIG_MX53)
> +#define MXC_CCM_CCGR6_EMI_INT2_OFFSET			8
> +#define MXC_CCM_CCGR6_EMI_INT2(v)			(((v) & 0x3) << 8)
> +#endif
> +#define MXC_CCM_CCGR6_IPU_DI0_OFFSET			10
> +#define MXC_CCM_CCGR6_IPU_DI0(v)			(((v) & 0x3) << 10)
> +#define MXC_CCM_CCGR6_IPU_DI1_OFFSET			12
> +#define MXC_CCM_CCGR6_IPU_DI1(v)			(((v) & 0x3) << 12)
> +#define MXC_CCM_CCGR6_GPU2D_OFFSET			14
> +#define MXC_CCM_CCGR6_GPU2D(v)				(((v) & 0x3) << 14)
> +#if defined(CONFIG_MX53)
> +#define MXC_CCM_CCGR6_ESAI_IPG_OFFSET			16
> +#define MXC_CCM_CCGR6_ESAI_IPG(v)			(((v) & 0x3) << 16)
> +#define MXC_CCM_CCGR6_ESAI_ROOT_OFFSET			18
> +#define MXC_CCM_CCGR6_ESAI_ROOT(v)			(((v) & 0x3) << 18)
> +#define MXC_CCM_CCGR6_CAN1_IPG_OFFSET			20
> +#define MXC_CCM_CCGR6_CAN1_IPG(v)			(((v) & 0x3) << 20)
> +#define MXC_CCM_CCGR6_CAN1_SERIAL_OFFSET		22
> +#define MXC_CCM_CCGR6_CAN1_SERIAL(v)			(((v) & 0x3) << 22)
> +#define MXC_CCM_CCGR6_PL301_4X1_OFFSET			24
> +#define MXC_CCM_CCGR6_PL301_4X1(v)			(((v) & 0x3) << 24)
> +#define MXC_CCM_CCGR6_PL301_2X2_OFFSET			26
> +#define MXC_CCM_CCGR6_PL301_2X2(v)			(((v) & 0x3) << 26)
> +#define MXC_CCM_CCGR6_LDB_DI0_OFFSET			28
> +#define MXC_CCM_CCGR6_LDB_DI0(v)			(((v) & 0x3) << 28)
> +#define MXC_CCM_CCGR6_LDB_DI1_OFFSET			30
> +#define MXC_CCM_CCGR6_LDB_DI1(v)			(((v) & 0x3) << 30)
> +
> +#define MXC_CCM_CCGR7_ASRC_IPG_OFFSET			0
> +#define MXC_CCM_CCGR7_ASRC_IPG(v)			(((v) & 0x3) << 0)
> +#define MXC_CCM_CCGR7_ASRC_ASRCK_OFFSET			2
> +#define MXC_CCM_CCGR7_ASRC_ASRCK(v)			(((v) & 0x3) << 2)
> +#define MXC_CCM_CCGR7_MLB_OFFSET			4
> +#define MXC_CCM_CCGR7_MLB(v)				(((v) & 0x3) << 4)
> +#define MXC_CCM_CCGR7_IEEE1588_OFFSET			6
> +#define MXC_CCM_CCGR7_IEEE1588(v)			(((v) & 0x3) << 6)
> +#define MXC_CCM_CCGR7_UART4_IPG_OFFSET			8
> +#define MXC_CCM_CCGR7_UART4_IPG(v)			(((v) & 0x3) << 8)
> +#define MXC_CCM_CCGR7_UART4_PER_OFFSET			10
> +#define MXC_CCM_CCGR7_UART4_PER(v)			(((v) & 0x3) << 10)
> +#define MXC_CCM_CCGR7_UART5_IPG_OFFSET			12
> +#define MXC_CCM_CCGR7_UART5_IPG(v)			(((v) & 0x3) << 12)
> +#define MXC_CCM_CCGR7_UART5_PER_OFFSET			14
> +#define MXC_CCM_CCGR7_UART5_PER(v)			(((v) & 0x3) << 14)
> +#endif
>  
>  /* Define the bits in register CLPCR */
>  #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS                 (0x1 << 18)
> diff --git u-boot-imx-e1eb75b.orig/drivers/video/ipu_common.c u-boot-imx-e1eb75b/drivers/video/ipu_common.c
> index 2020da9..7869d65 100644
> --- u-boot-imx-e1eb75b.orig/drivers/video/ipu_common.c
> +++ u-boot-imx-e1eb75b/drivers/video/ipu_common.c
> @@ -213,7 +213,7 @@ static struct clk ipu_clk = {
>  	.rate = CONFIG_IPUV3_CLK,
>  	.enable_reg = (u32 *)(CCM_BASE_ADDR +
>  		offsetof(struct mxc_ccm_reg, CCGR5)),
> -	.enable_shift = MXC_CCM_CCGR5_CG5_OFFSET,
> +	.enable_shift = MXC_CCM_CCGR5_IPU_OFFSET,
>  	.enable = clk_ipu_enable,
>  	.disable = clk_ipu_disable,
>  	.usecount = 0,
> 

Acked-by: Stefano Babic <sbabic@denx.de>

Best regards,
Stefano Babic


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 09/14] mx5 clocks: Fix get_ipg_per_clk()

[Stefano Babic]

On 27/09/2012 22:23, Beno?t Th?baudeau wrote:
> This fixes the "IPG PERCLK" frequency printed by the clocks command. The issue
> was that get_ipg_per_clk() used periph_clk instead of lp_apm in the case
> CCM.CBCMR.perclk_lp_apm_sel is set.
> 
> It also fixes I?C support.
> 

Hi Beno?t,

I understand "clocks" reports a wrong value only if
CCM.CBCMR.perclk_lp_apm_sel is set, not always.

Can you better explain me which is wrong and which is the fix for I2C ?
It seems unrelated, and I do not get the reason checking the patch

Thanks,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 05/14] mx51: Fix USB PHY clocks

[Benoît Thébaudeau]

Hi Igor,

On Friday, September 28, 2012 9:26:38 AM, Igor Grinberg wrote:
> Hi Beno?t,
> 
> please, see a minor #ifdef comment below
> 
> On 09/27/12 22:21, Beno?t Th?baudeau wrote:
> > The i.MX51 has a single USB PHY clock, while the i.MX53 has two.
> > These 3 clocks
> > have different clock gate control bit-fields.
> > 
> > The existing code was correct only for i.MX53, so this patch fixes
> > the i.MX51
> > use case.
> > 
> > Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> > Cc: Stefano Babic <sbabic@denx.de>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Jana Rapava <fermata7@gmail.com>
> > Cc: Wolfgang Grandegger <wg@denx.de>
> > Cc: Igor Grinberg <grinberg@compulab.co.il>
> > ---
> > This patch supersedes http://patchwork.ozlabs.org/patch/177403/ .
> > Changes for v2:
> >  - Split patch into 3 parts (the 3, 4 and 5 from this v2 series).
> >  - Merge the various set_usb_phy*_clk() functions (they were
> >  identical).
> > 
> >  .../arch/arm/cpu/armv7/mx5/clock.c                 |   20
> >  +++++++++++++-------
> >  .../arch/arm/include/asm/arch-mx5/clock.h          |    7 ++++++-
> >  .../drivers/usb/host/ehci-mx5.c                    |    6 +++++-
> >  3 files changed, 24 insertions(+), 9 deletions(-)
> > 
> > diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
> > u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
> > index df7e5cd..f727cfa 100644
> > --- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
> > +++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
> > @@ -126,11 +126,21 @@ int enable_i2c_clk(unsigned char enable,
> > unsigned i2c_num)
> >  }
> >  #endif
> >  
> > -void set_usb_phy1_clk(void)
> > +void set_usb_phy_clk(void)
> >  {
> >  	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
> >  }
> >  
> > +#if defined(CONFIG_MX51)
> > +void enable_usb_phy_clk(unsigned char enable)
> 
> I think the same name as the MX53 case will do better, see
> explanation below.
> 
> > +{
> > +	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON :
> > MXC_CCM_CCGR_CG_OFF;
> > +
> > +	clrsetbits_le32(&mxc_ccm->CCGR2,
> > +			MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
> > +			MXC_CCM_CCGR2_USB_PHY(cg));
> > +}
> 
> I would add here (again explanation below):
> void enable_usb_phy2_clk(unsigned char enable)
> {
> 	/* MX51 has a single USB PHY clock, so do nothing here */
> }
> 
> > +#elif defined(CONFIG_MX53)
> >  void enable_usb_phy1_clk(unsigned char enable)
> >  {
> >  	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON :
> >  	MXC_CCM_CCGR_CG_OFF;
> > @@ -140,11 +150,6 @@ void enable_usb_phy1_clk(unsigned char enable)
> >  			MXC_CCM_CCGR4_USB_PHY1(cg));
> >  }
> >  
> > -void set_usb_phy2_clk(void)
> > -{
> > -	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
> > -}
> > -
> >  void enable_usb_phy2_clk(unsigned char enable)
> >  {
> >  	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON :
> >  	MXC_CCM_CCGR_CG_OFF;
> > @@ -153,6 +158,7 @@ void enable_usb_phy2_clk(unsigned char enable)
> >  			MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
> >  			MXC_CCM_CCGR4_USB_PHY2(cg));
> >  }
> > +#endif
> >  
> >  /*
> >   * Calculate the frequency of PLLn.
> > @@ -803,7 +809,7 @@ void mxc_set_sata_internal_clock(void)
> >  	u32 *tmp_base =
> >  		(u32 *)(IIM_BASE_ADDR + 0x180c);
> >  
> > -	set_usb_phy1_clk();
> > +	set_usb_phy_clk();
> >  
> >  	clrsetbits_le32(tmp_base, 0x6, 0x4);
> >  }
> > diff --git
> > u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/clock.h
> > u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/clock.h
> > index 55e3b51..e4ca417 100644
> > --- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/clock.h
> > +++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/clock.h
> > @@ -56,8 +56,13 @@ u32 imx_get_uartclk(void);
> >  u32 imx_get_fecclk(void);
> >  unsigned int mxc_get_clock(enum mxc_clock clk);
> >  int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
> > -void set_usb_phy2_clk(void);
> > +void set_usb_phy_clk(void);
> > +#if defined(CONFIG_MX51)
> > +void enable_usb_phy_clk(unsigned char enable);
> > +#elif defined(CONFIG_MX53)
> > +void enable_usb_phy1_clk(unsigned char enable);
> >  void enable_usb_phy2_clk(unsigned char enable);
> > +#endif
> 
> If you follow my suggestion above, then here you will only have:
>  -void set_usb_phy2_clk(void);
>  +void set_usb_phy_clk(void);
>  +void enable_usb_phy1_clk(unsigned char enable);
> 
> and no complicating with #ifdefs needed.
> 
> >  void set_usboh3_clk(void);
> >  void enable_usboh3_clk(unsigned char enable);
> >  void mxc_set_sata_internal_clock(void);
> > diff --git u-boot-imx-e1eb75b.orig/drivers/usb/host/ehci-mx5.c
> > u-boot-imx-e1eb75b/drivers/usb/host/ehci-mx5.c
> > index 58cdcbe..5bf89f0 100644
> > --- u-boot-imx-e1eb75b.orig/drivers/usb/host/ehci-mx5.c
> > +++ u-boot-imx-e1eb75b/drivers/usb/host/ehci-mx5.c
> > @@ -221,8 +221,12 @@ int ehci_hcd_init(void)
> >  
> >  	set_usboh3_clk();
> >  	enable_usboh3_clk(1);
> > -	set_usb_phy2_clk();
> > +	set_usb_phy_clk();
> > +#if defined(CONFIG_MX51) && CONFIG_MXC_USB_PORT == 0
> > +	enable_usb_phy_clk(1);
> > +#elif defined(CONFIG_MX53)
> >  	enable_usb_phy2_clk(1);
> > +#endif
> 
> same here, it should be much cleaner.
> 
> >  	mdelay(1);
> >  
> >  	/* Do board specific initialization */
> > 

Indeed. In clock.h, the #ifdefs could anyway be removed with the naming from my patch. The only difference would be an error at link time rather than at compile time if these functions were called for the wrong i.MX5. If we change the naming as you suggest, it's not a problem for set_usb_phy1_clk(), but for enable_usb_phy2_clk() I think that it would not really make sense. My point is that ehci-mx5.c should be cleaned even more deeply in order to initialize the USB PHYs corresponding to the selected EHCI ports, and not all (or only some for i.MX53) the PHYs at the beginning of ehci_hcd_init(). Also, calling enable_usb_phy2_clk() for i.MX51 would not make sense, even if it does nothing, because it would be confusing. So this solution has both advantages and drawbacks.

Stefano, Marek, what do you think?

Best regards,
Beno?t

[U-Boot] [PATCH v2 09/14] mx5 clocks: Fix get_ipg_per_clk()

[Benoît Thébaudeau]

Hi Stefano,

On Friday, September 28, 2012 11:31:11 AM, Stefano Babic wrote:
> On 27/09/2012 22:23, Beno?t Th?baudeau wrote:
> > This fixes the "IPG PERCLK" frequency printed by the clocks
> > command. The issue
> > was that get_ipg_per_clk() used periph_clk instead of lp_apm in the
> > case
> > CCM.CBCMR.perclk_lp_apm_sel is set.
> > 
> > It also fixes I?C support.
> > 
> 
> Hi Beno?t,
> 
> I understand "clocks" reports a wrong value only if
> CCM.CBCMR.perclk_lp_apm_sel is set, not always.

Correct.

> Can you better explain me which is wrong and which is the fix for I2C
> ?
> It seems unrelated, and I do not get the reason checking the patch

It's only because mxc_get_clock(MXC_IPG_CLK) (or mxc_get_clock(MXC_I2C_CLK)
after [1]) both return get_ipg_per_clk() for the I?C driver's clock.

Best regards,
Beno?t

[1] http://git.denx.de/?p=u-boot/u-boot-imx.git;a=commitdiff;h=f6e11ba5997be9cc1044ca55f7b20d04bb7ed38a

[U-Boot] [PATCH v2 05/14] mx51: Fix USB PHY clocks

[Stefano Babic]

On 28/09/2012 12:27, Beno?t Th?baudeau wrote:
> Hi Igor,
> 
> On Friday, September 28, 2012 9:26:38 AM, Igor Grinberg wrote:
>> Hi Beno?t,
>>
>> please, see a minor #ifdef comment below
>>
>> On 09/27/12 22:21, Beno?t Th?baudeau wrote:
>>> The i.MX51 has a single USB PHY clock, while the i.MX53 has two.
>>> These 3 clocks
>>> have different clock gate control bit-fields.
>>>
>>> The existing code was correct only for i.MX53, so this patch fixes
>>> the i.MX51
>>> use case.
>>>
>>> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
>>> Cc: Stefano Babic <sbabic@denx.de>
>>> Cc: Marek Vasut <marex@denx.de>
>>> Cc: Jana Rapava <fermata7@gmail.com>
>>> Cc: Wolfgang Grandegger <wg@denx.de>
>>> Cc: Igor Grinberg <grinberg@compulab.co.il>
>>> ---
>>> This patch supersedes http://patchwork.ozlabs.org/patch/177403/ .
>>> Changes for v2:
>>>  - Split patch into 3 parts (the 3, 4 and 5 from this v2 series).
>>>  - Merge the various set_usb_phy*_clk() functions (they were
>>>  identical).
>>>
>>>  .../arch/arm/cpu/armv7/mx5/clock.c                 |   20
>>>  +++++++++++++-------
>>>  .../arch/arm/include/asm/arch-mx5/clock.h          |    7 ++++++-
>>>  .../drivers/usb/host/ehci-mx5.c                    |    6 +++++-
>>>  3 files changed, 24 insertions(+), 9 deletions(-)
>>>
>>> diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
>>> u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
>>> index df7e5cd..f727cfa 100644
>>> --- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
>>> +++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
>>> @@ -126,11 +126,21 @@ int enable_i2c_clk(unsigned char enable,
>>> unsigned i2c_num)
>>>  }
>>>  #endif
>>>  
>>> -void set_usb_phy1_clk(void)
>>> +void set_usb_phy_clk(void)
>>>  {
>>>  	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
>>>  }
>>>  
>>> +#if defined(CONFIG_MX51)
>>> +void enable_usb_phy_clk(unsigned char enable)
>>
>> I think the same name as the MX53 case will do better, see
>> explanation below.
>>
>>> +{
>>> +	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON :
>>> MXC_CCM_CCGR_CG_OFF;
>>> +
>>> +	clrsetbits_le32(&mxc_ccm->CCGR2,
>>> +			MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
>>> +			MXC_CCM_CCGR2_USB_PHY(cg));
>>> +}
>>
>> I would add here (again explanation below):
>> void enable_usb_phy2_clk(unsigned char enable)
>> {
>> 	/* MX51 has a single USB PHY clock, so do nothing here */
>> }
>>
>>> +#elif defined(CONFIG_MX53)
>>>  void enable_usb_phy1_clk(unsigned char enable)
>>>  {
>>>  	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON :
>>>  	MXC_CCM_CCGR_CG_OFF;
>>> @@ -140,11 +150,6 @@ void enable_usb_phy1_clk(unsigned char enable)
>>>  			MXC_CCM_CCGR4_USB_PHY1(cg));
>>>  }
>>>  
>>> -void set_usb_phy2_clk(void)
>>> -{
>>> -	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
>>> -}
>>> -
>>>  void enable_usb_phy2_clk(unsigned char enable)
>>>  {
>>>  	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON :
>>>  	MXC_CCM_CCGR_CG_OFF;
>>> @@ -153,6 +158,7 @@ void enable_usb_phy2_clk(unsigned char enable)
>>>  			MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
>>>  			MXC_CCM_CCGR4_USB_PHY2(cg));
>>>  }
>>> +#endif
>>>  
>>>  /*
>>>   * Calculate the frequency of PLLn.
>>> @@ -803,7 +809,7 @@ void mxc_set_sata_internal_clock(void)
>>>  	u32 *tmp_base =
>>>  		(u32 *)(IIM_BASE_ADDR + 0x180c);
>>>  
>>> -	set_usb_phy1_clk();
>>> +	set_usb_phy_clk();
>>>  
>>>  	clrsetbits_le32(tmp_base, 0x6, 0x4);
>>>  }
>>> diff --git
>>> u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/clock.h
>>> u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/clock.h
>>> index 55e3b51..e4ca417 100644
>>> --- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/clock.h
>>> +++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/clock.h
>>> @@ -56,8 +56,13 @@ u32 imx_get_uartclk(void);
>>>  u32 imx_get_fecclk(void);
>>>  unsigned int mxc_get_clock(enum mxc_clock clk);
>>>  int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
>>> -void set_usb_phy2_clk(void);
>>> +void set_usb_phy_clk(void);
>>> +#if defined(CONFIG_MX51)
>>> +void enable_usb_phy_clk(unsigned char enable);
>>> +#elif defined(CONFIG_MX53)
>>> +void enable_usb_phy1_clk(unsigned char enable);
>>>  void enable_usb_phy2_clk(unsigned char enable);
>>> +#endif
>>
>> If you follow my suggestion above, then here you will only have:
>>  -void set_usb_phy2_clk(void);
>>  +void set_usb_phy_clk(void);
>>  +void enable_usb_phy1_clk(unsigned char enable);
>>
>> and no complicating with #ifdefs needed.
>>
>>>  void set_usboh3_clk(void);
>>>  void enable_usboh3_clk(unsigned char enable);
>>>  void mxc_set_sata_internal_clock(void);
>>> diff --git u-boot-imx-e1eb75b.orig/drivers/usb/host/ehci-mx5.c
>>> u-boot-imx-e1eb75b/drivers/usb/host/ehci-mx5.c
>>> index 58cdcbe..5bf89f0 100644
>>> --- u-boot-imx-e1eb75b.orig/drivers/usb/host/ehci-mx5.c
>>> +++ u-boot-imx-e1eb75b/drivers/usb/host/ehci-mx5.c
>>> @@ -221,8 +221,12 @@ int ehci_hcd_init(void)
>>>  
>>>  	set_usboh3_clk();
>>>  	enable_usboh3_clk(1);
>>> -	set_usb_phy2_clk();
>>> +	set_usb_phy_clk();
>>> +#if defined(CONFIG_MX51) && CONFIG_MXC_USB_PORT == 0
>>> +	enable_usb_phy_clk(1);
>>> +#elif defined(CONFIG_MX53)
>>>  	enable_usb_phy2_clk(1);
>>> +#endif
>>
>> same here, it should be much cleaner.
>>
>>>  	mdelay(1);
>>>  
>>>  	/* Do board specific initialization */
>>>
> 
> Indeed. In clock.h, the #ifdefs could anyway be removed with the naming from my patch. The only difference would be an error at link time rather than at compile time if these functions were called for the wrong i.MX5. If we change the naming as you suggest, it's not a problem for set_usb_phy1_clk(), but for enable_usb_phy2_clk() I think that it would not really make sense. My point is that ehci-mx5.c should be cleaned even more deeply in order to initialize the USB PHYs corresponding to the selected EHCI ports, and not all (or only some for i.MX53) the PHYs at the beginning of ehci_hcd_init(). Also, calling enable_usb_phy2_clk() for i.MX51 would not make sense, even if it does nothing, because it would be confusing. So this solution has both advantages and drawbacks.
> 
> Stefano, Marek, what do you think?

I am much sensible regarding #ifdef. I admit, I hate them. Igor's
suggestion drop some of them, and IMHO the code is more readable,
independently if and when the ehci-mx5.c will be cleaned up. However, I
understand it is a personal taste ;-)

Best regards,
Stefano


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 09/14] mx5 clocks: Fix get_ipg_per_clk()

[Stefano Babic]

On 28/09/2012 12:42, Beno?t Th?baudeau wrote:
> Hi Stefano,
> 
> On Friday, September 28, 2012 11:31:11 AM, Stefano Babic wrote:
>> On 27/09/2012 22:23, Beno?t Th?baudeau wrote:
>>> This fixes the "IPG PERCLK" frequency printed by the clocks
>>> command. The issue
>>> was that get_ipg_per_clk() used periph_clk instead of lp_apm in the
>>> case
>>> CCM.CBCMR.perclk_lp_apm_sel is set.
>>>
>>> It also fixes I?C support.
>>>
>>
>> Hi Beno?t,
>>
>> I understand "clocks" reports a wrong value only if
>> CCM.CBCMR.perclk_lp_apm_sel is set, not always.
> 
> Correct.
> 
>> Can you better explain me which is wrong and which is the fix for I2C
>> ?
>> It seems unrelated, and I do not get the reason checking the patch
> 
> It's only because mxc_get_clock(MXC_IPG_CLK) (or mxc_get_clock(MXC_I2C_CLK)
> after [1]) both return get_ipg_per_clk() for the I?C driver's clock.

Ah, thanks - it is clear now.

Best regards,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 09/14] mx5 clocks: Fix get_ipg_per_clk()

[Benoît Thébaudeau]

Hi Stefano,

On Friday, September 28, 2012 12:45:31 PM, Stefano Babic wrote:
> On 28/09/2012 12:42, Beno?t Th?baudeau wrote:
> > Hi Stefano,
> > 
> > On Friday, September 28, 2012 11:31:11 AM, Stefano Babic wrote:
> >> On 27/09/2012 22:23, Beno?t Th?baudeau wrote:
> >>> This fixes the "IPG PERCLK" frequency printed by the clocks
> >>> command. The issue
> >>> was that get_ipg_per_clk() used periph_clk instead of lp_apm in
> >>> the
> >>> case
> >>> CCM.CBCMR.perclk_lp_apm_sel is set.
> >>>
> >>> It also fixes I?C support.
> >>>
> >>
> >> Hi Beno?t,
> >>
> >> I understand "clocks" reports a wrong value only if
> >> CCM.CBCMR.perclk_lp_apm_sel is set, not always.
> > 
> > Correct.
> > 
> >> Can you better explain me which is wrong and which is the fix for
> >> I2C
> >> ?
> >> It seems unrelated, and I do not get the reason checking the patch
> > 
> > It's only because mxc_get_clock(MXC_IPG_CLK) (or
> > mxc_get_clock(MXC_I2C_CLK)
> > after [1]) both return get_ipg_per_clk() for the I?C driver's
> > clock.
> 
> Ah, thanks - it is clear now.

For the full story, I?C was completely broken on my custom i.MX51 platform
because of this issue. The command "i2c probe" only detected address 0x00, and
if run again, it hung.

Best regards,
Beno?t

[U-Boot] [PATCH v2 05/14] mx51: Fix USB PHY clocks

[Benoît Thébaudeau]

Hi Stefano,

On Friday, September 28, 2012 12:43:53 PM, Stefano Babic wrote:
> On 28/09/2012 12:27, Beno?t Th?baudeau wrote:
> > Hi Igor,
> > 
> > On Friday, September 28, 2012 9:26:38 AM, Igor Grinberg wrote:
> >> Hi Beno?t,
> >>
> >> please, see a minor #ifdef comment below
> >>
> >> On 09/27/12 22:21, Beno?t Th?baudeau wrote:
> >>> The i.MX51 has a single USB PHY clock, while the i.MX53 has two.
> >>> These 3 clocks
> >>> have different clock gate control bit-fields.
> >>>
> >>> The existing code was correct only for i.MX53, so this patch
> >>> fixes
> >>> the i.MX51
> >>> use case.
> >>>
> >>> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> >>> Cc: Stefano Babic <sbabic@denx.de>
> >>> Cc: Marek Vasut <marex@denx.de>
> >>> Cc: Jana Rapava <fermata7@gmail.com>
> >>> Cc: Wolfgang Grandegger <wg@denx.de>
> >>> Cc: Igor Grinberg <grinberg@compulab.co.il>
> >>> ---
> >>> This patch supersedes http://patchwork.ozlabs.org/patch/177403/ .
> >>> Changes for v2:
> >>>  - Split patch into 3 parts (the 3, 4 and 5 from this v2 series).
> >>>  - Merge the various set_usb_phy*_clk() functions (they were
> >>>  identical).
> >>>
> >>>  .../arch/arm/cpu/armv7/mx5/clock.c                 |   20
> >>>  +++++++++++++-------
> >>>  .../arch/arm/include/asm/arch-mx5/clock.h          |    7
> >>>  ++++++-
> >>>  .../drivers/usb/host/ehci-mx5.c                    |    6 +++++-
> >>>  3 files changed, 24 insertions(+), 9 deletions(-)
> >>>
> >>> diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
> >>> u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
> >>> index df7e5cd..f727cfa 100644
> >>> --- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
> >>> +++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
> >>> @@ -126,11 +126,21 @@ int enable_i2c_clk(unsigned char enable,
> >>> unsigned i2c_num)
> >>>  }
> >>>  #endif
> >>>  
> >>> -void set_usb_phy1_clk(void)
> >>> +void set_usb_phy_clk(void)
> >>>  {
> >>>  	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
> >>>  }
> >>>  
> >>> +#if defined(CONFIG_MX51)
> >>> +void enable_usb_phy_clk(unsigned char enable)
> >>
> >> I think the same name as the MX53 case will do better, see
> >> explanation below.
> >>
> >>> +{
> >>> +	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON :
> >>> MXC_CCM_CCGR_CG_OFF;
> >>> +
> >>> +	clrsetbits_le32(&mxc_ccm->CCGR2,
> >>> +			MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
> >>> +			MXC_CCM_CCGR2_USB_PHY(cg));
> >>> +}
> >>
> >> I would add here (again explanation below):
> >> void enable_usb_phy2_clk(unsigned char enable)
> >> {
> >> 	/* MX51 has a single USB PHY clock, so do nothing here */
> >> }
> >>
> >>> +#elif defined(CONFIG_MX53)
> >>>  void enable_usb_phy1_clk(unsigned char enable)
> >>>  {
> >>>  	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON :
> >>>  	MXC_CCM_CCGR_CG_OFF;
> >>> @@ -140,11 +150,6 @@ void enable_usb_phy1_clk(unsigned char
> >>> enable)
> >>>  			MXC_CCM_CCGR4_USB_PHY1(cg));
> >>>  }
> >>>  
> >>> -void set_usb_phy2_clk(void)
> >>> -{
> >>> -	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
> >>> -}
> >>> -
> >>>  void enable_usb_phy2_clk(unsigned char enable)
> >>>  {
> >>>  	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON :
> >>>  	MXC_CCM_CCGR_CG_OFF;
> >>> @@ -153,6 +158,7 @@ void enable_usb_phy2_clk(unsigned char
> >>> enable)
> >>>  			MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
> >>>  			MXC_CCM_CCGR4_USB_PHY2(cg));
> >>>  }
> >>> +#endif
> >>>  
> >>>  /*
> >>>   * Calculate the frequency of PLLn.
> >>> @@ -803,7 +809,7 @@ void mxc_set_sata_internal_clock(void)
> >>>  	u32 *tmp_base =
> >>>  		(u32 *)(IIM_BASE_ADDR + 0x180c);
> >>>  
> >>> -	set_usb_phy1_clk();
> >>> +	set_usb_phy_clk();
> >>>  
> >>>  	clrsetbits_le32(tmp_base, 0x6, 0x4);
> >>>  }
> >>> diff --git
> >>> u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/clock.h
> >>> u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/clock.h
> >>> index 55e3b51..e4ca417 100644
> >>> --- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/clock.h
> >>> +++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/clock.h
> >>> @@ -56,8 +56,13 @@ u32 imx_get_uartclk(void);
> >>>  u32 imx_get_fecclk(void);
> >>>  unsigned int mxc_get_clock(enum mxc_clock clk);
> >>>  int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
> >>> -void set_usb_phy2_clk(void);
> >>> +void set_usb_phy_clk(void);
> >>> +#if defined(CONFIG_MX51)
> >>> +void enable_usb_phy_clk(unsigned char enable);
> >>> +#elif defined(CONFIG_MX53)
> >>> +void enable_usb_phy1_clk(unsigned char enable);
> >>>  void enable_usb_phy2_clk(unsigned char enable);
> >>> +#endif
> >>
> >> If you follow my suggestion above, then here you will only have:
> >>  -void set_usb_phy2_clk(void);
> >>  +void set_usb_phy_clk(void);
> >>  +void enable_usb_phy1_clk(unsigned char enable);
> >>
> >> and no complicating with #ifdefs needed.
> >>
> >>>  void set_usboh3_clk(void);
> >>>  void enable_usboh3_clk(unsigned char enable);
> >>>  void mxc_set_sata_internal_clock(void);
> >>> diff --git u-boot-imx-e1eb75b.orig/drivers/usb/host/ehci-mx5.c
> >>> u-boot-imx-e1eb75b/drivers/usb/host/ehci-mx5.c
> >>> index 58cdcbe..5bf89f0 100644
> >>> --- u-boot-imx-e1eb75b.orig/drivers/usb/host/ehci-mx5.c
> >>> +++ u-boot-imx-e1eb75b/drivers/usb/host/ehci-mx5.c
> >>> @@ -221,8 +221,12 @@ int ehci_hcd_init(void)
> >>>  
> >>>  	set_usboh3_clk();
> >>>  	enable_usboh3_clk(1);
> >>> -	set_usb_phy2_clk();
> >>> +	set_usb_phy_clk();
> >>> +#if defined(CONFIG_MX51) && CONFIG_MXC_USB_PORT == 0
> >>> +	enable_usb_phy_clk(1);
> >>> +#elif defined(CONFIG_MX53)
> >>>  	enable_usb_phy2_clk(1);
> >>> +#endif
> >>
> >> same here, it should be much cleaner.
> >>
> >>>  	mdelay(1);
> >>>  
> >>>  	/* Do board specific initialization */
> >>>
> > 
> > Indeed. In clock.h, the #ifdefs could anyway be removed with the
> > naming from my patch. The only difference would be an error at
> > link time rather than at compile time if these functions were
> > called for the wrong i.MX5. If we change the naming as you
> > suggest, it's not a problem for set_usb_phy1_clk(), but for
> > enable_usb_phy2_clk() I think that it would not really make sense.
> > My point is that ehci-mx5.c should be cleaned even more deeply in
> > order to initialize the USB PHYs corresponding to the selected
> > EHCI ports, and not all (or only some for i.MX53) the PHYs at the
> > beginning of ehci_hcd_init(). Also, calling enable_usb_phy2_clk()
> > for i.MX51 would not make sense, even if it does nothing, because
> > it would be confusing. So this solution has both advantages and
> > drawbacks.
> > 
> > Stefano, Marek, what do you think?
> 
> I am much sensible regarding #ifdef. I admit, I hate them. Igor's
> suggestion drop some of them, and IMHO the code is more readable,
> independently if and when the ehci-mx5.c will be cleaned up. However,
> I
> understand it is a personal taste ;-)

OK, so should I eventually send for that an update only of this specific patch
(not the full series), or will it just be fine with the current v2?

Best regards,
Beno?t

[U-Boot] [PATCH v2 09/14] mx5 clocks: Fix get_ipg_per_clk()

[Stefano Babic]

On 28/09/2012 14:55, Beno?t Th?baudeau wrote:

>>
>> Ah, thanks - it is clear now.
> 
> For the full story, I?C was completely broken on my custom i.MX51 platform
> because of this issue. The command "i2c probe" only detected address 0x00, and
> if run again, it hung.

Ok - this explains to myself why I have never noted - I used SPI on MX51
for PMIC, and I2C on MX53.

Regards,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 05/14] mx51: Fix USB PHY clocks

[Stefano Babic]

On 28/09/2012 15:00, Beno?t Th?baudeau wrote:

> 
> OK, so should I eventually send for that an update only of this specific patch
> (not the full series), or will it just be fine with the current v2?

Not the full series, send an update only for this patch, thanks.

Best regards,
Stefano


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v3 05/14] mx51: Fix USB PHY clocks

[Benoît Thébaudeau]

The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks
have different clock gate control bit-fields.

The existing code was correct only for i.MX53, so this patch fixes the i.MX51
use case.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Jana Rapava <fermata7@gmail.com>
Cc: Wolfgang Grandegger <wg@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
---
This patch supersedes http://patchwork.ozlabs.org/patch/187458/ .
Changes for v2:
 - Split patch into 3 parts (the 3, 4 and 5 from this v2 series).
 - Merge the various set_usb_phy*_clk() functions (they were identical).
Changes for v3:
 - Use same functions on i.MX51 (with one empty) as on i.MX53 in order to avoid
   #ifdef's.

 .../arch/arm/cpu/armv7/mx5/clock.c                 |   25 ++++++++++++++------
 .../arch/arm/include/asm/arch-mx5/clock.h          |    3 ++-
 .../drivers/usb/host/ehci-mx5.c                    |    3 ++-
 3 files changed, 22 insertions(+), 9 deletions(-)

diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
index df7e5cd..fd5456e 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
@@ -126,23 +126,33 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 }
 #endif
 
-void set_usb_phy1_clk(void)
+void set_usb_phy_clk(void)
 {
 	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
 }
 
+#if defined(CONFIG_MX51)
 void enable_usb_phy1_clk(unsigned char enable)
 {
 	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
 
-	clrsetbits_le32(&mxc_ccm->CCGR4,
-			MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
-			MXC_CCM_CCGR4_USB_PHY1(cg));
+	clrsetbits_le32(&mxc_ccm->CCGR2,
+			MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
+			MXC_CCM_CCGR2_USB_PHY(cg));
 }
 
-void set_usb_phy2_clk(void)
+void enable_usb_phy2_clk(unsigned char enable)
 {
-	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
+	/* i.MX51 has a single USB PHY clock, so do nothing here. */
+}
+#elif defined(CONFIG_MX53)
+void enable_usb_phy1_clk(unsigned char enable)
+{
+	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+	clrsetbits_le32(&mxc_ccm->CCGR4,
+			MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
+			MXC_CCM_CCGR4_USB_PHY1(cg));
 }
 
 void enable_usb_phy2_clk(unsigned char enable)
@@ -153,6 +163,7 @@ void enable_usb_phy2_clk(unsigned char enable)
 			MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
 			MXC_CCM_CCGR4_USB_PHY2(cg));
 }
+#endif
 
 /*
  * Calculate the frequency of PLLn.
@@ -803,7 +814,7 @@ void mxc_set_sata_internal_clock(void)
 	u32 *tmp_base =
 		(u32 *)(IIM_BASE_ADDR + 0x180c);
 
-	set_usb_phy1_clk();
+	set_usb_phy_clk();
 
 	clrsetbits_le32(tmp_base, 0x6, 0x4);
 }
diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/clock.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/clock.h
index 55e3b51..668e913 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/clock.h
+++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/clock.h
@@ -56,7 +56,8 @@ u32 imx_get_uartclk(void);
 u32 imx_get_fecclk(void);
 unsigned int mxc_get_clock(enum mxc_clock clk);
 int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
-void set_usb_phy2_clk(void);
+void set_usb_phy_clk(void);
+void enable_usb_phy1_clk(unsigned char enable);
 void enable_usb_phy2_clk(unsigned char enable);
 void set_usboh3_clk(void);
 void enable_usboh3_clk(unsigned char enable);
diff --git u-boot-imx-e1eb75b.orig/drivers/usb/host/ehci-mx5.c u-boot-imx-e1eb75b/drivers/usb/host/ehci-mx5.c
index 58cdcbe..fbfd310 100644
--- u-boot-imx-e1eb75b.orig/drivers/usb/host/ehci-mx5.c
+++ u-boot-imx-e1eb75b/drivers/usb/host/ehci-mx5.c
@@ -221,7 +221,8 @@ int ehci_hcd_init(void)
 
 	set_usboh3_clk();
 	enable_usboh3_clk(1);
-	set_usb_phy2_clk();
+	set_usb_phy_clk();
+	enable_usb_phy1_clk(1);
 	enable_usb_phy2_clk(1);
 	mdelay(1);
 

[U-Boot] [PATCH v2 01/14] mx5/6: Define default SoC input clock frequencies

[Stefano Babic]

On 27/09/2012 22:19, Beno?t Th?baudeau wrote:
> Define default SoC input clock frequencies for i.MX5/6 in order to get rid of
> duplicated definitions.
> 
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Jason Liu <r64343@freescale.com>
> Cc: Matt Sealey <matt@genesi-usa.com>
> Cc: Fabio Estevam <fabio.estevam@freescale.com>
> ---


All series applied to u-boot-imx, next branch, thanks.

Best regards,
Stefano Babic


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 01/14] mx5/6: Define default SoC input clock frequencies

[Benoît Thébaudeau]

Hi Stefano,

On Sunday, September 30, 2012 12:28:07 PM, Stefano Babic wrote:
> On 27/09/2012 22:19, Beno?t Th?baudeau wrote:
> > Define default SoC input clock frequencies for i.MX5/6 in order to
> > get rid of
> > duplicated definitions.
> > 
> > Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> > Cc: Stefano Babic <sbabic@denx.de>
> > Cc: Jason Liu <r64343@freescale.com>
> > Cc: Matt Sealey <matt@genesi-usa.com>
> > Cc: Fabio Estevam <fabio.estevam@freescale.com>
> > ---
> 
> 
> All series applied to u-boot-imx, next branch, thanks.

Thanks. Since you have applied it to /next, the following hunk should be added
for 01/14 for include/configs/mx6qsabre_common.h:
---
#define __MX6QSABRE_COMMON_CONFIG_H

#define CONFIG_MX6Q
-#define CONFIG_SYS_MX6_HCLK            24000000
-#define CONFIG_SYS_MX6_CLK32           32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

---

Since there is no breakage, this can be done as a replacement or separately. How
should we proceed?

Best regards,
Beno?t

[U-Boot] [PATCH v2 01/14] mx5/6: Define default SoC input clock frequencies

[Stefano Babic]

On 30/09/2012 15:55, Beno?t Th?baudeau wrote:
> Hi Stefano,
> 
> On Sunday, September 30, 2012 12:28:07 PM, Stefano Babic wrote:
>> On 27/09/2012 22:19, Beno?t Th?baudeau wrote:
>>> Define default SoC input clock frequencies for i.MX5/6 in order to
>>> get rid of
>>> duplicated definitions.
>>>
>>> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
>>> Cc: Stefano Babic <sbabic@denx.de>
>>> Cc: Jason Liu <r64343@freescale.com>
>>> Cc: Matt Sealey <matt@genesi-usa.com>
>>> Cc: Fabio Estevam <fabio.estevam@freescale.com>
>>> ---
>>
>>
>> All series applied to u-boot-imx, next branch, thanks.
> 
> Thanks. Since you have applied it to /next, the following hunk should be added
> for 01/14 for include/configs/mx6qsabre_common.h:
> ---
> #define __MX6QSABRE_COMMON_CONFIG_H
> 
> #define CONFIG_MX6Q
> -#define CONFIG_SYS_MX6_HCLK            24000000
> -#define CONFIG_SYS_MX6_CLK32           32768
> #define CONFIG_DISPLAY_CPUINFO
> #define CONFIG_DISPLAY_BOARDINFO
> 
> ---
> 
> Since there is no breakage, this can be done as a replacement or separately. How
> should we proceed?

Because changes are so easy, my proposal to Fabio is that I can fix
directly his patch into my -next. Of course, this can be fixed with a
new patch, too.

Best regards,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v3 05/14] mx51: Fix USB PHY clocks

[Igor Grinberg]

On 09/28/12 19:09, Beno?t Th?baudeau wrote:
> The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks
> have different clock gate control bit-fields.
> 
> The existing code was correct only for i.MX53, so this patch fixes the i.MX51
> use case.
> 
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Jana Rapava <fermata7@gmail.com>
> Cc: Wolfgang Grandegger <wg@denx.de>
> Cc: Igor Grinberg <grinberg@compulab.co.il>

Acked-by: Igor Grinberg <grinberg@compulab.co.il>

-- 
Regards,
Igor.