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CTRY:IT; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:smtpO365.st.com; PTR:ErrorRetry; CAT:NONE; SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Nov 2025 17:59:53.1084 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 09b26082-bfad-4b06-33f6-08de22de7279 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f; Ip=[164.130.1.60]; Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF000001AF.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS4PR10MB6181 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTEzMDE0MCBTYWx0ZWRfX5ZLvYMx6cR8w FamRIYZFLjy+9HqNzHf7H8YmNOJJ6jWe6xvJk0z0f/bX+UUbOykZC07Z65fjqwZhhbdc5o8KDYd 50sOWLRrjnMVaSt7YvHFtAakj/Y4sJb93aBiBZU/J+t/55u+TQJqv0nAXhvUOPTqMP68f56b8y6 zu8DUcFTj8ISQEmAT+SjbAIWQEFXpaypbcvveqBTfiqTBe5ffM3kRsvTPN3VDL437GLkXjlQ1fG UkqrX1Nr4qQ4k/6+mOLjv6JvdoE5jZcMkXzTm3mJzDjnjpCjlYn51KP77xKxzp/x3bjO/cmtzbB Yr+XC9+2cy6u4a7PwEVaLjTMFMguW21xvxnd+yXbCHdH3xLRRbOZ+U0UojG/DOL1zgcUl5GDQMN EOkDpigr6telxsFyL1VvmUa3z8TkgA== X-Authority-Analysis: v=2.4 cv=D+hK6/Rj c=1 sm=1 tr=0 ts=69161c9e cx=c_pps a=6PCtUV3SjW4dSF/fw/j/Nw==:117 a=uCuRqK4WZKO1kjFMGfU4lQ==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=q6CKDgr7omsA:10 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=KrXZwBdWH7kA:10 a=VkNPw1HP01LnGYTKEx00:22 a=8b9GpE9nAAAA:8 a=PUsbfvoI6Aq4JJ9LE7IA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=T3LWEMljR5ZiDmsYVIUa:22 a=HhbK4dLum7pmb74im6QT:22 X-Proofpoint-ORIG-GUID: A-k06rSz5Z_vGS3qOLbZgW08e03JoiD3 X-Proofpoint-GUID: A-k06rSz5Z_vGS3qOLbZgW08e03JoiD3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-13_03,2025-11-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 priorityscore=1501 adultscore=0 suspectscore=0 bulkscore=0 phishscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511130140 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Hi, On 10/9/25 17:25, Patrice Chotard wrote: > From: Olivier Moysan > > Add support of STM32 ADCs to STM32MP13x. This patch introduces > stm32_adc_regspec structure, as this is already done in kernel > driver, to manage smartly the differences in register set > between STMP32MP15 and STM32MP13 ADCs. > > Signed-off-by: Olivier Moysan > Signed-off-by: Patrice Chotard > --- > > drivers/adc/stm32-adc-core.c | 1 + > drivers/adc/stm32-adc.c | 79 +++++++++++++++++++++++++++++++----- > 2 files changed, 70 insertions(+), 10 deletions(-) > > diff --git a/drivers/adc/stm32-adc-core.c b/drivers/adc/stm32-adc-core.c > index af340b8b273..3446e34fa46 100644 > --- a/drivers/adc/stm32-adc-core.c > +++ b/drivers/adc/stm32-adc-core.c > @@ -200,6 +200,7 @@ err_aclk_disable: > static const struct udevice_id stm32_adc_core_ids[] = { > { .compatible = "st,stm32h7-adc-core" }, > { .compatible = "st,stm32mp1-adc-core" }, > + { .compatible = "st,stm32mp13-adc-core" }, > {} > }; > > diff --git a/drivers/adc/stm32-adc.c b/drivers/adc/stm32-adc.c > index d50f00f1233..808c3c610f8 100644 > --- a/drivers/adc/stm32-adc.c > +++ b/drivers/adc/stm32-adc.c > @@ -49,16 +49,35 @@ > /* STM32H7_ADC_SQR1 - bit fields */ > #define STM32H7_SQ1_SHIFT 6 > > +/* STM32H7_ADC_DIFSEL - bit fields */ > +#define STM32H7_DIFSEL_SHIFT 0 > +#define STM32H7_DIFSEL_MASK GENMASK(19, 0) > + > /* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */ > #define STM32H7_BOOST_CLKRATE 20000000UL > > +/* STM32MP13 - Registers for each ADC instance */ > +#define STM32MP13_ADC_DIFSEL 0xB0 > + > +/* STM32MP13_ADC_CFGR specific bit fields */ > +#define STM32MP13_DMAEN BIT(0) > +#define STM32MP13_DMACFG BIT(1) > + > +/* STM32MP13_ADC_DIFSEL - bit fields */ > +#define STM32MP13_DIFSEL_SHIFT 0 > +#define STM32MP13_DIFSEL_MASK GENMASK(18, 0) > + > #define STM32_ADC_CH_MAX 20 /* max number of channels */ > #define STM32_ADC_TIMEOUT_US 100000 > > struct stm32_adc_cfg { > + const struct stm32_adc_regspec *regs; minor replace tab by space before "*regs" and it is strange to use "struct stm32_adc_regspec" before to define it that can cause some warning with compiler ? > unsigned int max_channels; > unsigned int num_bits; > bool has_vregready; > + bool has_boostmode; > + bool has_linearcal; > + bool has_presel; > }; > > struct stm32_adc { > @@ -67,11 +86,30 @@ struct stm32_adc { > const struct stm32_adc_cfg *cfg; > }; > > +struct stm32_adc_regs { > + int reg; > + int mask; > + int shift; > +}; > + > +struct stm32_adc_regspec { > + const struct stm32_adc_regs difsel; > +}; > + > +static const struct stm32_adc_regspec stm32h7_adc_regspec = { > + .difsel = { STM32H7_ADC_DIFSEL, STM32H7_DIFSEL_MASK }, > +}; > + > +static const struct stm32_adc_regspec stm32mp13_adc_regspec = { > + .difsel = { STM32MP13_ADC_DIFSEL, STM32MP13_DIFSEL_MASK }, > +}; minor all this block can move before "struct stm32_adc_cfg" (when used) > static void stm32_adc_enter_pwr_down(struct udevice *dev) > { > struct stm32_adc *adc = dev_get_priv(dev); > > - clrbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_BOOST); > + if (adc->cfg->has_boostmode) > + clrbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_BOOST); > + > /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */ > setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_DEEPPWD); > } > @@ -90,8 +128,7 @@ static int stm32_adc_exit_pwr_down(struct udevice *dev) > /* Exit deep power down, then enable ADC voltage regulator */ > clrbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_DEEPPWD); > setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADVREGEN); > - > - if (common->rate > STM32H7_BOOST_CLKRATE) > + if (adc->cfg->has_boostmode && common->rate > STM32H7_BOOST_CLKRATE) > setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_BOOST); > > /* Wait for startup time */ > @@ -134,7 +171,7 @@ static int stm32_adc_start_channel(struct udevice *dev, int channel) > return ret; > > /* Only use single ended channels */ > - writel(0, adc->regs + STM32H7_ADC_DIFSEL); > + clrbits_le32(adc->regs + adc->cfg->regs->difsel.reg, adc->cfg->regs->difsel.mask); > > /* Enable ADC, Poll for ADRDY to be set (after adc startup time) */ > setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADEN); > @@ -147,7 +184,8 @@ static int stm32_adc_start_channel(struct udevice *dev, int channel) > } > > /* Preselect channels */ > - writel(uc_pdata->channel_mask, adc->regs + STM32H7_ADC_PCSEL); > + if (adc->cfg->has_presel) > + writel(uc_pdata->channel_mask, adc->regs + STM32H7_ADC_PCSEL); > > /* Set sampling time to max value by default */ > writel(0xffffffff, adc->regs + STM32H7_ADC_SMPR1); > @@ -156,9 +194,11 @@ static int stm32_adc_start_channel(struct udevice *dev, int channel) > /* Program regular sequence: chan in SQ1 & len = 0 for one channel */ > writel(channel << STM32H7_SQ1_SHIFT, adc->regs + STM32H7_ADC_SQR1); > > - /* Trigger detection disabled (conversion can be launched in SW) */ > - clrbits_le32(adc->regs + STM32H7_ADC_CFGR, STM32H7_EXTEN | > - STM32H7_DMNGT); > + /* > + * Trigger detection disabled (conversion can be launched in SW) > + * STM32H7_DMNGT is equivalent to STM32MP13_DMAEN & STM32MP13_DMACFG > + */ > + clrbits_le32(adc->regs + STM32H7_ADC_CFGR, STM32H7_EXTEN | STM32H7_DMNGT); > adc->active_channel = channel; > > return 0; > @@ -206,7 +246,7 @@ static int stm32_adc_selfcalib(struct udevice *dev) > { > struct stm32_adc *adc = dev_get_priv(dev); > int ret; > - u32 val; > + u32 val, mask; > > /* > * Select calibration mode: > @@ -231,7 +271,10 @@ static int stm32_adc_selfcalib(struct udevice *dev) > * - Linearity calibration (needs to be done only once for single/diff) > * will run simultaneously with offset calibration. > */ > - setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADCALDIF | STM32H7_ADCALLIN); > + mask = STM32H7_ADCALDIF; > + if (adc->cfg->has_linearcal) > + mask |= STM32H7_ADCALLIN; > + setbits_le32(adc->regs + STM32H7_ADC_CR, mask); > > /* Start calibration, then wait for completion */ > setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADCAL); > @@ -394,14 +437,28 @@ static const struct adc_ops stm32_adc_ops = { > }; > > static const struct stm32_adc_cfg stm32h7_adc_cfg = { > + .regs = &stm32h7_adc_regspec, > .num_bits = 16, > .max_channels = STM32_ADC_CH_MAX, > + .has_boostmode = true, > + .has_linearcal = true, > + .has_presel = true, > }; > > static const struct stm32_adc_cfg stm32mp1_adc_cfg = { > + .regs = &stm32h7_adc_regspec, > .num_bits = 16, > .max_channels = STM32_ADC_CH_MAX, > .has_vregready = true, > + .has_boostmode = true, > + .has_linearcal = true, > + .has_presel = true, > +}; > + > +static const struct stm32_adc_cfg stm32mp13_adc_cfg = { > + .regs = &stm32mp13_adc_regspec, > + .num_bits = 12, > + .max_channels = STM32_ADC_CH_MAX - 1, > }; > > static const struct udevice_id stm32_adc_ids[] = { > @@ -409,6 +466,8 @@ static const struct udevice_id stm32_adc_ids[] = { > .data = (ulong)&stm32h7_adc_cfg }, > { .compatible = "st,stm32mp1-adc", > .data = (ulong)&stm32mp1_adc_cfg }, > + { .compatible = "st,stm32mp13-adc", > + .data = (ulong)&stm32mp13_adc_cfg }, > {} > }; > only minor  remarks Reviewed-by: Patrick Delaunay Thanks Patrick