* [U-Boot-Users] PQ2FADS-VR 2nd Ethernet
@ 2004-07-16 22:11 Jihua Cheng
2004-07-17 22:53 ` Yuli Barcohen
0 siblings, 1 reply; 10+ messages in thread
From: Jihua Cheng @ 2004-07-16 22:11 UTC (permalink / raw)
To: u-boot
Hi,
I have a PQ2FADS-VR board which u-boot 1.0.0 runs well. Ethernet port1(FCC2) and Serial port1(SCC1) run pretty well.
I am trying to make Ethernet port2(FCC3) work. In the configuration file mpc8260ads.h, I added
#undef CONFIG_ETHER_INDEX
#define CONFIG_ETHER_INDEX 3
#if (CONFIG_ETHER_INDEX == 3)
# define CFG_CMXFCR_MASK (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16) /* Clk15 and Clk16 for Rx and Tx*/
# define CFG_CPMFCR_RAMTYPE 0
# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
#endif
And in board\mpc8260ads\mpc8260ads.c, I enabled the parall portC pin PC16 and PC17; PortB PB4~PB17. The new definition for portB and portC are
/* Port B configuration */
{ /* conf ppar psor pdir podr pdat */
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
/* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
/* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
/* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
/* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
/* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */
/* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
/* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
},
/* Port C */
{ /* conf ppar psor pdir podr pdat */
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
/* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* RX Clk15 jhc&m*/
/* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* Tx Clock (CLK16) */
/* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
/* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT970 FETHMDC */
/* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
}.
However, Ethernet port2 on SCC3 still does not work.
Could anyone tell me where I am wrong, or what I missed?
Thanks a lot!
Regards,
Charles
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot-Users] PQ2FADS-VR 2nd Ethernet
2004-07-16 22:11 Jihua Cheng
@ 2004-07-17 22:53 ` Yuli Barcohen
0 siblings, 0 replies; 10+ messages in thread
From: Yuli Barcohen @ 2004-07-17 22:53 UTC (permalink / raw)
To: u-boot
>>>>> Jihua Cheng writes:
Jihua> Hi, I have a PQ2FADS-VR board which u-boot 1.0.0
Upgrade to the top of CVS before you start changing anything. 1.0.0 is
too old.
Jihua> runs well. Ethernet port1(FCC2) and Serial port1(SCC1) run
Jihua> pretty well.
Jihua> I am trying to make Ethernet port2(FCC3) work. In the
Jihua> configuration file mpc8260ads.h, I added
[...code deleted...]
Jihua> And in board\mpc8260ads\mpc8260ads.c, I enabled the parall
Jihua> portC pin PC16 and PC17; PortB PB4~PB17. The new definition
Jihua> for portB and portC are
[...code deleted...]
Jihua> However, Ethernet port2 on SCC3 still does not work.
Jihua> Could anyone tell me where I am wrong, or what I missed?
First of all, "does not work" is not good problem description. Could you
explain what happens exactly? On this board, there are several more
things which can require initialisation. Check BCSR and PHY. If you
upgrade to CVS top, you'll see what's done for FCC2. To check PHY state,
you can use mii command.
--
========================================================================
Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader
yuli at arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel
========================================================================
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot-Users] PQ2FADS-VR 2nd Ethernet
@ 2004-07-19 15:03 Jihua Cheng
2004-07-19 15:47 ` Yuli Barcohen
2004-07-19 15:56 ` Rune Torgersen
0 siblings, 2 replies; 10+ messages in thread
From: Jihua Cheng @ 2004-07-19 15:03 UTC (permalink / raw)
To: u-boot
Yuli,
Thanks very much!
Here is the sympotoms.
Based on the PQ2FADS-VR schematic, I route parallel portC pin PC17(Clk 15 for RX) and pin PC16(Clk16 for TX) for FCC3. PortB PB4~PB17 are enabled for FCC3. When I use ping command, I got "fec: tx error!" message in the console. I found the message is from fec_send(...) at cpu/mpc8260/ether_fcc.c. It seems CPM did not send out the data to Phy.
1) I check BCSR3. Both FETHIEN2 and FETH2_RST are 1.
2) Phy Register seems OK (Reg0 = 0x2100, reg1 = 0x7809).
3) I check PortB PB4~PB17. Dedicated Pin setting seems OK.
Where do I need to check?
I appreciate your help!
Regards,
Jihua
-----Original Message-----
From: Yuli Barcohen [mailto:yuli at arabellasw.com]
Sent: Saturday, July 17, 2004 3:53 PM
To: Jihua Cheng
Cc: u-boot-users at lists.sourceforge.net
Subject: Re: [U-Boot-Users] PQ2FADS-VR 2nd Ethernet
>>>>> Jihua Cheng writes:
Jihua> Hi, I have a PQ2FADS-VR board which u-boot 1.0.0
Upgrade to the top of CVS before you start changing anything. 1.0.0 is
too old.
Jihua> runs well. Ethernet port1(FCC2) and Serial port1(SCC1) run
Jihua> pretty well.
Jihua> I am trying to make Ethernet port2(FCC3) work. In the
Jihua> configuration file mpc8260ads.h, I added
[...code deleted...]
Jihua> And in board\mpc8260ads\mpc8260ads.c, I enabled the parall
Jihua> portC pin PC16 and PC17; PortB PB4~PB17. The new definition
Jihua> for portB and portC are
[...code deleted...]
Jihua> However, Ethernet port2 on SCC3 still does not work.
Jihua> Could anyone tell me where I am wrong, or what I missed?
First of all, "does not work" is not good problem description. Could you
explain what happens exactly? On this board, there are several more
things which can require initialisation. Check BCSR and PHY. If you
upgrade to CVS top, you'll see what's done for FCC2. To check PHY state,
you can use mii command.
--
========================================================================
Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader
yuli at arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel
========================================================================
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot-Users] PQ2FADS-VR 2nd Ethernet
2004-07-19 15:03 [U-Boot-Users] PQ2FADS-VR 2nd Ethernet Jihua Cheng
@ 2004-07-19 15:47 ` Yuli Barcohen
2004-07-19 15:56 ` Rune Torgersen
1 sibling, 0 replies; 10+ messages in thread
From: Yuli Barcohen @ 2004-07-19 15:47 UTC (permalink / raw)
To: u-boot
>>>>> Jihua Cheng writes:
Jihua> Yuli, Thanks very much!
Jihua> Here is the sympotoms.
Jihua> Based on the PQ2FADS-VR schematic, I route parallel portC pin
Jihua> PC17(Clk 15 for RX) and pin PC16(Clk16 for TX) for
Jihua> FCC3. PortB PB4~PB17 are enabled for FCC3. When I use ping
Jihua> command, I got "fec: tx error!" message in the console. I
Jihua> found the message is from fec_send(...) at
Jihua> cpu/mpc8260/ether_fcc.c. It seems CPM did not send out the
Jihua> data to Phy.
This usually indicates that there is no Tx clock, probably because the
PHY does not provide it.
Jihua> 1) I check BCSR3. Both FETHIEN2 and FETH2_RST are 1.
FETHIEN2=1 means that the PHY is isolated after power-up. This is not
what you want. Set FETHIEN2 to zero and reset PHY by toggling FETH2_RST.
Jihua> 2) Phy Register seems OK (Reg0 = 0x2100, reg1 = 0x7809).
It's not completely OK because auto-negotiation is disabled. It's can be
a result of above mentioned isolation. Check what happens after enabling
the PHY, and set as necessary.
Jihua> 3) I check PortB PB4~PB17. Dedicated Pin setting seems OK.
Jihua> Where do I need to check?
Jihua> I appreciate your help!
--
========================================================================
Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader
yuli at arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel
========================================================================
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot-Users] PQ2FADS-VR 2nd Ethernet
2004-07-19 15:03 [U-Boot-Users] PQ2FADS-VR 2nd Ethernet Jihua Cheng
2004-07-19 15:47 ` Yuli Barcohen
@ 2004-07-19 15:56 ` Rune Torgersen
1 sibling, 0 replies; 10+ messages in thread
From: Rune Torgersen @ 2004-07-19 15:56 UTC (permalink / raw)
To: u-boot
On Mon, 2004-07-19 at 10:03, Jihua Cheng wrote:
> Where do I need to check?
The TX error message is very typical if there is no TX clock from the
phy to the FCC.
* Check your TC clock
* if that is OK, Check the Port settings for the RX and TX clock
* Check the software settings, make sure they use the right clocks.
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot-Users] PQ2FADS-VR 2nd Ethernet
@ 2004-07-19 17:39 Jihua Cheng
2004-07-19 17:55 ` Yuli Barcohen
0 siblings, 1 reply; 10+ messages in thread
From: Jihua Cheng @ 2004-07-19 17:39 UTC (permalink / raw)
To: u-boot
Yuli,
Thanks very much for your instruction.
It seems I move further, however I still do not make Ethernet port2 works fine. Following is the my modification and the symptom.
1) I changed the BCSRs bit FETHIEN2 to 0, reset the Ethernet Port2 (Phy addr 3) to enable auto-negatiation. Now, the MII reg0 = 0x3100, reg1=0x782D.
IP Addr 172.18.100.54 does exist. when I enable FCC2 and ping 172.18.100.54, ping success.
When I "ping 172.18.100.54", the message "fex: tx error" is gone. It seems TX is fine. Is it correct?
2) However, "ping 172.18.100.54" fail. the message "ping failed; host 172.18.100.54" is not alive.
FCC3 Rx Clock is set to CLK15. PortB4~17, PortC16~17 are enabled.
I added a debug message to fec_recv(...) in cpu\mpc8260\ether_fcc.c, as follows.
static int fec_recv(struct eth_device* dev)
{
int length;
for (;;)
{
if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
length = -1;
#ifdef ET_DEBUG
printf("%s::%s Nothing Rcv\n", __FILE__, __FUNCTION__); /*Added Debug*/
#endif
break; /* nothing received - leave for() loop */
}
.....
}
I got "ether_fcc.c::fec_recv Nothing Rcv" message.
The following few lines for the CPM clock route in added in include\configs\MPC8260ADS.h:
#if (CONFIG_ETHER_INDEX == 3)
/*
* - Rx-CLK is CLK15
* - Tx-CLK is CLK16
* - Select bus for bd/buffers (see 28-13)
* - Full duplex
*/
# define CFG_CMXFCR_MASK (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16)
# define CFG_CPMFCR_RAMTYPE 0
# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
#endif /* CONFIG_ETHER_INDEX */
Ethernet port2 dedicated Pin setting for PortB 4~17 and PortC 17~17 are enabled. The definition in board\mpc8260ads\mpc8260ads.c is shown as follows:
/* Port B configuration */
{ /* conf ppar psor pdir podr pdat */
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
/* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV*/
/* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
/* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
/* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
/* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */
/* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
/* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
},
/* Port C */
{ /* conf ppar psor pdir podr pdat */
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
/* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* RX Clk15*/
/* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* Tx Clock (CLK16) */
/* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
/* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT970 FETHMDC */
/* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
},
Thanks a lot!
Regards,
Charles
-----Original Message-----
From: Yuli Barcohen [mailto:yuli at arabellasw.com]
Sent: Monday, July 19, 2004 8:47 AM
To: Jihua Cheng
Cc: u-boot-users at lists.sourceforge.net
Subject: RE: [U-Boot-Users] PQ2FADS-VR 2nd Ethernet
>>>>> Jihua Cheng writes:
Jihua> Yuli, Thanks very much!
Jihua> Here is the sympotoms.
Jihua> Based on the PQ2FADS-VR schematic, I route parallel portC pin
Jihua> PC17(Clk 15 for RX) and pin PC16(Clk16 for TX) for
Jihua> FCC3. PortB PB4~PB17 are enabled for FCC3. When I use ping
Jihua> command, I got "fec: tx error!" message in the console. I
Jihua> found the message is from fec_send(...) at
Jihua> cpu/mpc8260/ether_fcc.c. It seems CPM did not send out the
Jihua> data to Phy.
This usually indicates that there is no Tx clock, probably because the
PHY does not provide it.
Jihua> 1) I check BCSR3. Both FETHIEN2 and FETH2_RST are 1.
FETHIEN2=1 means that the PHY is isolated after power-up. This is not
what you want. Set FETHIEN2 to zero and reset PHY by toggling FETH2_RST.
Jihua> 2) Phy Register seems OK (Reg0 = 0x2100, reg1 = 0x7809).
It's not completely OK because auto-negotiation is disabled. It's can be
a result of above mentioned isolation. Check what happens after enabling
the PHY, and set as necessary.
Jihua> 3) I check PortB PB4~PB17. Dedicated Pin setting seems OK.
Jihua> Where do I need to check?
Jihua> I appreciate your help!
--
========================================================================
Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader
yuli at arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel
========================================================================
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot-Users] PQ2FADS-VR 2nd Ethernet
2004-07-19 17:39 Jihua Cheng
@ 2004-07-19 17:55 ` Yuli Barcohen
0 siblings, 0 replies; 10+ messages in thread
From: Yuli Barcohen @ 2004-07-19 17:55 UTC (permalink / raw)
To: u-boot
>>>>> Jihua Cheng writes:
Jihua> Yuli, Thanks very much for your instruction. It seems I move
Jihua> further, however I still do not make Ethernet port2 works
Jihua> fine. Following is the my modification and the symptom.
Jihua> 1) I changed the BCSRs bit FETHIEN2 to 0, reset the Ethernet
Jihua> Port2 (Phy addr 3) to enable auto-negatiation. Now, the
Jihua> MII reg0 = 0x3100, reg1=0x782D. IP Addr 172.18.100.54
Jihua> does exist. when I enable FCC2 and ping 172.18.100.54,
Jihua> ping success. When I "ping 172.18.100.54", the message
Jihua> "fex: tx error" is gone. It seems TX is fine. Is it
Jihua> correct?
Probably it is. Try a sniffer (ethereal, tcpdump) on the host to see if
anything is transmitted by the board.
Jihua> 2) However, "ping 172.18.100.54" fail. the message "ping
Jihua> failed; host 172.18.100.54" is not alive. FCC3 Rx Clock
Jihua> is set to CLK15. PortB4~17, PortC16~17 are enabled.
Why do you think that the problem is still at the hardware level? What
are the board's IP address, MAC address, subnet mask, etc. (just type
printenv). You write that 172.18.100.54 exists but you don't write
anything about the host to which this address belongs. Is it a Linux
machine? Does it respond to pings at all? What's about subnets? There
are too many possible reasons for ping failure.
[...code deleted...]
--
========================================================================
Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader
yuli at arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel
========================================================================
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot-Users] PQ2FADS-VR 2nd Ethernet
@ 2004-07-19 18:44 Jihua Cheng
0 siblings, 0 replies; 10+ messages in thread
From: Jihua Cheng @ 2004-07-19 18:44 UTC (permalink / raw)
To: u-boot
Yuli,
Thanks so much for your help.
Let me explan the experiments which I did.
1) 172.18.100.54 is a redhat linux. Netmask is 255:255:255:0. I verified by use of ifconfig command.
1) Here is the environment variable for PQ2FADS-VR.
=> printenv
bootdelay=5
baudrate=38400
ethaddr=00:30:d4:00:01:02
g=bootm 100000
ipaddr=172.18.100.99
serverip=172.18.100.54
stdin=serial
stdout=serial
stderr=serial
2) I use arp command and found "172.18.100.99 ether 00:30:d4:00:01:02 C eth0" is in the ARP display.
When I use ifconfig, I found RX packets and Tx packets increase the same number.
It seems Linux host received the ping from Pq2FADS-VR board and replied.
4) Why I suspect some hardware setting is probabily quite right is
I use same U-boot environment parameter and linux machine(172.18.100.54) for ethernet port1 with FCC2, the ping works fine.
I only the u-boot to use FCC3 for ethernet port2, ping fails.
5) I check the RxBD status. I found the Empty bit is 1, means no data received in Rx.
Could I suspect something is wrong for FCC3 Rx portion?
Could you please tell me what I must to check, or what I missed?
I greatly appreciate your help.
Reagrds,
Charles
-----Original Message-----
From: Yuli Barcohen [mailto:yuli at arabellasw.com]
Sent: Monday, July 19, 2004 10:55 AM
To: Jihua Cheng
Cc: u-boot-users at lists.sourceforge.net
Subject: RE: [U-Boot-Users] PQ2FADS-VR 2nd Ethernet
>>>>> Jihua Cheng writes:
Jihua> Yuli, Thanks very much for your instruction. It seems I move
Jihua> further, however I still do not make Ethernet port2 works
Jihua> fine. Following is the my modification and the symptom.
Jihua> 1) I changed the BCSRs bit FETHIEN2 to 0, reset the Ethernet
Jihua> Port2 (Phy addr 3) to enable auto-negatiation. Now, the
Jihua> MII reg0 = 0x3100, reg1=0x782D. IP Addr 172.18.100.54
Jihua> does exist. when I enable FCC2 and ping 172.18.100.54,
Jihua> ping success. When I "ping 172.18.100.54", the message
Jihua> "fex: tx error" is gone. It seems TX is fine. Is it
Jihua> correct?
Probably it is. Try a sniffer (ethereal, tcpdump) on the host to see if
anything is transmitted by the board.
Jihua> 2) However, "ping 172.18.100.54" fail. the message "ping
Jihua> failed; host 172.18.100.54" is not alive. FCC3 Rx Clock
Jihua> is set to CLK15. PortB4~17, PortC16~17 are enabled.
Why do you think that the problem is still at the hardware level? What
are the board's IP address, MAC address, subnet mask, etc. (just type
printenv). You write that 172.18.100.54 exists but you don't write
anything about the host to which this address belongs. Is it a Linux
machine? Does it respond to pings at all? What's about subnets? There
are too many possible reasons for ping failure.
[...code deleted...]
--
========================================================================
Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader
yuli at arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel
========================================================================
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot-Users] PQ2FADS-VR 2nd Ethernet
@ 2004-07-20 15:04 Jihua Cheng
2004-07-20 15:18 ` Yuli Barcohen
0 siblings, 1 reply; 10+ messages in thread
From: Jihua Cheng @ 2004-07-20 15:04 UTC (permalink / raw)
To: u-boot
Yuli,
We finally found the reason of the 2nd ethernet is some hardware parts got some problem.
Now, the 2nd ethernet port works fine.
I noticed in include\configs\MPC8260ADS.h
#define FETHIEN2 0x01000000
should be changed to
#define FETHIEN2 0x10000000 /*BCSR3 bit3 FETHIEN2*/
Thanks a lot for your advice and help!
charles
-----Original Message-----
From: Yuli Barcohen [mailto:yuli at arabellasw.com]
Sent: Monday, July 19, 2004 10:55 AM
To: Jihua Cheng
Cc: u-boot-users at lists.sourceforge.net
Subject: RE: [U-Boot-Users] PQ2FADS-VR 2nd Ethernet
>>>>> Jihua Cheng writes:
Jihua> Yuli, Thanks very much for your instruction. It seems I move
Jihua> further, however I still do not make Ethernet port2 works
Jihua> fine. Following is the my modification and the symptom.
Jihua> 1) I changed the BCSRs bit FETHIEN2 to 0, reset the Ethernet
Jihua> Port2 (Phy addr 3) to enable auto-negatiation. Now, the
Jihua> MII reg0 = 0x3100, reg1=0x782D. IP Addr 172.18.100.54
Jihua> does exist. when I enable FCC2 and ping 172.18.100.54,
Jihua> ping success. When I "ping 172.18.100.54", the message
Jihua> "fex: tx error" is gone. It seems TX is fine. Is it
Jihua> correct?
Probably it is. Try a sniffer (ethereal, tcpdump) on the host to see if
anything is transmitted by the board.
Jihua> 2) However, "ping 172.18.100.54" fail. the message "ping
Jihua> failed; host 172.18.100.54" is not alive. FCC3 Rx Clock
Jihua> is set to CLK15. PortB4~17, PortC16~17 are enabled.
Why do you think that the problem is still at the hardware level? What
are the board's IP address, MAC address, subnet mask, etc. (just type
printenv). You write that 172.18.100.54 exists but you don't write
anything about the host to which this address belongs. Is it a Linux
machine? Does it respond to pings at all? What's about subnets? There
are too many possible reasons for ping failure.
[...code deleted...]
--
========================================================================
Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader
yuli at arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel
========================================================================
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot-Users] PQ2FADS-VR 2nd Ethernet
2004-07-20 15:04 Jihua Cheng
@ 2004-07-20 15:18 ` Yuli Barcohen
0 siblings, 0 replies; 10+ messages in thread
From: Yuli Barcohen @ 2004-07-20 15:18 UTC (permalink / raw)
To: u-boot
>>>>> Jihua Cheng writes:
Jihua> Yuli, We finally found the reason of the 2nd ethernet is some
Jihua> hardware parts got some problem. Now, the 2nd ethernet port
Jihua> works fine.
Great.
Jihua> I noticed in include\configs\MPC8260ADS.h
Jihua> #define FETHIEN2 0x01000000
Jihua> should be changed to
Jihua> #define FETHIEN2 0x10000000 /*BCSR3 bit3 FETHIEN2*/
It was fixed in CVS long time ago. If you upgraded to the latest
version, you'd have this fix included.
Jihua> Thanks a lot for your advice and help!
--
========================================================================
Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader
yuli at arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel
========================================================================
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2004-07-20 15:18 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2004-07-19 15:03 [U-Boot-Users] PQ2FADS-VR 2nd Ethernet Jihua Cheng
2004-07-19 15:47 ` Yuli Barcohen
2004-07-19 15:56 ` Rune Torgersen
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2004-07-20 15:04 Jihua Cheng
2004-07-20 15:18 ` Yuli Barcohen
2004-07-19 18:44 Jihua Cheng
2004-07-19 17:39 Jihua Cheng
2004-07-19 17:55 ` Yuli Barcohen
2004-07-16 22:11 Jihua Cheng
2004-07-17 22:53 ` Yuli Barcohen
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