Re: [PATCH v2 1/4] riscv: dts: Update memory configuration

[<Conor.Dooley@microchip.com>]

On 22/10/2022 12:21, Conor Dooley wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On Fri, Oct 21, 2022 at 12:29:19PM +0530, Padmarao Begari wrote:
>> In the v2022.10 Icicle reference design, the seg registers are going to be
> 
> Hey Padmarao,
> Since the release was done the other day I think that this should be
> s/are going to be/have been
> 
>> changed, resulting in a required change to the memory map.
>> A small 4MB reservation is made at the end of 32-bit DDR to provide some
>> memory for the HSS to use, so that it can cache its payload between
>> reboots of a specific context.
>>
>> Co-developed-by: Conor Dooley <conor.dooley@microchip.com>
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>> Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
>> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>> ---
>>  arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 70 ++++----------------
>>  1 file changed, 14 insertions(+), 56 deletions(-)
>>
>> diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
>> index 287ef3d23b..876c475069 100644
>> --- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
>> +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
>> @@ -1,6 +1,6 @@
>>  // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>>  /*
>> - * Copyright (C) 2021 Microchip Technology Inc.
>> + * Copyright (C) 2021-2022 Microchip Technology Inc.
>>   * Padmarao Begari <padmarao.begari@microchip.com>
>>   */
>>
>> @@ -28,70 +28,28 @@
>>               timebase-frequency = <RTCCLK_FREQ>;
>>       };
> 
> FWIW I think we should add the compatible that the linux dt has,
> signifying that this memory layout is compatible with the v2022.10
> release and later (w/ appropriate line-wrapping ofc):
> compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit", "microchip,mpfs";
> 
> Other than that:
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> 
>>
>> -     reserved-memory {
>> -             ranges;
>> -             #size-cells = <2>;
>> -             #address-cells = <2>;
>> -
>> -             fabricbuf0: fabricbuf@0 {
>> -                     compatible = "shared-dma-pool";
>> -                     reg = <0x0 0xae000000 0x0 0x2000000>;
>> -                     label = "fabricbuf0-ddr-c";
>> -             };
>> -
>> -             fabricbuf1: fabricbuf@1 {
>> -                     compatible = "shared-dma-pool";
>> -                     reg = <0x0 0xc0000000 0x0 0x8000000>;
>> -                     label = "fabricbuf1-ddr-nc";
>> -             };
>> -
>> -             fabricbuf2: fabricbuf@2 {
>> -                     compatible = "shared-dma-pool";
>> -                     reg = <0x0 0xd8000000 0x0 0x8000000>;
>> -                     label = "fabricbuf2-ddr-nc-wcb";
>> -             };
>> -     };
>> -
>> -     udmabuf0 {
>> -             compatible = "ikwzm,u-dma-buf";
>> -             device-name = "udmabuf-ddr-c0";
>> -             minor-number = <0>;
>> -             size = <0x0 0x2000000>;
>> -             memory-region = <&fabricbuf0>;
>> -             sync-mode = <3>;
>> -     };
>> -
>> -     udmabuf1 {
>> -             compatible = "ikwzm,u-dma-buf";
>> -             device-name = "udmabuf-ddr-nc0";
>> -             minor-number = <1>;
>> -             size = <0x0 0x8000000>;
>> -             memory-region = <&fabricbuf1>;
>> -             sync-mode = <3>;
>> -     };
>> -
>> -     udmabuf2 {
>> -             compatible = "ikwzm,u-dma-buf";
>> -             device-name = "udmabuf-ddr-nc-wcb0";
>> -             minor-number = <2>;
>> -             size = <0x0 0x8000000>;
>> -             memory-region = <&fabricbuf2>;
>> -             sync-mode = <3>;
>> -     };
>> -
>>       ddrc_cache_lo: memory@80000000 {
>>               device_type = "memory";
>> -             reg = <0x0 0x80000000 0x0 0x2e000000>;
>> -             clocks = <&clkcfg CLK_DDRC>;
>> +             reg = <0x0 0x80000000 0x0 0x40000000>;
>>               status = "okay";
>>       };
>>
>>       ddrc_cache_hi: memory@1000000000 {

Sorry for not noticing prior, but this should bee changed too to match
the reg property shouldn't it..

>>               device_type = "memory";
>> -             reg = <0x10 0x0 0x0 0x40000000>;
>> -             clocks = <&clkcfg CLK_DDRC>;
>> +             reg = <0x10 0x40000000 0x0 0x40000000>;
>>               status = "okay";
>>       };
>> +
>> +     reserved-memory {
>> +             #address-cells = <2>;
>> +             #size-cells = <2>;
>> +             ranges;
>> +
>> +             hss_payload: region@BFC00000 {
>> +                     reg = <0x0 0xBFC00000 0x0 0x400000>;
>> +                     no-map;
>> +             };
>> +     };
>>  };
>>
>>  &uart1 {
>> --
>> 2.25.1
>>