[U-Boot] [PATCH 3/4] arm: make relocation section symbols compiler-generated

Albert ARIBAUD
2013-05-10T21:56:51Z

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
---
arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds | 15 ++++++++++++---
arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds | 15 ++++++++++++---
arch/arm/cpu/ixp/u-boot.lds | 18 ++++++++++++++----
arch/arm/cpu/u-boot-spl.lds | 18 ++++++++++++++----
arch/arm/cpu/u-boot.lds | 18 ++++++++++++++----
arch/arm/lib/sections.c | 3 +++
board/actux1/u-boot.lds | 18 ++++++++++++++----
board/actux2/u-boot.lds | 18 ++++++++++++++----
board/actux3/u-boot.lds | 19 +++++++++++++++----
board/ait/cam_enc_4xx/u-boot-spl.lds | 16 +++++++++++++---
board/davinci/da8xxevm/u-boot-spl-da850evm.lds | 16 +++++++++++++---
board/dvlhost/u-boot.lds | 18 ++++++++++++++----
board/freescale/mx31ads/u-boot.lds | 18 ++++++++++++++----
board/vpac270/u-boot-spl.lds | 18 ++++++++++++++----
14 files changed, 180 insertions(+), 48 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
index 673c725..b078387 100644
--- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
@@ -51,14 +51,23 @@ SECTIONS

. = ALIGN(4);

+ .rel_dyn_start : {
+ *(.__rel_dyn_start);
+ }
+
.rel.dyn : {
- __rel_dyn_start = .;
*(.rel*)
- __rel_dyn_end = .;
+ }
+
+ .rel_dyn_end : {
+ *(.__rel_dyn_end);
+ }
+
+ .dynsym_start : {
+ *(.__dynsym_start);
}

.dynsym : {
- __dynsym_start = .;
*(.dynsym)
}

diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
index 967a135..a24879f 100644
--- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
@@ -51,14 +51,23 @@ SECTIONS

. = ALIGN(4);

+ .rel_dyn_start : {
+ *(.__rel_dyn_start);
+ }
+
.rel.dyn : {
- __rel_dyn_start = .;
*(.rel*)
- __rel_dyn_end = .;
+ }
+
+ .rel_dyn_end : {
+ *(.__rel_dyn_end);
+ }
+
+ .dynsym_start : {
+ *(.__dynsym_start);
}

.dynsym : {
- __dynsym_start = .;
*(.dynsym)
}

diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds
index 1a0ba17..1315b41 100644
--- a/arch/arm/cpu/ixp/u-boot.lds
+++ b/arch/arm/cpu/ixp/u-boot.lds
@@ -60,14 +60,24 @@ SECTIONS
*(.__image_copy_end);
}

+ .rel_dyn_start : {
+ __rel_dyn_base = .;
+ *(.__rel_dyn_start);
+ }
+
.rel.dyn : {
- __rel_dyn_start = .;
*(.rel*)
- __rel_dyn_end = .;
+ }
+
+ .rel_dyn_end : {
+ *(.__rel_dyn_end);
+ }
+
+ .dynsym_start : {
+ *(.__dynsym_start);
}

.dynsym : {
- __dynsym_start = .;
*(.dynsym)
}

@@ -78,7 +88,7 @@ SECTIONS
* __bss_base and __bss_limit are for linker only (overlay ordering)
*/

- .bss_start __rel_dyn_start (OVERLAY) : {
+ .bss_start __rel_dyn_base (OVERLAY) : {
KEEP(*(.__bss_start));
__bss_base = .;
}
diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds
index 87341c1..87e5655 100644
--- a/arch/arm/cpu/u-boot-spl.lds
+++ b/arch/arm/cpu/u-boot-spl.lds
@@ -51,20 +51,30 @@ SECTIONS

__image_copy_end = .;

+ .rel_dyn_start : {
+ __rel_dyn_base = .;
+ *(.__rel_dyn_start);
+ }
+
.rel.dyn : {
- __rel_dyn_start = .;
*(.rel*)
- __rel_dyn_end = .;
+ }
+
+ .rel_dyn_end : {
+ *(.__rel_dyn_end);
+ }
+
+ .dynsym_start : {
+ *(.__dynsym_start);
}

.dynsym : {
- __dynsym_start = .;
*(.dynsym)
}

_end = .;

- .bss __rel_dyn_start (OVERLAY) : {
+ .bss __rel_dyn_base (OVERLAY) : {
__bss_start = .;
*(.bss*)
. = ALIGN(4);
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 5b43621..fbac4d1 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -62,14 +62,24 @@ SECTIONS
*(.__image_copy_end);
}

+ .rel_dyn_start : {
+ __rel_dyn_base = .;
+ *(.__rel_dyn_start);
+ }
+
.rel.dyn : {
- __rel_dyn_start = .;
*(.rel*)
- __rel_dyn_end = .;
+ }
+
+ .rel_dyn_end : {
+ *(.__rel_dyn_end);
+ }
+
+ .dynsym_start : {
+ *(.__dynsym_start);
}

.dynsym : {
- __dynsym_start = .;
*(.dynsym)
}

@@ -89,7 +99,7 @@ SECTIONS
* __bss_base and __bss_limit are for linker only (overlay ordering)
*/

- .bss_start __rel_dyn_start (OVERLAY) : {
+ .bss_start __rel_dyn_base (OVERLAY) : {
KEEP(*(.__bss_start));
__bss_base = .;
}
diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c
index 80a0c38..c1ef867 100644
--- a/arch/arm/lib/sections.c
+++ b/arch/arm/lib/sections.c
@@ -39,3 +39,6 @@ char __bss_start[0] __attribute__((used, section(".__bss_start")));
char __bss_end[0] __attribute__((used, section(".__bss_end")));
char __image_copy_start[0] __attribute__((used, section(".__image_copy_start")));
char __image_copy_end[0] __attribute__((used, section(".__image_copy_end")));
+char __rel_dyn_start[0] __attribute__((used, section(".__rel_dyn_start")));
+char __rel_dyn_end[0] __attribute__((used, section(".__rel_dyn_end")));
+char __dynsym_start[0] __attribute__((used, section(".__dynsym_start")));
diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds
index ef4a25b..0327c27 100644
--- a/board/actux1/u-boot.lds
+++ b/board/actux1/u-boot.lds
@@ -64,14 +64,24 @@ SECTIONS

__image_copy_end = .;

+ .rel_dyn_start : {
+ __rel_dyn_base = .;
+ *(.__rel_dyn_start);
+ }
+
.rel.dyn : {
- __rel_dyn_start = .;
*(.rel*)
- __rel_dyn_end = .;
+ }
+
+ .rel_dyn_end : {
+ *(.__rel_dyn_end);
+ }
+
+ .dynsym_start : {
+ *(.__dynsym_start);
}

.dynsym : {
- __dynsym_start = .;
*(.dynsym)
}

@@ -82,7 +92,7 @@ SECTIONS
* __bss_base and __bss_limit are for linker only (overlay ordering)
*/

- .bss_start __rel_dyn_start (OVERLAY) : {
+ .bss_start __rel_dyn_base (OVERLAY) : {
KEEP(*(.__bss_start));
__bss_base = .;
}
diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds
index 00ad8b7..a025bf1 100644
--- a/board/actux2/u-boot.lds
+++ b/board/actux2/u-boot.lds
@@ -64,14 +64,24 @@ SECTIONS

__image_copy_end = .;

+ .rel_dyn_start : {
+ __rel_dyn_base = .;
+ *(.__rel_dyn_start);
+ }
+
.rel.dyn : {
- __rel_dyn_start = .;
*(.rel*)
- __rel_dyn_end = .;
+ }
+
+ .rel_dyn_end : {
+ *(.__rel_dyn_end);
+ }
+
+ .dynsym_start : {
+ *(.__dynsym_start);
}

.dynsym : {
- __dynsym_start = .;
*(.dynsym)
}

@@ -82,7 +92,7 @@ SECTIONS
* __bss_base and __bss_limit are for linker only (overlay ordering)
*/

- .bss_start __rel_dyn_start (OVERLAY) : {
+ .bss_start __rel_dyn_base (OVERLAY) : {
KEEP(*(.__bss_start));
__bss_base = .;
}
diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds
index 44b990e..41510c4 100644
--- a/board/actux3/u-boot.lds
+++ b/board/actux3/u-boot.lds
@@ -64,14 +64,25 @@ SECTIONS

__image_copy_end = .;

+
+ .rel_dyn_start : {
+ __rel_dyn_base = .;
+ *(.__rel_dyn_start);
+ }
+
.rel.dyn : {
- __rel_dyn_start = .;
*(.rel*)
- __rel_dyn_end = .;
+ }
+
+ .rel_dyn_end : {
+ *(.__rel_dyn_end);
+ }
+
+ .dynsym_start : {
+ *(.__dynsym_start);
}

.dynsym : {
- __dynsym_start = .;
*(.dynsym)
}

@@ -82,7 +93,7 @@ SECTIONS
* __bss_base and __bss_limit are for linker only (overlay ordering)
*/

- .bss_start __rel_dyn_start (OVERLAY) : {
+ .bss_start __rel_dyn_base (OVERLAY) : {
KEEP(*(.__bss_start));
__bss_base = .;
}
diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds
index 1daa1b3..68c65c1 100644
--- a/board/ait/cam_enc_4xx/u-boot-spl.lds
+++ b/board/ait/cam_enc_4xx/u-boot-spl.lds
@@ -48,14 +48,24 @@ SECTIONS
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
. = ALIGN(4);
+
+ .rel_dyn_start : {
+ *(.__rel_dyn_start);
+ } >.sram
+
.rel.dyn : {
- __rel_dyn_start = .;
*(.rel*)
- __rel_dyn_end = .;
+ } >.sram
+
+ .rel_dyn_end : {
+ *(.__rel_dyn_end);
+ } >.sram
+
+ .dynsym_start : {
+ *(.__dynsym_start);
} >.sram

.dynsym : {
- __dynsym_start = .;
*(.dynsym)
} >.sram

diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
index b1b8701..56c276f 100644
--- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
+++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
@@ -49,14 +49,24 @@ SECTIONS
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram

. = ALIGN(4);
+
+ .rel_dyn_start : {
+ *(.__rel_dyn_start);
+ } >.sram
+
.rel.dyn : {
- __rel_dyn_start = .;
*(.rel*)
- __rel_dyn_end = .;
+ } >.sram
+
+ .rel_dyn_end : {
+ *(.__rel_dyn_end);
+ } >.sram
+
+ .dynsym_start : {
+ *(.__dynsym_start);
} >.sram

.dynsym : {
- __dynsym_start = .;
*(.dynsym)
} >.sram

diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds
index 6d4b187..ea00c09 100644
--- a/board/dvlhost/u-boot.lds
+++ b/board/dvlhost/u-boot.lds
@@ -64,14 +64,24 @@ SECTIONS

__image_copy_end = .;

+ .rel_dyn_start : {
+ __rel_dyn_base = .;
+ *(.__rel_dyn_start);
+ }
+
.rel.dyn : {
- __rel_dyn_start = .;
*(.rel*)
- __rel_dyn_end = .;
+ }
+
+ .rel_dyn_end : {
+ *(.__rel_dyn_end);
+ }
+
+ .dynsym_start : {
+ *(.__dynsym_start);
}

.dynsym : {
- __dynsym_start = .;
*(.dynsym)
}

@@ -82,7 +92,7 @@ SECTIONS
* __bss_base and __bss_limit are for linker only (overlay ordering)
*/

- .bss_start __rel_dyn_start (OVERLAY) : {
+ .bss_start __rel_dyn_base (OVERLAY) : {
KEEP(*(.__bss_start));
__bss_base = .;
}
diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds
index 4969960..092232f 100644
--- a/board/freescale/mx31ads/u-boot.lds
+++ b/board/freescale/mx31ads/u-boot.lds
@@ -67,14 +67,24 @@ SECTIONS

__image_copy_end = .;

+ .rel_dyn_start : {
+ __rel_dyn_base = .;
+ *(.__rel_dyn_start);
+ }
+
.rel.dyn : {
- __rel_dyn_start = .;
*(.rel*)
- __rel_dyn_end = .;
+ }
+
+ .rel_dyn_end : {
+ *(.__rel_dyn_end);
+ }
+
+ .dynsym_start : {
+ *(.__dynsym_start);
}

.dynsym : {
- __dynsym_start = .;
*(.dynsym)
}

@@ -85,7 +95,7 @@ SECTIONS
* __bss_base and __bss_limit are for linker only (overlay ordering)
*/

- .bss_start __rel_dyn_start (OVERLAY) : {
+ .bss_start __rel_dyn_base (OVERLAY) : {
KEEP(*(.__bss_start));
__bss_base = .;
}
diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds
index 61d1154..e341ce6 100644
--- a/board/vpac270/u-boot-spl.lds
+++ b/board/vpac270/u-boot-spl.lds
@@ -61,14 +61,24 @@ SECTIONS

__image_copy_end = .;

+ .rel_dyn_start : {
+ __rel_dyn_base = .;
+ *(.__rel_dyn_start);
+ }
+
.rel.dyn : {
- __rel_dyn_start = .;
*(.rel*)
- __rel_dyn_end = .;
+ }
+
+ .rel_dyn_end : {
+ *(.__rel_dyn_end);
+ }
+
+ .dynsym_start : {
+ *(.__dynsym_start);
}

.dynsym : {
- __dynsym_start = .;
*(.dynsym)
}

@@ -76,7 +86,7 @@ SECTIONS

_end = .;

- .bss __rel_dyn_start (OVERLAY) : {
+ .bss __rel_dyn_base (OVERLAY) : {
__bss_start = .;
*(.bss*)
. = ALIGN(4);
--
1.7.10.4