From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?utf-8?Q?Beno=C3=AEt_Th=C3=A9baudeau?= Date: Tue, 14 Aug 2012 20:43:47 +0200 (CEST) Subject: [U-Boot] [PATCH] Fix mx31_decode_pll Message-ID: <1137031036.2409235.1344969827665.JavaMail.root@advansee.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de The MFN bit-field of the PLL registers represents a signed value. See the reference manual. Signed-off-by: Beno?t Th?baudeau Cc: Stefano Babic --- .../arch/arm/cpu/arm1136/mx31/generic.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx31/generic.c u-boot-4d3c95f/arch/arm/cpu/arm1136/mx31/generic.c index 8873fb7..3a35bfa 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx31/generic.c +++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx31/generic.c @@ -22,6 +22,7 @@ */ #include +#include #include #include #include @@ -30,16 +31,17 @@ static u32 mx31_decode_pll(u32 reg, u32 infreq) { u32 mfi = GET_PLL_MFI(reg); - u32 mfn = GET_PLL_MFN(reg); + s32 mfn = GET_PLL_MFN(reg); u32 mfd = GET_PLL_MFD(reg); u32 pd = GET_PLL_PD(reg); mfi = mfi <= 5 ? 5 : mfi; + mfn = mfn >= 512 ? mfn - 1024 : mfn; mfd += 1; pd += 1; - return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) / - (mfd * pd)) << 10; + return lldiv(2 * (u64)infreq * (mfi * mfd + mfn), + mfd * pd); } static u32 mx31_get_mpl_dpdgck_clk(void)