[U-Boot-Users] [PATCH 00/10 v3]: Add mpc7448hpc2 (Taiga) board support

Zang Roy-r61911
2006-11-02T09:27:20Z

This serial of patches have been submitted on 11, Aug., 2006.
I wait for more than two months. there is no feedback, positive or
negative.

I updated the patches based on the current u-boot git tree.
I hope I will not wait for so long time again.
Any feedback is welcomed. I'd like to refine the code according to your
warm comments.

This series of patches add mpc7448hpc2 board support.
Mpc7448hpc2 (taiga) board is a high-performance PowerPC server reference
design,which is optimized for high speed throughput between the
processor and the memory, disk drive and Ethernet port subsystems.

The board is designed to the micro-ATX chassis, allowing it to be used
in 1U or 2U rack-mount chassis

----------------------------------------------------------------------

Add README file for mpc7448hpc2 board.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
---
doc/README.mpc7448hpc2 | 193 ++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 193 insertions(+), 0 deletions(-)

diff --git a/doc/README.mpc7448hpc2 b/doc/README.mpc7448hpc2
new file mode 100644
index 0000000..5142a0f
--- /dev/null
+++ b/doc/README.mpc7448hpc2
@@ -0,0 +1,193 @@
+Freescale MPC7448hpc2 (Taiga) board
+===================================
+
+Created 08/11/2006 Roy Zang
+--------------------------
+MPC7448hpc2 (Taiga) board is a high-performance PowerPC server reference
+design, which is optimized for high speed throughput between the processor and
+the memory, disk drive and Ethernet port subsystems.
+
+MPC7448hpc2(Taiga) is designed to the micro-ATX chassis, allowing it to be
+used in 1U or 2U rack-mount chassisol and CPU Reset Option
+
+ 7
+ -
+ SW2=0 System bus uses MPX bus protocol
+ SW2=1 System bus uses 60x bus protocol
+
+ 8
+ -
+ SW2=0 TSI108 can cause CPU reset
+ SW2=1 TSI108 can not cause CPU reset
+
+
+SW3[1-8] system options
+
+ 123
+ ---
+ SW3=xxx Connected to GPIO[0:2] on TSI108
+
+ 4
+ -
+ SW3=0 CPU boots from low half of flash
+ SW3=1 CPU boots from high half of flash
+
+ 5
+ -
+ SW3=0 SATA and slot2 connected to PCI bus
+ SW3=1 Only slot1 connected to PCI bus
+
+ 6
+ -
+ SW3=0 USB connected to PCI bus
+ SW3=1 USB disconnected from PCI bus
+
+ 7
+ -
+ SW3=0 Flash is write protected
+ SW3=1 Flash is NOT write protected
+
+ 8
+ -
+ SW3=0 CPU will boot from flash
+ SW3=1 CPU will boot from PromJet
+
+SW4[1-3]: System bus frequency
+
+ Bus Frequency (MHz)
+ ---
+ SW4=010 183
+ SW4=011 100
+ SW4=100 133
+ SW4=101 166 only for MPC7447A
+ SW4=110 200 only for MPC7448
+ others reserved
+
+
+SW4[4-6]: DDR2 SDRAM frequency
+
+ Bus Frequency (MHz)
+ ---
+ SW4=000 external clock
+ SW4=011 system clock
+ SW4=100 133
+ SW4=101 166
+ SW4=110 200
+ others reserved
+
+
+SW4[7-8]: PCI/PCI-X frequency control
+ 7
+ -
+ SW4=0 PCI/PCI-X bus operates normally
+ SW4=1 PCI bus forced to PCI-33 mode
+
+ 8
+ -
+ SW4=0 PCI-X mode at 133 MHz allowed
+ SW4=1 PCI-X mode limited to 100 MHz
+
--
1.4.0