From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jon Loeliger <jdl@freescale.com>
Date: Thu, 17 May 2007 10:35:10 -0500
Subject: [U-Boot-Users] CFG_MONITOR_BASE < CFG_FLASH_BASE
In-Reply-To: <464B8F93.7010005@freescale.com>
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On Wed, 2007-05-16 at 18:11, Timur Tabi wrote:

> Can you give me some details as to how this works?  I'm trying to figure out if this 
> approach is meaningful for boards based on Freescale 8xxx CPUs.  I'm guessing it's not, 
> and that the code I see in the board header files is some left-over legacy from a 
> completely different CPU that no one ever bothered to think about.

Timur,

There are test-bed environments, for example, that are capable
of setting up some LAWs, configuring DDR, and injecting a new
test image into RAM via a JTAG or scan device.  From there it
is an obvious "boot from RAM" situation useful for rapid turn
testing.

jdl