* [U-Boot-Users] [PATCH] mpc83xx: Correct the burst length for DDR2 with 32 bits
@ 2007-08-01 6:01 Dave Liu
2007-08-04 5:34 ` Dave Liu
0 siblings, 1 reply; 2+ messages in thread
From: Dave Liu @ 2007-08-01 6:01 UTC (permalink / raw)
To: u-boot
The burst length should be 4 for DDR2 with 32 bits bus
Signed-off-by: Dave Liu<daveliu@freescale.com>
---
cpu/mpc83xx/spd_sdram.c | 8 ++++++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 647813f..5e89add 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -730,8 +730,12 @@ long int spd_sdram()
sdram_cfg |= 0x10000000;
/* The DIMM is 32bit width */
- if (spd.dataw_lsb == 0x20)
- sdram_cfg |= 0x000C0000;
+ if (spd.dataw_lsb == 0x20) {
+ if (spd.mem_type == SPD_MEMTYPE_DDR)
+ sdram_cfg |= 0x000C0000;
+ if (spd.mem_type == SPD_MEMTYPE_DDR2)
+ sdram_cfg |= 0x00080000;
+ }
ddrc_ecc_enable = 0;
--
1.5.3.rc2.29.gc4640f
^ permalink raw reply related [flat|nested] 2+ messages in thread* [U-Boot-Users] [PATCH] mpc83xx: Correct the burst length for DDR2 with 32 bits
2007-08-01 6:01 [U-Boot-Users] [PATCH] mpc83xx: Correct the burst length for DDR2 with 32 bits Dave Liu
@ 2007-08-04 5:34 ` Dave Liu
0 siblings, 0 replies; 2+ messages in thread
From: Dave Liu @ 2007-08-04 5:34 UTC (permalink / raw)
To: u-boot
Sorry for that, the patch only fix bottom half.
I will resend the new patch.
Thanks,
Dave
On Wed, 2007-08-01 at 14:01 +0800, Dave Liu wrote:
> The burst length should be 4 for DDR2 with 32 bits bus
>
> Signed-off-by: Dave Liu<daveliu@freescale.com>
> ---
> cpu/mpc83xx/spd_sdram.c | 8 ++++++--
> 1 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
> index 647813f..5e89add 100644
> --- a/cpu/mpc83xx/spd_sdram.c
> +++ b/cpu/mpc83xx/spd_sdram.c
> @@ -730,8 +730,12 @@ long int spd_sdram()
> sdram_cfg |= 0x10000000;
>
> /* The DIMM is 32bit width */
> - if (spd.dataw_lsb == 0x20)
> - sdram_cfg |= 0x000C0000;
> + if (spd.dataw_lsb == 0x20) {
> + if (spd.mem_type == SPD_MEMTYPE_DDR)
> + sdram_cfg |= 0x000C0000;
> + if (spd.mem_type == SPD_MEMTYPE_DDR2)
> + sdram_cfg |= 0x00080000;
> + }
>
> ddrc_ecc_enable = 0;
>
^ permalink raw reply [flat|nested] 2+ messages in thread
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