From mboxrd@z Thu Jan 1 00:00:00 1970 From: Matthias Fuchs Date: Mon, 12 Nov 2007 18:19:00 +0100 Subject: [U-Boot-Users] [PATCH] Fix MSB check in Xilinx Spartan slave serial mode In-Reply-To: <1194887941159-git-send-email-matthias.fuchs@esd-electronics.com> References: <1194887941159-git-send-email-matthias.fuchs@esd-electronics.com> Message-ID: <11948879422702-git-send-email-matthias.fuchs@esd-electronics.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Signed-off-by: Matthias Fuchs --- common/spartan2.c | 4 ++-- common/spartan3.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/common/spartan2.c b/common/spartan2.c index 724ad0d..2f1ea2c 100644 --- a/common/spartan2.c +++ b/common/spartan2.c @@ -441,7 +441,7 @@ static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns; int i; - char val; + unsigned char val; PRINTF ("%s: start with interface functions @ 0x%p\n", __FUNCTION__, fn); @@ -516,7 +516,7 @@ static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) (*fn->clk) (FALSE, TRUE, cookie); CONFIG_FPGA_DELAY (); /* Write data */ - (*fn->wr) ((val < 0), TRUE, cookie); + (*fn->wr) ((val & 0x80), TRUE, cookie); CONFIG_FPGA_DELAY (); /* Assert the clock */ (*fn->clk) (TRUE, TRUE, cookie); diff --git a/common/spartan3.c b/common/spartan3.c index 20edc0c..d329e70 100644 --- a/common/spartan3.c +++ b/common/spartan3.c @@ -446,7 +446,7 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns; int i; - char val; + unsigned char val; PRINTF ("%s: start with interface functions @ 0x%p\n", __FUNCTION__, fn); @@ -521,7 +521,7 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) (*fn->clk) (FALSE, TRUE, cookie); CONFIG_FPGA_DELAY (); /* Write data */ - (*fn->wr) ((val < 0), TRUE, cookie); + (*fn->wr) ((val & 0x80), TRUE, cookie); CONFIG_FPGA_DELAY (); /* Assert the clock */ (*fn->clk) (TRUE, TRUE, cookie); -- 1.5.3